KR102556601B1 - Display device - Google Patents

Abstract

A display device includes a first substrate including a display area and a non-display area surrounding the display area, a plurality of pixels disposed on the display area of the first substrate, and a non-display area adjacent to one side of the first substrate. A gate driver disposed on and connected to the pixels, a data driver connected to the first substrate and connected to the pixels, disposed between the one side of the first substrate and the gate driver and connected to the gate driver, a receiving first voltage wire, and a second voltage wire disposed between the one side of the first substrate and the gate driver and adjacent to the one side of the first substrate than the first voltage wire; A voltage wire receives a compensation voltage having a different voltage level from the low voltage, and a lower end of the second voltage wire is connected to a lower end of the first voltage wire.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device capable of maintaining a constant gate-off voltage level.

In general, a display device includes a plurality of pixels, a gate driver applying a plurality of gate signals to the pixels, and a data driver applying a plurality of data voltages to the pixels. The gate driver generates gate signals in response to the gate control signal, and the data driver generates data voltages in response to the data control signals.

The gate driver may receive a low voltage and determine low levels of the gate signals using the low voltage. The gate driver includes a plurality of stages for generating gate signals, and the stages are dependently connected to each other and sequentially activated.

The low voltage is connected to the stages through power wiring. A normal low voltage may be applied to the first stage. However, in the final stage, a voltage drop occurs in the low voltage due to resistance of the power wiring, so that the normal low voltage may not be applied.

An object of the present invention is to provide a display device capable of maintaining a constant gate-off voltage level.

A display device according to an exemplary embodiment of the present invention includes a first substrate including a display area and a non-display area surrounding the display area, a plurality of pixels disposed on the display area of the first substrate, and the first substrate. A gate driver disposed in a non-display area adjacent to one side of a substrate and connected to the pixels, a data driver connected to the first substrate and connected to the pixels, and disposed between the one side of the first substrate and the gate driver to A first voltage wire connected to the gate driver and receiving a low voltage, and a second voltage wire disposed between the one side of the first substrate and the gate driver, and closer to the one side of the first substrate than the first voltage wire. and a wiring, wherein the second voltage wiring receives a compensation voltage having a voltage level different from that of the low voltage, and a lower end of the second voltage wiring is connected to a lower end of the first voltage wiring.

A display device according to an exemplary embodiment of the present invention includes a first substrate, a plurality of pixels disposed on the first substrate, a plurality of gate driving chips connected to one side of the first substrate and connected to the pixels, and the first substrate. 1 a data driver connected to an upper end of a substrate and connected to the pixels, a first voltage line disposed adjacent to the one side of the first substrate and connected to the gate driving chips and receiving a low voltage, and the first voltage line and a second voltage line disposed adjacent to and receiving a compensation voltage having a voltage level lower than the low voltage, the second voltage line being spaced apart from the gate driving chips more than the first voltage line, and the second voltage line being spaced apart from the gate driving chips. A lower end of the voltage wire is connected to a lower end of the first voltage wire.

The level of the gate-off voltage of the display device according to the exemplary embodiment of the present invention may be maintained constant.

1 is a plan view of a display device according to an exemplary embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of one pixel shown in FIG. 1 .
FIG. 3 is a diagram showing the configuration of the gate driver shown in FIG. 1 .
FIG. 4 is an enlarged view of a portion of the first substrate on which the stages shown in FIG. 3 are disposed.
5 is a diagram illustrating a timing diagram of gate signals, a low voltage, and a compensation voltage by way of example.
6 is a diagram illustrating a display device according to another exemplary embodiment of the present invention.

In this specification, when an element (or region, layer, section, etc.) is referred to as being “on,” “connected to,” or “coupled to” another element, it is directly placed/placed on the other element. It means that they can be connected/combined or a third component may be placed between them.

Like reference numerals designate like components. Also, in the drawings, the thickness, ratio, and dimensions of components are exaggerated for effective description of technical content.

“And/or” includes any combination of one or more that the associated elements may define.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

In addition, terms such as "below", "lower side", "above", and "upper side" are used to describe the relationship between components shown in the drawings. The above terms are relative concepts and will be described based on the directions shown in the drawings.

Unless defined otherwise, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In addition, terms such as terms defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning in the context of the related art, and are not explicitly defined herein unless interpreted in an ideal or overly formal sense. It's possible.

Terms such as "include" or "have" are intended to indicate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but that one or more other features, numbers, or steps are present. However, it should be understood that it does not preclude the possibility of existence or addition of operations, components, parts, or combinations thereof.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a plan view of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a display device 500 according to the present invention may include a display panel 100 , a gate driver 200 , a data driver 300 , and a printed circuit board 400 . The display panel 100 may have a rectangular shape having long sides in a first direction DR1 and short sides in a second direction DR2 crossing the first direction DR1 .

The display panel 100 includes a first substrate 110, a second substrate 120 facing the first substrate 110, and a liquid crystal layer disposed between the first substrate 110 and the second substrate 120 ( not shown). The first and second substrates 110 and 120 may have a rectangular shape having long sides in the first direction DR1 and short sides in the second direction DR2 .

For example, the display panel 100 may be a liquid crystal display panel including a liquid crystal layer. However, it is not limited thereto, and various display panels capable of displaying images such as an electrophoretic display panel, an electrowetting display panel, or an organic light emitting display panel may be used as the display panel 100 .

The display panel 100 may include a plurality of gate lines GL1 to GLm, a plurality of data lines DL1 to DLn, and a plurality of pixels PX11 to PXmn. m and n are integers greater than zero. The gate lines GL1 to GLm and the data lines DL1 to DLn may be disposed on the first substrate 110 . The gate lines GL1 to GLm and the data lines DL1 to DLn may be insulated from each other and may be arranged to cross each other.

A flat area of the display panel 100 may include a display area DA displaying an image and a non-display area NDA disposed to surround the display area DA and not displaying an image. Like the display panel 100 , the first substrate 110 and the second substrate 120 may also include a display area DA and a non-display area NDA.

The gate lines GL1 to GLm may extend in the first direction DR1 and be connected to the gate driver 200 . The data lines DL1 to DLn may extend in the second direction DR2 and be connected to the data driver 300 .

The pixels PX11 to PXmn may be arranged in a matrix form and disposed in the display area DA. For example, the pixels PX11 to PXmn may be disposed in regions partitioned by gate lines GL1 to GLm and data lines DL1 to DLn that cross each other.

The pixels PX11 to PXmn may be connected to gate lines GL1 to GLm and data lines DL1 to DLn. Each of the pixels PX11 to PXmn may display one of the primary colors. Primary colors may include red, green, blue, and white colors. However, it is not limited thereto, and the main color may further include various colors such as yellow, cyan, and magenta.

The gate driver 200 may be disposed in the non-display area NDA adjacent to one side of the display area DA in the first direction DR1. Specifically, the gate driver 200 may be disposed in the non-display area NDA between one side of the first substrate 110 and the display area DA. One side of the first substrate 110 may be defined as one of short sides of the first substrate 110 .

The gate driver 200 is formed at the same time as the transistors of the pixels PX11 to PXmn through the same process as the first substrate 110 in the form of an amorphous silicon TFT gate driver circuit (ASG) or oxide silicon TFT gate driver circuit (OSG). ) can be mounted.

The data driver 300 may include a plurality of source driving chips 310 . The source driving chips 310 are disposed on the plurality of flexible circuit boards 320 and are provided on the printed circuit board 400 and the first substrate 110 in the non-display area NDA adjacent to the upper side of the display area DA. can be connected That is, the data driver 300 may be connected to the display panel 100 in a tape carrier package (TCP) method.

A timing controller 410 may be disposed on the printed circuit board 400 . The timing controller 410 may be mounted on the printed circuit board 400 in the form of an integrated circuit chip and connected to the gate driver 200 and the data driver 300 . The timing controller 410 may output a gate control signal, a data control signal, and image data.

The timing controller 410 and the source driving chips 310 may be connected through first signal lines SL1. The timing controller 410 and the gate driver 200 may be connected through a second signal line SL2. The second signal line SL2 may be connected to the gate driver 200 via the leftmost flexible circuit board 320 among the flexible circuit boards 320 . Although not shown, each of the first signal wires SL1 and the second signal wire SL2 may include a plurality of wires.

The data driver 300 receives image signals and a data control signal from the timing controller 410 . Image signals and data control signals may be provided to the data driver 300 through the first signal lines SL1. The data driver 300 may generate analog data voltages corresponding to image signals in response to a data control signal. Data voltages may be provided to the pixels PX11 to PXmn through the data lines DL1 to DLn.

The gate driver 200 may receive a gate control signal from the timing controller 410 . The gate control signal may be provided to the gate driver 200 through the second signal line SL2. The gate driver 200 may generate a plurality of gate signals in response to a gate control signal. Gate signals may be sequentially output. The gate signals may be provided to the pixels PX11 to PXmn in a row unit through the gate lines GL1 to GLm. As a result, the pixels PX11 to PXmn may be driven in units of rows.

The pixels PX11 to PXmn may receive data voltages through the data lines DL1 to DLn in response to the gate signals provided through the gate lines GL1 to GLm. The pixels PX11 to PXmn display gray levels corresponding to the data voltages, and as a result, an image can be displayed.

FIG. 2 is an equivalent circuit diagram of one pixel shown in FIG. 1 .

For convenience of explanation, a pixel PX11 connected to the first gate line GL1 and the first data line DL1 is illustrated in FIG. 2 . Although not shown, configurations of other pixels of the display panel 100 may be substantially the same as those of the pixel PX11 shown in FIG. 2 .

Referring to FIG. 2 , the display panel 100 includes a first substrate 110, a second substrate 120 facing the first substrate 110, and a space between the first substrate 110 and the second substrate 120. It may include a liquid crystal layer (LC) disposed on.

The pixel PX11 includes a transistor TR connected to the first gate line GL1 and the first data line DL1, a liquid crystal capacitor Clc connected to the transistor TR, and a storage connected in parallel to the liquid crystal capacitor Clc. A capacitor Cst may be included. The storage capacitor Cst may be omitted.

The transistor TR may include a gate electrode connected to the first gate line GL1, a source electrode connected to the first data line DL1, and a drain electrode connected to the liquid crystal capacitor Clc and the storage capacitor Cst. .

The liquid crystal capacitor Clc is formed between the pixel electrode PE disposed on the first substrate 110, the common electrode CE disposed on the second substrate 120, and between the pixel electrode PE and the common electrode CE. A disposed liquid crystal layer LC may be included. The liquid crystal layer LC may serve as a dielectric. The pixel electrode PE may be connected to the drain electrode of the transistor TR.

In FIG. 2 , the pixel electrode PE has a non-slit structure, but is not limited thereto, and may have a slit structure including a cross-shaped stem portion and a plurality of branch portions radially extending from the stem portion. there is.

The common electrode CE may be entirely formed on the second substrate 120 . However, it is not limited thereto, and the common electrode CE may be disposed on the first substrate 110 . In this case, at least one of the pixel electrode PE and the common electrode CE may include a slit.

The storage capacitor Cst may include a pixel electrode PE, a storage electrode (not shown) branched from a storage line (not shown), and an insulating layer disposed between the pixel electrode PE and the storage electrode. . The storage line is disposed on the first substrate 110 and may be simultaneously formed on the same layer as the gate lines GL1 to GLm. The storage electrode may partially overlap the pixel electrode PE.

The pixel PX may further include a color filter CF representing one of the main colors. As an exemplary embodiment, the color filter CF may be disposed on the second substrate 120 as shown in FIG. 2 . However, it is not limited thereto, and the color filter CF may be disposed on the first substrate 110 .

The transistor TR may be turned on in response to a gate signal provided through the first gate line GL1. The data voltage received through the first data line DL1 may be provided to the pixel electrode PE of the liquid crystal capacitor Clc through the turned-on transistor TR. A common voltage may be applied to the common electrode CE.

An electric field may be formed between the pixel electrode PE and the common electrode CE due to a difference in voltage levels between the data voltage and the common voltage. Liquid crystal molecules of the liquid crystal layer LC may be driven by an electric field formed between the pixel electrode PE and the common electrode CE. An image may be displayed by controlling light transmittance by the driven liquid crystal molecules. Although not shown, a backlight unit for providing light to the display panel 100 may be disposed behind the display panel 100 .

A storage voltage having a constant voltage level may be applied to the storage line. However, the storage line is not limited thereto, and a common voltage may be applied to the storage line. The storage capacitor Cst may play a role of supplementing the charge amount of the liquid crystal capacitor Clc.

FIG. 3 is a diagram showing the configuration of the gate driver shown in FIG. 1 .

Referring to FIG. 3 , the gate driver 200 may include first to m+1th stages SRC1 to SRCm+1 that are cascadedly connected. The first to mth stages SRC1 to SRCm may be electrically connected to the first to mth gate lines GL1 to GLm. The m+1th stage (SRCm+1) may be defined as a dummy stage.

The first to mth stages SRC1 to SRCm may generate a plurality of first to mth gate signals GS1 to GSm. The first to mth stages SRC1 to SRCm may be sequentially activated to sequentially output the first to mth gate signals GS1 to GSm. The first to m th gate signals GS1 to GSm may be provided to the pixels PX11 to PXmn through the first to m th gate lines GL1 , ..., GLm.

The first to m+1th stages SRC1 to SRCm+1 include a first clock terminal CK1, a second clock terminal CK2, a voltage terminal VT, a reset terminal RE, and a control terminal CT, respectively. , a carry terminal (CR), an output terminal (OUT), and an input terminal (IN). Clock signals having phases opposite to each other may be provided to the first clock terminal CK1 and the second clock terminal CK2 , respectively.

The first clock signal CKV is applied to the first clock terminals CK1 of the odd-numbered stages SRC1, SRC3, ..., SRCm-1, and the odd-numbered stages SRC1, SRC3, ... , SRCm−1), the second clock signal CKVB having an opposite phase to the first clock signal CKV may be provided to the second clock terminals CK2. The second clock signal CKVB is provided to the first clock terminals CK1 of the even-numbered stages SRC2, SRC4, ..., SRCm, and the even-numbered stages SRC2, SRC4, ..., SRCm ) may be provided with the first clock signal CKV to the second clock terminals CK2 .

The vertical start signal STV may be provided to the input terminal IN of the first stage SRC1 and the control terminal CT of the dummy stage SRCm+1. A carry signal output from the carry terminal CR of the previous stage may be provided to the input terminals IN of the second to m+1th stages SRC2 to SRCm+1, respectively. A carry signal output from the carry terminal CR may serve to drive the next stage.

A gate signal output through the output terminal OUT of the next stage may be provided to the control terminals CT of the first to mth stages SRC1 to SRCm, respectively. The low voltage VSS may be provided to the off voltage terminals VT of the first to m+1th stages SRC1 to SRCm+1. The carry signal output from the carry terminal CR of the dummy stage SRCm+1 may be commonly provided to the reset terminals RE of the first to m+1th stages SRC1 to SRCm+1.

The output terminals OUT of the first to m+1th stages SRC1 to SRCm+1 may output the high level section of the clock signal provided to the first clock terminal CK1. For example, the output terminals OUT of the odd-numbered stages SRC1, SRC3, ..., SRCm-1, SRCm+1 output the high level period of the first clock signal CKV, and the even-numbered stages The output terminals OUT of the stages SRC2 , SRC4 , ..., and SRCm may output the high level period of the second clock signal CKVB.

In one frame, each of the first to m th gate signals GS1 to GSm may be one pulse signal, and the first to m th gate signals GS1 to GSm may be output without overlapping each other. A high level of each of the first and second clock signals CKV and CKVB is a gate-on voltage for driving the pixels PX11 to PXmn, and a low level of each of the first and second clock signals CKV and CKVB The level may be a gate-off voltage for turning off the pixels PX11 to PXmn.

The low voltage VSS may determine the level of the gate-off voltage. The carry terminals CR of the first to m+1th stages SRC1 to SRCm+1 output a carry signal based on the same clock signal as the clock signal output from the output terminal OUT.

The second signal line SL2 may include a first voltage line VL1 , a second voltage line VL2 , and a plurality of control signal lines CL. The control signal wires CL may receive the first and second clock signals CKV and CKVB and the start signal STV. The control signal lines CL provide the first and second clock signals CKV and CKVB and the start signal STV to the first to m+1th stages SRC1 to SRCm+1. to the m+1th stages SRC1 to SRCm+1.

The control signal lines CL may include first, second, and third control signal lines CL1 , CL2 , and CL3 . The first control signal line CL1 may be connected to the first and m+1th stages SRC1 and SRCm+1. The second control signal line CL2 connects first clock terminals CK1 of odd-numbered stages SRC1, SRC3, ..., SRCm-1, SRCm+1 and even-numbered stages SRC2, SRC4,. .., SRCm) may be connected to the second clock terminals CK2. The third control signal wire CL2 connects second clock terminals CK2 of odd-numbered stages SRC1, SRC3, ..., SRCm-1, SRCm+1 and even-numbered stages SRC2, SRC4,. .., SRCm) may be connected to the first clock terminals CK1.

The first voltage line VL1 may receive the low voltage VSS. The first voltage line VL1 may be connected to voltage terminals VT of the first to m+1th stages SRC1 to SRCm+1.

The second voltage line VL2 may receive the compensation voltage VC. A lower end of the second voltage line VL2 may be connected to a lower end of the first voltage line VL1 . The compensation voltage VC is applied between each of the first to m th gate signals GS1 to GSm of the first frame and each of the first to m th gate signals GS1 to GSm of the second frame following the first frame. The gate-off voltage may be maintained at a constant level. This configuration will be described in detail below.

FIG. 4 is an enlarged view of a portion of the first substrate on which the stages shown in FIG. 3 are disposed.

5 is a diagram illustrating a timing diagram of gate signals, a low voltage, and a compensation voltage by way of example.

For convenience of description, the control signal lines CL are shown as a single line, and the second substrate 120 is omitted.

Referring to FIG. 4 , the first to m+1th stages SRC1 to SRCm+1 may be arranged in the second direction DR2. The first voltage line VL1 and the second voltage line VL2 may be disposed between the gate driver 200 and one side of the first substrate 110 . The second voltage line VL2 may be disposed closer to one side of the first substrate 110 than the first voltage line VL1 . One side of the first substrate 110 may be parallel to the second direction DR2. The first voltage line VL1 may be connected to the first to m+1th stages SRC1 to SRCm+1.

The first voltage line VL1 may receive the low voltage VSS, and the second voltage line VL2 may receive a compensation voltage having a different level from that of the low voltage VSS. The first and second voltage wires VL1 and VL2 may extend to the first board 110 via the leftmost flexible circuit board 320 among the flexible circuit boards 320 . The first and second voltage wires VL1 and VL2 are disposed adjacent to the gate driver 110 on the first substrate 110 and may extend in the second direction DR2 .

As described above, the lower end of the second voltage line VL2 may be connected to the lower end of the first voltage line VL1. The lower end of the first voltage line VL1 and the lower end of the second voltage line VL2 are the m+1th stage (SRCm+1), which is the last stage among the first to m+1th stages (SRC1 to SRCm+1). can be placed adjacent to.

Referring to FIGS. 4 and 5 , the first to mth stages SRC1 to SRCm may sequentially output gate signals GS1 to GSm in every frame 1F and 2F. Illustratively, gate signals GS1, GSk, and GSm output from the first stage SRC1, the kth stage SRCk, and the mth stage SRCm are illustrated. k is a natural number greater than 1 and less than m. The low voltage VSS may be provided to the first to mth stages SRC1 to SRCm through the first voltage line VL1.

The voltage level of the low voltage VSS may vary according to the voltage drop of the first voltage line VL1. For example, since the resistance of a wire is inversely proportional to the thickness of the wire and proportional to the length of the wire, the longer the wire, the greater the voltage drop. When the voltage level is positive, the voltage drop may be defined as a phenomenon in which the voltage level decreases toward the ground voltage VGND. When the voltage level is negative, the voltage drop may be defined as a phenomenon in which the voltage level increases toward the ground voltage VGND.

The low voltage VSS may have a voltage level lower than the ground voltage. That is, the low voltage VSS may have a negative voltage level. When the low voltage VSS applied to the first voltage line VL1 maintains a constant voltage level, the following problems may occur.

The low voltage VSS in a portion of the first voltage line VL1 adjacent to the first stage SRC1 may normally have the first voltage level -V1. However, since the voltage drop increases toward the lower end of the first voltage line VL1, the voltage level of the low voltage VSS may increase toward the ground voltage VGND toward the lower end of the first voltage line VL1.

Therefore, even if the low voltage VSS applied to the first voltage line VL1 has a constant voltage level, the low voltage VSS is at the lower portion of the first voltage line VL1 adjacent to the mth stage SRCm. It may have a voltage level higher than 1 voltage level (-V1).

As described above, the first to mth stages SRC1 to SRCm may be sequentially activated. In the start section of one frame (1F or 2F), the low voltage VSS applied to the first stage SRC1 may have a normal first voltage level (−V1). However, the voltage drop may increase toward the lower end of the first voltage line VL1. Accordingly, the low voltage VSS having a voltage level gradually higher than the first voltage level -V1 may be applied to the second to mth stages SRC1 to SRCm.

In the last section of one frame (1F or 2F), a low voltage (VSS) having a higher voltage level than the first voltage level (-V1) may be applied to the mth stage (SRCm). In this case, a normal gate signal may not be generated.

To solve this problem, as shown in FIG. 5 , the level of the low voltage VSS may be changed to gradually decrease in one frame (1F or 2F). For example, the low voltage VSS having the first voltage level -V1 may be applied to the first stage SRC1 adjacent to the first voltage line VL1 having a relatively low voltage drop.

The low voltage (VSS) is gradually lowered in one frame (1F or 2F), and in the last section of one frame (1F or 2F), the low voltage (VSS) is at a second voltage level (-V2) lower than the first voltage level (-V1). ) can have. In this case, even if a voltage drop occurs in the first voltage line VL1, the low voltage VSS is at the second voltage level due to the voltage drop at the lower portion of the first voltage line VL1 adjacent to the mth stage SRCm. It may increase from (-V2) to the first voltage level (-V1).

Substantially, the low voltage VSS having the normal first voltage level -V1 may be applied to the mth stage SRCm despite the voltage drop of the first voltage line VL1. Although the low voltage VSS applied to the mth stage SRCm has been exemplarily described, the normal low voltage VSS may also be applied to the second to m−1th stages SRC2 to SRCm−1.

Each of the gate signals GS1 to GSm may include a gate-on voltage VON and a gate-off voltage VOFF having a lower level than the gate-on voltage VON. The low voltage (VSS) may determine the gate off (VOFF). However, since the level of the low voltage VSS is gradually changed to decrease, there is a gap between each of the gate signals GS1 to GSm of the first frame 1F and each of the gate signals GS1 to GSm of the second frame 2F. The level of the gate-off voltage VOFF of may change according to the change of the low voltage VSS.

The level of the gate-off voltage VOFF is not maintained constant and may change to a level indicated by a dotted line in the gate signals GS1 to GSm. When the level of the gate-off voltage VOFF is not maintained constant, kickback voltages of the transistors of the pixels PX11 to PXmn may change, resulting in afterimage problems.

In an embodiment of the present invention, the compensation voltage VC may be used to keep the level of the gate-off voltage VOFF constant. The compensation voltage VC may have a negative voltage level lower than the ground voltage VGND. Since the level of the low voltage VSS gradually decreases in one frame (1F or 2F), the level of the compensation voltage VC is gradually increased in one frame (1F or 2F) to offset the voltage level change. can

Specifically, the compensation voltage VC may have a different level from the low voltage VSS. A voltage drop may also occur in the second voltage line VL2 . Accordingly, the compensation voltage VC may be determined considering the voltage drop. In consideration of the voltage drop, the compensation voltage VC applied to the second voltage line VL2 is applied to the second voltage line VL2 so that the lower end of the second voltage line VL2 has the second voltage level (-V2). ) may have a third voltage level (-V3) having a lower level.

The level of the compensation voltage VC may gradually increase from the third voltage level -V3 to the fourth voltage level -V4 during one frame (1F or 2F). A change in the voltage level of the low voltage VSS is offset by the compensation voltage VC, so that the level of the gate-off voltage VOFF can be maintained constant.

As a result, the display device 500 according to an exemplary embodiment of the present invention can maintain a constant level of the gate-off voltage VOFF.

6 is a diagram illustrating a display device according to another exemplary embodiment of the present invention.

For convenience of description, FIG. 6 is a plan view corresponding to the plan view of the first substrate 110 shown in FIG. 4 , and pixels PX11 to PXmn and gate lines GL1 to GLm are omitted. It became.

Except for the configurations of the gate driver 210 and the first and second voltage wires VL1' and VL2', a display device according to another exemplary embodiment of the present invention is the same as the display device 500 shown in FIG. have a configuration Therefore, the configuration of the gate driver 210 and the first and second voltage wires VL1' and VL2' is mainly based on the configurations different from those of the gate driver 200 and the first and second voltage wires VL1 and VL2. will be described, and like elements are shown using like reference numerals.

Referring to FIG. 6 , the gate driver 210 includes a plurality of gate driving chips 211 , and the gate driving chips 211 may be connected to one side of the first substrate 110 . For example, the gate driving chips 211 may be respectively disposed on a plurality of flexible circuit films 212 , and the flexible circuit films 212 may be connected to one side of the first substrate 110 . The gate driving chips 211 may be connected to one side of the first substrate 110 through the flexible circuit films 212 .

Although not shown, the gate lines GL1 to GLm may extend in the first direction DR1 and be connected to the gate driving chips 211 via the flexible circuit films 212 .

The first voltage line VL1 ′ may be disposed adjacent to one side of the first substrate 110 and connected to the gate driving chips 211 via the flexible circuit films 212 . The second voltage line VL2' may be spaced further from the gate driving chips 211 than the first voltage line VL1'. The second voltage line VL2' extends in the second direction DR2, and a lower end of the second voltage line VL2' may be connected to a lower end of the first voltage line VL1'.

The voltage level of the low voltage VSS and the voltage level of the compensation voltage VC applied to the first and second voltage wires VL1' and VL2' may be substantially as shown in FIG. 5 .

Although described with reference to the above embodiments, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the present invention described in the claims below. You will be able to. In addition, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, and all technical ideas within the scope of the following claims and their equivalents should be construed as being included in the scope of the present invention. .

500: display device 100: display panel
200: gate driver 300: data driver
310: source driving chip 320: flexible circuit board
400: printed circuit board 410: timing controller
211: gate driving chip 212: flexible circuit film
VL1, VL2: first and second voltage wires

Claims (11)

a first substrate including a display area and a non-display area surrounding the display area;
a plurality of pixels disposed on the display area of the first substrate;
a gate driver disposed in a non-display area adjacent to one side of the first substrate and connected to the pixels;
a data driver connected to the first substrate and connected to the pixels;
a first voltage line disposed between the one side of the first substrate and the gate driver, connected to the gate driver, and receiving a low voltage; and
a second voltage wire disposed between the one side of the first substrate and the gate driver and adjacent to the one side of the first substrate than the first voltage wire;
wherein the second voltage wire receives a compensation voltage having a voltage level different from that of the low voltage, and a lower end of the second voltage wire is connected to a lower end of the first voltage wire. According to claim 1,
Each of the first and second voltage wires extends parallel to the one side of the first substrate. According to claim 1,
The gate driver includes a plurality of stages arranged in a direction parallel to the one side of the first substrate and dependently connected to each other;
The first voltage line is connected to the stages. According to claim 3,
A lower end of the first voltage wire and a lower end of the second voltage wire are adjacent to a last stage among the stages. According to claim 3,
a plurality of gate lines extending in a first direction and connected to the stages and the pixels; and
a plurality of data lines extending in a second direction crossing the first direction and connected to the data driver and the pixels;
The one side of the first substrate is parallel to the second direction. According to claim 5,
The stages are sequentially activated to generate a plurality of gate signals, and each of the gate signals includes a gate-on voltage and a gate-off voltage lower than the gate-on voltage. According to claim 6,
The low voltage determines the gate-off voltage, and the compensation voltage maintains a level between each of the gate signals of the first frame and each of the gate signals of the second frame at a level of the gate-off voltage. According to claim 1,
The compensation voltage has a lower voltage level than the low voltage. According to claim 1,
The compensation voltage and the low voltage have negative voltage levels. According to claim 9,
The display device of claim 1 , wherein the voltage level of the low voltage gradually decreases during one frame, and the voltage level of the compensation voltage gradually increases during one frame. a first substrate;
a plurality of pixels disposed on the first substrate;
a plurality of gate driving chips connected to one side of the first substrate and connected to the pixels;
a data driver connected to an upper end of the first substrate and connected to the pixels;
a first voltage line disposed adjacent to the one side of the first substrate, connected to the gate driving chips, and receiving a low voltage; and
A second voltage wire disposed adjacent to the first voltage wire and receiving a compensation voltage having a voltage level lower than the low voltage;
The second voltage wire is spaced apart from the gate driving chips more than the first voltage wire, and a lower end of the second voltage wire is connected to a lower end of the first voltage wire.

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