KR20080051743A - Driving circuit and method for liquid crystal display device - Google Patents

Abstract

A circuit and a method for driving an LCD(Liquid Crystal Display) device are provided to reduce the size of data driver by driving simultaneously left and right pixels using one data line. A circuit for driving an LCD(Liquid Crystal Display) device includes a timing controller(21), gate and data drivers(22,23), and an LCD panel(24). The timing controller outputs gate and data control signals, and outputs image data based on the structure of pixel and the supply sequence of scan pulses when the image data on a pair of pixels, commonly connected to respective horizontal lines of one data line on the LCD panel, are outputted. The gate driver sequentially supplies scan pulses to a pair of gate lines on the LCD panel in response to the gate control signal. The data driver converts digital video data into data voltage corresponding to gray scale values in response to the data control signal and outputs the converted data voltage to the LCD panel. The LCD panel includes a pair of gate lines supplying scan pulses to the pair of pixels, which are divided into odd and even numbered pixels and connected with each other through switching elements.

Description

DRIVING CIRCUIT AND METHOD FOR LIQUID CRYSTAL DISPLAY DEVICE}

1 is a pixel structure diagram of a liquid crystal panel according to the prior art.

2 is a block diagram of a driving circuit of a liquid crystal display device according to the present invention;

3 is an explanatory diagram showing a principle of changing the output order of image data in a timing controller;

4A and 4B are timing charts of inversion data and scan pulses.

*** Description of the symbols for the main parts of the drawings ***

21: timing controller 22: gate driver

23: data driver 24: liquid crystal panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technique of a liquid crystal display device, and in particular, to simplify the structure of the gate driver by changing the structure of the pixel and the driving method, and to prevent horizontal crosstalk from occurring due to the loading of the common voltage. A drive circuit and method for a display device are provided.

In general, liquid crystal display (LCD) has a trend that the application range is gradually expanded to office automation equipment, audio / video equipment, etc. due to features such as light weight, thin, low power consumption.

The driving principle of the pixel in the IPS (In-Plane Switching Mode) structure will be described with reference to FIG. 1.

The gate driver sequentially supplies scan pulses (gate pulses) to the gate lines G1 to Gn on the liquid crystal panel in response to a gate control signal from the timing controller, whereby horizontal lines of the liquid crystal panel to which data is supplied are sequentially Is selected.

The data driver converts the digital video data RGB into a data voltage corresponding to a gray scale value in response to a data control signal from the timing controller, and the data voltage is converted into each data line D1 on the liquid crystal panel. To Dm).

The liquid crystal panel includes a plurality of pixels PXL arranged in a matrix at the intersection of the data lines D1 to Dm and the gate lines G1 to Gn, which are gates supplied to the gate lines G1 to Gn. It is driven by the on signal and the data signal supplied to the data lines D1 to Dm.

As described above, in the conventional LCD, since the data signal is supplied only to pixels existing in one vertical column through one data line on the liquid crystal panel, a number of data lines corresponding to the vertical columns are required. As a result, the number of data lines allocated to the data driver increases, thereby increasing the manufacturing cost of the data driver and reducing the size of the data driver.

In addition, when the common voltage is supplied to the pixels on the liquid crystal panel, the common voltage is supplied for each horizontal line, thereby making it difficult to stabilize the common voltage, resulting in afterimages and crosstalk.

Accordingly, an object of the present invention is to provide a driving circuit for driving both left and right pixels using one data line.

Another object of the present invention is to provide a driving circuit for supplying a common voltage for each vertical line on the liquid crystal panel by using a data line space of whether or not.

In order to achieve the above object, the present invention outputs a gate control signal and a data control signal, and outputs image data for a pair of pixels commonly connected on each horizontal line per data line on the liquid crystal panel. A timing controller for changing and outputting in order corresponding to the pixel structure and the scan pulse supply order; A gate driver for sequentially supplying scan pulses to a pair of gate lines arranged up and down for each horizontal line on the liquid crystal panel in response to a gate control signal input from the timing controller; A data driver converting digital video data into a data voltage corresponding to a gray scale value and outputting the digital video data to the liquid crystal panel in response to a data control signal input from the timing controller; The left and right pixels on each horizontal line per data line are commonly connected through the switching elements, and each pair is provided with a pair of gate lines per horizontal line in order to supply scan pulses by dividing them into odd or even numbers. Characterized in that composed of a liquid crystal panel.

Another object of the present invention to achieve the above object is to connect a pair of pixels on each horizontal line per data line through a switching element, and to provide scan pulses by dividing them into odd and excellent numbers. Arranging a pair of gate lines per horizontal line; In addition to outputting a gate control signal and a data control signal, and outputting image data for a pair of pixels commonly connected to each horizontal line per data line on a liquid crystal panel, the pixel structure and scan pulse supply order correspond to the pixel structure and scan pulse supply order. Outputting by changing the order; Supplying scan pulses sequentially to a pair of gate lines arranged up and down for each horizontal line on the liquid crystal panel in response to the gate control signal; Converting digital video data into a data voltage corresponding to a gray value in response to the data control signal and outputting the digital voltage to the liquid crystal panel; A process of sequentially outputting gate signals to a pair of gate lines arranged for each horizontal line on the liquid crystal panel, and outputting the data voltages in order of changing the image data when outputting data voltages to data lines on each horizontal line. Characterized in that consists of.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing an embodiment of a driving circuit of a liquid crystal display according to the present invention. As shown in FIG. 2, a gate control signal and a data control signal are output, and one data is displayed on the liquid crystal panel 24. A timing controller 21 for outputting image data for pixels commonly connected to the left and right sides on each horizontal line per line, in order of outputting the image data in order corresponding to the pixel structure and the scan pulse supply order; When the scan pulse is supplied to the liquid crystal panel 24 in response to the gate control signal input from the timing controller 21, a gate for sequentially supplying the scan pulses to a pair of gate lines arranged up and down per horizontal line in turn. A driving unit 22; A data driver 23 for converting digital video data into a data voltage corresponding to a gray scale value and outputting the digital video data to the liquid crystal panel 24 in response to a data control signal input from the timing controller 21; The left and right pixels on each horizontal line per common data line are commonly connected through switching elements, and they are divided into odd radii to provide a pair of gate lines up and down per horizontal line to supply the scan pulse. It will be described in detail with reference to Figures 3 and 4 attached to the operation of the present invention configured as configured with a liquid crystal panel 24 provided as follows.

In the liquid crystal panel 24, mxn pixels FXL are arranged in a matrix type. The liquid crystal panel 24 includes 1/2 x m data lines D _{1.2 to} D _(M-1) and _{(M + 1} ) and a pair of gate lines G disposed up and down per horizontal line. _{1_1} , G _{1_2 to} G ₍ N_1 ₎ , and G _{(N_2)} are vertically intersected, and a thin film transistor TFT for driving the pixel FXL is formed at each intersection thereof.

The thin film transistor TFT is turned on in response to a scan pulse supplied from the gate driver 22, and at this time, the data signal on the data lines D _{1.2 to} D _(M-1) and _{(M + 1)} is the pixel (P ₎ . FXL).

That is, the gate electrode of the thin film transistor TFT is connected to the same gate line G _{1_1} , G _{1_2 to} G ₍ N_1 ₎ , and G _{(N_2)} every horizontal line, and the source electrode of the thin film transistor TFT Each vertical line is connected to the same data lines D _{1.2 to} D _(M-1) and _{(M + 1)} . The drain electrode of the thin film transistor TFT is connected to the pixel electrode of each pixel FXL.

The thin film transistor TFT is configured to respond to the data lines D _{1.2 to} D _(M−) in response to the gate high voltage of the scan pulses supplied to the gate lines G _{1_1} , G _{1_2 to} G ₍ N_1 ₎ , and G _{(N_2)} . ₁₎ The pixel voltage supplied to _{(M + 1)} ) is charged to the pixel electrode.

In other words, the pixels FXL formed on the left and right sides of each horizontal line per data line have a common connection structure through the thin film transistor TFT. Therefore, in order to selectively drive the common connected left and right pixels FXL, a pair of gate lines G _{1_1} , G _{1_2 to} G ₍ N_1 ₎ and G _{(N_2 )} per horizontal line as described above. ₎ ) So that one gate of a pair of TFTs commonly connected is connected to the gate line on one side and the other gate is connected to the gate line on the other side.

In this structure, the driving principle of the pixel FXL on the first horizontal line will be described as follows. Here, it is assumed that pixels (subpixels) from the left on the first horizontal line are arranged in the order of " R1, G1, B1, R2, G2, B2 to RM, GM, BM ".

In this case, the R1 and G1 pixels are connected to the first data line D _1.2 through the respective TFTs, and the B1 and R2 pixels are connected to the second data line D _3.4 through the TFTs, respectively. The remaining pixels are also connected in this manner.

When the scan pulse is supplied to the first gate line G _{1_1} , the pixel voltage is supplied to the pixels of "R1, B1, G2 ..." corresponding to the odd pixel through the data line and the TFT, respectively. Subsequently, a scan pulse is supplied to the gate line G _{1_2} that is paired with the gate line G _{1_1} , and at this time, a pixel of "G1, R2, B2 ..." corresponding to the even pixel is supplied through the data line and the TFT. The pixel voltage is supplied.

Similarly, scan pulses are sequentially supplied to the upper and lower gate lines for each pixel existing in the horizontal line of the subsequent stage, and the pixel voltage is applied to the pixel corresponding to the odd or even pixel through the corresponding data line and TFT each time. Is supplied

The timing controller 21 controls the gate control signal GDC and the data driver 23 for controlling the gate driver 22 by using a vertical / horizontal synchronization signal and a clock signal supplied from a system (not shown). To generate a data control signal DDC. In addition, the timing controller 21 samples the digital video data RGB input from the system, rearranges the digital video data RGB, and supplies the data to the data driver 23.

In addition, the timing controller 21 should supply image data to the data driver 23 in the driving order of the pixels as described above. An example thereof is illustrated in FIG. 3.

That is, the timing controller 21 receives image data RD1 GD1 BD1, RD2 GD2 BD2... In a horizontal line unit from the system and outputs the image data to the first output area 21A and the second output area 21B of the line memory. Save in order. That is, it stores in the order of "RD1 BD1, GD2 RD3, ..." in the first output area 21A, and stores in order of "GD1 RD2, BD2 GD3, ..." in the second output area 21B.

Thereafter, when reading the image data, the image data stored in the first output area 21A is read in the order of "RD1 BD1, GD2 RD3, ..." as described above and output to the data driver 23, and then the first The image data stored in the two output areas 21B are read out in the order of "GD1 RD2, BD2 GD3, ..." as described above and output to the data driver 23.

The gate driver 22 transmits scan pulses (gate pulses) to gate lines G _{1_1} , G _{1_2 to} G ₍ N_1 ₎ , and G _{(N_2)} in response to the gate control signal GDC from the timing controller 21. The horizontal lines of the liquid crystal panel 24, which are sequentially supplied to the data, to which data is supplied, are selected.

That is, as shown in (b), two scan pulses are output as shown in (b) as shown in FIG.

The data driver 24 converts the digital video data RGB into a data voltage (analog gamma compensation voltage) corresponding to the gray scale value in response to the data control signal DDC input from the timing controller 21. The converted data voltage is supplied to the data lines D _{1.2 to} D _(M-1) and _{(M + 1)} on the liquid crystal panel 24.

By the way, when the data driver 24 outputs the data voltage to the liquid crystal panel 24, the data driver 24 is arranged in the order of the image data input from the timing controller 21, that is, "RD1 BD1, GD2 RD3, ..., GD1 RD2". , Data voltages are output in the order of BD2 GD3, ... ".

For reference, in the above description, the gate driver 22 and the data driver 23 are described as being separately installed from the liquid crystal panel 24. However, in recent years, each of the gate driver 22 and the data driver 23 is COG (Chip On Glass) or COF (Chip On). There is a tendency to be directly mounted on the liquid crystal panel 24 using a packaging technology such as a film or a chip on flexible printed circuit.

Of course, in such a case, the liquid crystal panel driving technology of the present invention as described above is applied as it is.

As described in detail above, the present invention enables driving both the left and right pixels using one data line, thereby reducing the number of data lines and reducing the manufacturing cost and size of the data driver.

In addition, by supplying a common voltage for each vertical line on the liquid crystal panel by using the data line space reduced to half level, the common voltage is stabilized, and thus, afterimage or crosstalk is hardly generated.

Claims (8)

In addition to outputting a gate control signal and a data control signal, and outputting image data for a pair of pixels commonly connected to each horizontal line per data line on a liquid crystal panel, the pixel structure and scan pulse supply order correspond to the pixel structure and scan pulse supply order. A timing controller for changing and outputting the order; A gate driver for sequentially supplying scan pulses to a pair of up and down gate lines arranged for each horizontal line on the liquid crystal panel in response to the gate control signal; A data driver converting digital video data into a data voltage corresponding to a gray scale value in response to the data control signal and outputting the converted data voltage to the liquid crystal panel; A pair of pixels on each horizontal line per data line are commonly connected through switching elements, and the liquid crystal panel includes a pair of gate lines per horizontal line to supply scan pulses by dividing them into odd and excellent numbers. The driving circuit of the liquid crystal display device comprising a. 2. The timing controller of claim 1, wherein the timing controller receives image data in horizontal line units in the order of "RD1 GD1 BD1, RD2 GD2 BD2 ...", "RD1 BD1, GD2 RD3, ...", "GD1 RD2, BD2 GD3, ..." The driving circuit of the liquid crystal display device, characterized in that configured to output. 2. The driving circuit of the liquid crystal display device according to claim 1, wherein the timing controller is configured to change using two regions of the line memory when changing the output order of the image data. The liquid crystal panel driving circuit of claim 1, wherein the pair of gate lines are arranged above and below the pixels of one horizontal line. 2. The driving circuit of a liquid crystal display device according to claim 1, wherein the switching element in the liquid crystal panel is a thin film transistor (TFT). A process of arranging a pair of gate lines per horizontal line in order to supply a scan pulse by connecting a pair of pixels on each horizontal line per data line to each other through a switching element, and separating them into odd and excellent numbers; ; In addition to outputting a gate control signal and a data control signal, and outputting image data for a pair of pixels commonly connected to each horizontal line per data line on a liquid crystal panel, the pixel structure and scan pulse supply order correspond to the pixel structure and scan pulse supply order. Outputting by changing the order; Supplying scan pulses sequentially to a pair of gate lines arranged up and down for each horizontal line on the liquid crystal panel in response to the gate control signal; Converting digital video data into a data voltage corresponding to a gray value in response to the data control signal and outputting the digital voltage to the liquid crystal panel; A process of sequentially outputting gate signals to a pair of gate lines arranged for each horizontal line on the liquid crystal panel, and outputting the data voltages in order of changing the image data when outputting data voltages to data lines on each horizontal line. A driving method of a liquid crystal display device, characterized in that consisting of. 7. When changing the output order of the image data, the image data is input in the order of "RD1 GD1 BD1, RD2 GD2 BD2 ..." in the order of horizontal lines and received them in the order of "RD1 BD1, GD2 RD3, ...", "GD1 RD2, BD2 GD3, ... "The method of driving a liquid crystal display device characterized by the above-mentioned. 7. The method of driving a liquid crystal display device according to claim 6, wherein a change is made by using a line memory when changing the output order of the image data.

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