KR20080017626A - Liquid display device - Google Patents

Abstract

An LCD is provided to prevent ghost when pixels connected to a kth gate line are precharged by outputting compensation gradation data of pixels connected to a kth gate line based on a comparison result of gray data of a pixel connected to a k-1th gate line and gray data of pixels connected to the kth gate line. A plurality of data lines(DL1-Dm) intersects a plurality of gate lines(GL1-GLn) and is insulated from the gate lines. A liquid crystal panel(110) is connected to the gate lines and the data lines, and includes a plurality of pixels formed in respective intersections of the gate lines and the data lines. A first gate driver(120) is electrically connected to the k-1th gate line, and provides a first gate signal having a first precharging section and a first normal section adjacent to the first precharging section to the k-1th gate line. A second gate driver(130) is electrically connected to the kth gate line, and provides a second gate signal having a second precharging section corresponding to the first normal section and a second normal section adjacent to the second precharging section to the kth gate line. A compensation circuit receives a data signal from the outside, and compensates a gray data value corresponding to the second normal section of a pixel connected to the kth gate line based on a comparison result of a first gray data value of the sub-pixel connected to the k-1th gate line and a second gray data value of a pixel connected to the kth gate line. A data driver(150) provides a data voltage corresponding to the compensation gray data from the compensation circuit to the plurality of data lines.

Description

 Liquid crystal display {LIQUID DISPLAY DEVICE}

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a diagram illustrating a pixel array and a switching element of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a view illustrating a ghost phenomenon occurring in the liquid crystal display according to the present invention.

FIG. 4 is a timing diagram of gate signals respectively output from the gate drivers shown in FIG. 1.

FIG. 5 shows a preferred embodiment of the correction circuit shown in FIG.

6 shows another correction circuit in accordance with another embodiment of the present invention.

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device employing a precharging driving method.

In general, a liquid crystal display (LCD) includes two display panels including a pixel electrode and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween.

The pixel electrodes are arranged in a matrix form and connected to switching elements such as thin film transistors to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage.

In such a liquid crystal display, a voltage is applied to two electrodes to form an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to control the transmittance of light passing through the liquid crystal layer to obtain a desired image. At this time, in order to prevent the deterioration of the liquid crystal caused by the application of an electric field in one direction for a long time, the polarity of the data voltage is inverted based on the common voltage in units of frames, rows or dots.

Meanwhile, as the resolution of the liquid crystal display device increases, the number of scanning lines, that is, gate lines, increases, and accordingly, the time taken to charge the pixels of one line decreases rapidly. The precharge driving method is used to compensate for the reduced charging time. Here, in the precharge driving method, when the pixel connected to an arbitrary gate line is charged, the pixel connected to an adjacent gate line having the same pixel polarity is charged in advance to change the polarity of the pixel. Then, charging is performed with data of the corresponding pixel. That is, two gate lines are driven at the same time, so that one gate line performs two times of driving during one frame, that is, precharge driving and normal driving.

For example, in the liquid crystal display device driven by dot inversion, the pixel connected to the k-th gate line is precharged when the pixel connected to the k-1 th gate line is driven by the first pixel data. Since the pixel connected to the k-th gate line is already precharged with the first pixel data, the pixel connected to the k-th gate line may be displayed differently from the desired luminance under the influence of the first pixel data when it is normally driven with the second pixel data that is the original data.

Such a phenomenon is called a ghost phenomenon, which is the biggest disadvantage of the precharge driving method.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of preventing ghost phenomenon generated during precharge driving.

According to an aspect of the present invention, a liquid crystal display device includes a plurality of gate lines, a plurality of data lines, a liquid crystal panel, a first gate driver, a second gate driver, a correction circuit, and a data driver. .

The liquid crystal panel includes a plurality of pixels formed in an area where the gate lines intersect the data lines. The first gate driver is electrically connected to the k−1 th gate line and has a first precharge section and a first normal section adjacent to the first precharge section with the k−1 th gate line. Provide a gate signal. The second gate driver is electrically connected to the k-th gate line and is connected to the k-th gate line to a second precharging period corresponding to the first normal period and a second normal to the second precharging period. A second gate signal having a section is provided. The correction circuit may include a pixel connected to the k-th gate line based on a comparison result of the first gray-scale data value of the sub-pixel connected to the k-th gate line and the second gray-scale data value of the pixel connected to the k-th gate line. Correcting the gray scale data value corresponding to the second normal interval of the output gray scale data value. The data driver provides a plurality of data lines with data voltages corresponding to corrected gray scale data from the correction circuit.

According to the liquid crystal display device, ghost phenomenon can be prevented in the precharge-driven liquid crystal display device.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings. In understanding the drawings, it should be noted that like parts are intended to be represented by the same reference numerals as much as possible. Incidentally, detailed descriptions of well-known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention will be omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment includes a plurality of gate lines, a plurality of data lines, a pixel array, a first gate driver, a second gate driver, a compensation circuit, and a data driver.

1 is a view showing a liquid crystal display according to a preferred embodiment of the present invention, Figure 2 is a view showing an arrangement of pixels according to the present invention.

Referring to FIG. 1, the liquid crystal display 100 includes a liquid crystal panel 110, a first gate driver 120, a second gate driver 130, a timing controller 140, and a data driver 150.

The liquid crystal panel 110 includes a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm that are insulated from and cross the plurality of gate lines GL1 to GLn, and the gate lines L1 to GLn. A plurality of pixels PX are formed at intersections of the data lines DL1 to DLm, respectively.

2 is a diagram illustrating a pixel array and a switching element of a liquid crystal display according to an exemplary embodiment of the present invention.

As illustrated in FIG. 2, the plurality of pixels PX are arranged in a matrix form on the liquid crystal panel. Each of the plurality of pixels PX includes three sub pixels, that is, a red sub pixel px1, a green sub pixel px2, and a blue sub pixel px3. These three sub-pixels are arranged in the same direction as the data line DL, that is, in the horizontal direction, to form one pixel. Thus, the sub pixels arranged in the longitudinal direction have the same color.

On the other hand, the liquid crystal display device 100 according to the present invention employs a 2x1 inversion driving method (that is, the liquid crystal display device 100 has a two dot pattern structure) inverting polarity for each selection of two gate lines. A vertical line inversion driving method is adopted in which the polarity is inverted every frame. Each sub pixel includes a thin film transistor M having a gate electrode and a source electrode connected to a gate line GL1 -GLn and a data line DL1 -DLm, and a liquid crystal capacitor connected to a drain electrode of the thin film transistor M. C) and a storage capacitor (not shown).

Specifically, the thin film transistor M formed in the pixels belonging to the first gate line GL1 and the second gate line GL2 is connected to the left data line, and the third gate line GL3 and the fourth gate line ( Each thin film transistor M formed in the pixels belonging to GL4 is connected to the right data line. That is, the positions of the thin film transistors M are alternately repeated alternately.

Hereinafter, the ghost phenomenon that occurs when the precharge driving method is applied to the structure having the pixel array as described above will be briefly described.

3 is a view illustrating a ghost phenomenon occurring in the liquid crystal display according to the present invention. In FIG. 3, a gate line is not shown to simplify the drawing.

Referring to FIG. 3, when a data voltage is applied from the data driver 150 to each of the data lines DL1 -DLm, the kth is applied by the data voltage applied to the subpixel px4 connected to the k−1th gate line. The sub pixel px3 connected to the gate line is precharged. Here, it should be noted that precharging the sub pixel px3 is not the data voltage applied to the sub pixel px2 but the sub pixel px4.

As a result, the charge amount of the pixel connected to the k-th gate line is excessively increased by the data voltage provided to the pixel connected to the k-th gate line, thereby causing a ghost phenomenon that appears brighter than the original gray scale.

The liquid crystal display device 100 according to the present invention includes a correction circuit 145 capable of removing the above ghost phenomenon in a timing controller to be described later. A detailed description of the correction circuit 145 will be described later.

Meanwhile, the liquid crystal display device 100 according to an exemplary embodiment of the present invention electrically connects one end of odd-numbered gate lines G1, G3,..., Gn-1 of the gate lines GL1 -GLn. The first gate driver 120 is connected to the second gate driver 130 electrically connected to one end of the even-numbered gate lines G2, G4,..., Gn.

The first gate driver 120 responds to the first gate control signal CONT1 provided from the timing controller 140, which will be described later. The odd-numbered gate lines G1, G3,... A plurality of first gate signals are sequentially provided.

The second gate driver 130 includes a plurality of second gate lines G2, G4,..., Gn in response to the second gate control signal CONT2 provided from the timing controller 140. Provide two gate signals sequentially.

4 is a timing diagram of gate signals output from the gate drivers 120 and 130 illustrated in FIG. 1, respectively. For convenience of description, only four gate signals GS1, GS2, GS3, and GS4 output from the gate drivers 120 and 130 appear. The first gate signals GS1 and GS3 are gate signals output to the first gate driver 120, and the second gate signals GS2 and GS4 are gate signals output from the second gate driver 130.

As shown in FIG. 4, each of the gate signals GS1, GS2, GS3, and GS4 includes precharging sections P1 and P2 and normal sections N1 and N2. In detail, the high period of the first gate signals GS1 and GS3 includes a first precharging period P1 and a first normal period N1. The high period of the second gate signals GS2 and GS4 includes a second precharging period P2 and a second normal period N2.

Each of the gate signals GS1, GS2, GS3, and GS4 remains high during the T / 2 period. In this case, the first precharging section is a T / 4 section corresponding to an initial stage of the first gate signals GS1 and GS3, and the first normal section is a T section corresponding to a later stage of the first gate signals GS1 and GS3. / 4 section. The second precharging period is a T / 4 period corresponding to a later period of the second gate signals GS2 and GS4, and the second normal period is a T corresponding to a later period of the second gate signals GS2 and GS4. / 4 section.

The high period of the second gate signals GS2 and GS4 is a signal delayed by a T / 4 period from the high period of the first gate signals GS1 and GS3, respectively. Accordingly, the second precharging periods P2 and P4 of the second gate signals GS2 and GS4 correspond to the first normal periods N1 and N3 of the first gate signals GS1 and GS3, respectively. (Overlap).

Subsequently, the data driver 150 generally includes a plurality of day driver ICs, and the data line of the liquid crystal panel 110 in response to the control gray scale data CRGB provided from the timing controller 140 and control signals. Generates signals to drive them. For example, the correction grayscale data CRGB sequentially received in synchronization with the load signal TP is latched to output correction data to the data lines D1 -Dm.

The data driver 150 provides the first data signal DATA1 to the plurality of data lines DL1 to DLm during the first normal periods N1 and N3 to charge the plurality of pixels connected to the odd-numbered gate lines.

In addition, the data driver 150 outputs the second data signal DATA2 to the plurality of data lines DL1 to DLm during the second normal periods N2 and N4, thereby providing the even-numbered gate lines GL2 and GL4. Charge a plurality of pixels connected to.

In this case, the plurality of pixels connected to the first and second gate lines GL2 and GL4 during the second precharging periods P2 and P4 are precharged with the first and third data signals, respectively, A plurality of pixels connected to the third gate line GL3 is precharged with the second data signal during one precharging period P1.

Thus, by partially overlapping the gate signal of the previous stage and the current stage gate signal, a plurality of pixels connected to the current stage gate line with the previous stage data signal are precharged.

The timing controller 140 receives a horizontal sync signal H_SYNC, a vertical sync signal V_SYNC, a data enable signal DE, and pixel data RGB provided from an external graphic source.

The timing controller 140 converts the data format to meet the specifications of the liquid crystal panel 110 and corrects the gray scale data CRGB by correcting the luminance change of the pixels due to the precharge driving by the correction circuit 145. The data control signal DCONT including the horizontal synchronization start signal STH and the load signal TP is output to the data driver 150.

A detailed operation of the correction circuit 145 will be described later in detail.

In addition, the timing controller 140 may receive the first gate control signal GCONT1 and the second gate control signal GCONT2 in response to the horizontal synchronization signal H_SYNC, the vertical synchronization signal V_SYNC, and the data enable signal DE. Output

The output first gate control signal GCONT1 and the second gate control signal GCONT2 are respectively input to the first gate driver 120 and the second gate driver 130 to control the respective gate drivers 120 and 130. do.

The first gate control signal GCONT1 includes a first vertical synchronization signal STV1 (start vertical), a first gate clock signal CPV1, and a first output enable signal OE1.

The first vertical synchronization signal STV1 indicates the start of output of a first gate signal (eg, GS1 and GS3 of FIG. 3), and the first gate clock signal CPV1 is a first gate signal. To control the output time. In addition, the first output enable signal OE1 defines a width of the first gate signal.

The second gate control signal GCONT2 includes a second vertical synchronization signal STV1 (start vertical), a second gate clock signal CPV1, and a second output enable signal OE1.

The first vertical synchronizing signal STV1 indicates the start of output of the second gate signal (eg, GS1 and GS3 of FIG. 3), and the second gate clock signal CPV1 is the first gate signal as the second gate signal. To control the output time. In addition, the second output enable signal OE1 defines the width of the second gate signal.

FIG. 5 shows a preferred embodiment of the correction circuit shown in FIG.

The correction circuit 145 according to an exemplary embodiment of the present invention compares the image data of the k-th gate line currently input from the outside with the image data of the k-th gate line previously input, and according to the comparison result, Correct image data of the k-th gate line. According to such a correction circuit, the goth phenomenon which arises in the precharge drive system can be prevented.

Referring to FIG. 6, the correction circuit 145 includes a line memory 142 and a correction unit 144.

The line memory 142 outputs a gray scale data value RGB _{GK -1} of a pixel connected to a k-1 th gate line (hereinafter, referred to as a 'k-1 th pixel') and is connected to a k th gate line. The second grayscale data value RGB _GK (hereinafter referred to as 'k-th pixel') is stored.

The correction unit 144 corrects the pixel data value (CRGB _Gk) by comparing the k-1-th pixel value of the gradation data (RGB _{Gk -1)} for providing the precharge gray-scale data values of the k-th pixel (RGB _Gk) Outputs

Specifically, when the second grayscale data value RGB _Gk of the kth pixel is smaller than the first grayscale data RGB _{GK -1} of the k-1th pixel, the second grayscale data value RGB _Gk of the kth pixel. ) And outputs a correction gray scale data value CRGB _Gk corresponding to a luminance lower than that corresponding to. When the second grayscale data value RGB _Gk of the k-th pixel is greater than or equal to the first grayscale data RGB _{GK -1} of the k-1th pixel, the second grayscale data value RGB of the kth pixel _The correction gray scale data value CRGB _Gk corresponding to the same luminance as the luminance corresponding to _Gk ) is output.

The correction gray scale data value CRGB _Gk of the k-th pixel output from the correction circuit 145 is further performed by gamma correction or the like in the timing controller 140, and then the data driver 150 shown in FIG. 1. Is provided.

6 shows another correction circuit in accordance with another embodiment of the present invention.

The correction circuit 145 shown in FIG. 6 includes a line memory and a lookup table 244 instead of the correction unit of the correction circuit shown in FIG. The lookup table 244 is a kind of memory that stores the correction gradation data value CRGB _Gk according to the comparison result value of the input pixel data RGB _GK and the gradation data RGB _{GK- 1} from the line memory 142. When the grayscale data values RGB _Gk and RGB _{Gk −1} are input, the lookup table outputs the corrected grayscale data CRGB _Gk corresponding to the grayscale data values RGB _Gk and RGB _{Gk −1} .

Meanwhile, in the present embodiment, an example in which the correction circuit 145 is provided inside the timing controller 140 has been described, but may be separately configured outside the timing controller 140 as necessary.

According to the present invention, the ghost phenomenon can be prevented in the precharge-driven liquid crystal display device.

As described above, the optimum embodiment has been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (8)

A plurality of gate lines; A plurality of data lines insulated from and intersecting the plurality of gate lines; A liquid crystal panel connected to the gate lines and the data lines, the liquid crystal panel including a plurality of pixels formed at an intersection of the gate lines and the data lines; a k-1 (where k is a natural number) electrically connected to the gate line, and having a first precharge interval and a first normal interval adjacent to the first precharge interval to the k-1th gate line; A first gate driver providing a first gate signal; a second gate signal electrically connected to the k th gate line and having a second precharge section corresponding to the first normal section and a second normal section adjacent to the second precharging section as the k th gate line; A second gate driver providing a; The k-th gate is received based on a result of comparing a first grayscale data value of a subpixel connected to the k-1th gate line and a second grayscale data value of a pixel connected to the kth gate line. A correction circuit for correcting the grayscale data value corresponding to the second normal section of the pixel connected to the line and outputting corrected grayscale data; And And a data driver for supplying data voltages corresponding to the correction gray scale data from the correction circuit to the plurality of data lines. The liquid crystal display of claim 1, wherein the second gate signal is a signal delayed by the first precharging period from the first gate signal. The method of claim 1, The correction circuit, A line memory for storing a first gray level data value of a pixel connected to the k-1 th gate line; And A look-up value for outputting correction values corresponding to the comparison result of the first grayscale data value of the pixel connected to the k-1th gate line and the second grayscale data value of the pixel connected to the kth gate line as the correction grayscale data value; And an up table. The method of claim 1, The correction circuit, A line memory for storing first grayscale data of a pixel connected to the k-1th gate line; And And a correction unit configured to correct first grayscale data stored in the line memory and second grayscale data values of a pixel connected to the k-th gate line. The method of claim 4, wherein The correction unit, When the second grayscale data value of the pixel connected to the kth gate line is smaller than the first grayscale data value of the k-1th pixel, the correction grayscale corresponding to the luminance lower than the luminance corresponding to the second grayscale data value of the kth pixel Output data values, When the second grayscale data value of the pixel connected to the k-th gate line is greater than or equal to the first grayscale data value of the pixel connected to the k-th gate line, the luminance is equal to the luminance corresponding to the grayscale data value of the kth pixel. And a corresponding corrected gradation data value. The method of claim 1, And each of the plurality of pixels is any one of a red color pixel, a green color pixel, and a blue color pixel. The method of claim 6, The plurality of pixels, And the gate lines are arranged in the same color pixels in the extending direction, and the data lines are arranged in different color pixels in the extending direction. The method of claim 6, And a data voltage applied to the data line is a vertical inversion driving signal.

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