KR20080044444A - Generator and liquid crystal display comprising the same - Google Patents

Abstract

A voltage generator and a liquid crystal display device having the same are provided to improve image quality of the display device by enhancing driving performance of a driver and preventing damage to a data driver. A voltage generator includes a driving voltage generator(810), a driving voltage generator(820), a gate-on voltage generator(830), and a gate-off voltage generator(840). The driving voltage generator outputs a first driving voltage and a pulse signal. The first driving voltage level is changed according to ambient temperature. The driving voltage generator receives the first driving voltage level and outputs a second driving voltage whose voltage level is adjusted between first and second reference voltages. The level of the first reference voltage is lower than that of the first reference voltage. The gate-on voltage generator outputs a gate-on voltage by shifting the second driving voltage by the voltage level of the pulse signal. The gate-off voltage generator outputs a gate-off voltage by shifting the first input voltage by the voltage level of the pulse signal.

Description

A voltage generator and a liquid crystal display including the same {Generator and liquid crystal display comprising the same}

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of one pixel of FIG. 1.

3 is a block diagram illustrating the voltage generator of FIG. 1.

4 is a graph for describing the driving voltage generator and the driving voltage controller of FIG. 3.

5 is a signal diagram illustrating a clock generator of FIG. 1.

6 is a block diagram illustrating the gate driver of FIG. 1.

FIG. 7 is a circuit diagram illustrating the j-th stage of FIG. 6.

FIG. 8 is a circuit diagram illustrating the driving voltage generator of FIG. 3.

FIG. 9 is a block diagram illustrating the PWM generator of FIG. 8.

FIG. 10 is a circuit diagram illustrating a gate on voltage generator and a gate off voltage generator of FIG. 3.

FIG. 11 is a circuit diagram illustrating the driving voltage controller of FIG. 3.

12 is a circuit diagram illustrating a driving voltage controller of a voltage generating device and a liquid crystal display including the same according to another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10: liquid crystal display 300: liquid crystal panel

400: gate driver 500: signal controller

600: clock generator 700: data driver

800: voltage generator 810: driving voltage generator

820: driving voltage controller 830: gate-on voltage generator

840: gate off voltage generator 900: gray voltage generator

The present invention relates to a voltage generator capable of improving display quality and a liquid crystal display including the same.

The liquid crystal display includes a liquid crystal panel having a plurality of gate lines and a plurality of data lines, a gate driver for outputting gate signals to the plurality of gate lines, and a data driver for outputting data signals to the plurality of data lines. Recently, in order to reduce the size of the liquid crystal display and increase productivity, a structure in which a gate driver is integrated and formed in a predetermined region of the liquid crystal display panel has been developed.

The gate driver formed on the liquid crystal panel includes a plurality of stages that sequentially output gate signals, each stage being at least one amorphous silicon thin film transistor (hereinafter referred to as an 'a-Si TFT'). It includes). The a-Si TFT receives a first clock signal and a second clock signal and outputs a gate signal. The driving capability of the a-Si TFT changes depending on the ambient temperature. In particular, when the ambient temperature is lowered, the driving capability is lowered, and a gate signal of a sufficient voltage level for turning on / off the switching element in the pixel cannot be output. . Therefore, in order to improve the driving capability of the a-Si TFT at low temperature, the amplitude of the first clock signal and the second clock signal is increased. Here, in order to increase the amplitude of the first clock signal and the second clock signal, the amplitude of the driving voltage based on the generation of the first clock signal and the second clock signal must be adjusted according to the temperature.

However, the driving voltage is also provided to the data driving IC of the data driver, and the driving voltage provided to the data driving IC should be within a predetermined range. If it is out of the predetermined range, the display quality is deteriorated due to damage or malfunction of the data driver IC, such as the data driver IC being broken or a vertical line unevenness is recognized.

Therefore, while it is necessary to improve the driving capability of the a-Si TFT, it is necessary to prevent damage or malfunction of the data driver IC.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a voltage generator capable of improving display quality.

Another object of the present invention is to provide a liquid crystal display device capable of improving display quality.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a voltage generating device comprising: a driving voltage generation unit configured to output a first driving voltage and a pulse signal whose voltage level changes according to an ambient temperature, and a voltage of the first driving voltage; A driving voltage controller configured to receive a level and output a second driving voltage between a first reference voltage and a second reference voltage having a lower voltage level than the first reference voltage, and converting the second driving voltage by the voltage level of the pulse signal. And a gate-on voltage generator for shifting the gate-on voltage and outputting a gate-off voltage by shifting the first input voltage by the voltage level of the pulse signal.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a driving voltage generator configured to output a first driving voltage and a pulse signal having a voltage level varying according to an ambient temperature; A driving voltage controller configured to receive a voltage level and output a second driving voltage between a first reference voltage and a second reference voltage having a lower voltage level than the first reference voltage, and converting the second driving voltage into a voltage level of the pulse signal. A voltage generator including a gate-on voltage generator for shifting the gate-on voltage by outputting a gate-on voltage, and a gate-off voltage generator for outputting a gate-off voltage by shifting a first input voltage by a voltage level of the pulse signal; A clock generator configured to receive a voltage and the gate-off voltage and output a first clock signal and a second clock signal; A gate driver which receives a first clock signal and the second clock signal and outputs a gate signal, a gray voltage generator that receives the second driving voltage and outputs a plurality of gray voltages, and an image signal among the plurality of gray voltages And a liquid crystal panel including a data driver for selecting and outputting one gray voltage corresponding to the plurality of gray voltages, and a plurality of pixels turned on / off by the gate signal to display an image according to the selected gray voltage.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a voltage generator and a liquid crystal display including the same according to embodiments of the present invention will be described with reference to the accompanying drawings. 1 is a block diagram illustrating a liquid crystal display according to example embodiments of the present invention, FIG. 2 is an equivalent circuit diagram of one pixel of FIG. 1, and FIG. 3 is a block diagram illustrating the voltage generation device of FIG. 1. 4 is a graph illustrating the driving voltage generator and the driving voltage controller of FIG. 3, FIG. 5 is a signal diagram illustrating the clock generator of FIG. 1, and FIG. FIG. 7 is a circuit diagram for describing the j-th stage of FIG. 6.

Referring to FIG. 1, the liquid crystal display 10 according to the exemplary embodiments of the present invention may include a liquid crystal panel 300, a voltage generator 800, a signal controller 500, a clock generator 600, and a gate driver. 400, a data driver 700, and a gray voltage generator 900.

The liquid crystal panel 300 is divided into a display unit DA on which an image is displayed and a non-display unit PA on which an image is not displayed.

The display unit DA is formed for each region where a plurality of gate lines G1 to Gn, a plurality of data lines D1 to Dm, a plurality of gate lines G1 to Gn, and a plurality of data lines D1 to Dm cross each other. The image is displayed by including the pixel PX. The gate lines G1 to Gn extend substantially in the row direction and are substantially parallel to each other, and the data lines D1 to Dm extend substantially in the column direction and are substantially parallel to each other.

Referring to FIG. 2, a pixel PX of FIG. 1 is described. A pixel electrode PE is formed on a first substrate 100, and a common electrode CE and a color filter are formed on a second substrate 200. (CF) can be formed. The liquid crystal 150 is interposed between the first substrate 100 and the second substrate 200. For example, the pixel PX connected to the i-th (i = 1 to n) gate line Gi and the j-th (j = 1 to m) data line Dj is a switching element connected to the signal lines Gi and Dj. Q1, and a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto. The sustain capacitor Cst may be omitted as necessary.

The non-display area PA refers to a portion where the first substrate (see 100 of FIG. 2) is formed wider than the second substrate (see 200 of FIG. 2) so that an image is not displayed.

The voltage generator 800 generates a voltage required for the operation of the liquid crystal display 10. For example, the gate on voltage Von, the gate off voltage Voff, and the controlled driving voltage AVDD_C are generated. Hereinafter, the controlled driving voltage AVDD_C will be described in more detail with reference to FIGS. 3 and 4.

First, referring to FIG. 3, the voltage generator 800 may include a driving voltage generator 810, a driving voltage controller 820, a gate on voltage generator 830, and a gate off voltage generator 840. have. For convenience of description, the voltage AVDD output by the driving voltage generator 810 is referred to as a first driving voltage, and the controlled driving voltage AVDD_C output by the driving voltage controller 820 is referred to as a second driving voltage. do.

The driving voltage generator 810 receives the first input voltage Vin1 and provides a first driving voltage AVDD and a pulse signal PULSE whose voltage level is changed according to temperature. As shown in FIG. 4, the voltage level of the first driving voltage AVDD varies with temperature, and the voltage level of the first driving voltage AVDD is inversely proportional to the change in temperature.

The driving voltage controller 820 receives the first driving voltage AVDD and outputs the second driving voltage AVDD_C. The driving voltage controller 820 is the first reference voltage Vref1 as shown in FIG. 4. The second driving voltage AVDD_C is output between the second reference voltage Vref2 and the second driving voltage AVref_C.

That is, since the first driving voltage AVDD is inversely proportional to temperature, when the ambient temperature is less than the first temperature T1, when the ambient temperature is lower than the voltage level of the first reference voltage Vref1 and greater than the second temperature T2. The voltage level is lower than the voltage level of the second reference voltage Vref2. However, when the first driving voltage AVDD is greater than the first reference voltage Vref1, the driving voltage controller 820 outputs the second driving voltage AVDD_C of the first reference voltage Vref1 level and outputs the second driving voltage AVDD_C. If less than the reference voltage Vref2, the second driving voltage AVDD_C of the second reference voltage Vref2 level is output, and if less than the first reference voltage Vref1 and greater than the second reference voltage Vref2, the first The driving voltage AVDD is output as it is.

The first reference voltage Vref1 and the second reference voltage Vref2 may be, for example, 12V and 7V, respectively, and are voltage levels capable of preventing damage or malfunction of the data drive IC in the data driver 700. In more detail, the second driving voltage AVDD_C is provided to the gray voltage generator 900, and the plurality of gray voltages GV generated based on the second driving voltage AVDD_C are transferred to the data driver 700. In this case, the second driving voltage AVDD_C may be provided to the data driver IC inside the data driver 700. In this case, when the second driving voltage AVDD_C is 12V or more, the data drive IC may be damaged, and when the second driving voltage AVDD_C is 7V or less, the data drive IC may malfunction and the vertical lines may be recognized. However, in the present invention, since the second driving voltage AVDD_C is 7V to 12V, damage or malfunction of the data drive IC may be prevented. In addition, when the first driving voltage AVDD is 7V to 12V, since the second driving voltage AVDD_C varies inversely with temperature, the second driving voltage AVDD is used to improve the driving capability of the gate driver 400 even at low temperatures. However, the first reference voltage Vref1 and the second reference voltage Vref2 are not limited to 12V and 7V, respectively. A process of improving the driving capability of the gate driver 400 through the second driving voltage AVDD_C having the sections Vref1 to Vref2 varying inversely with temperature will be described later.

The gate-on voltage generator 830 receives the second driving voltage AVDD_C and the pulse signal PULSE to generate a gate-on voltage Von that varies with temperature. The voltage level of the gate-on voltage Von may rise at low temperatures and decrease at high temperatures.

The gate off voltage generator 840 receives the second input voltage vin1 and the pulse signal PULSE and outputs a gate off voltage Voff that is variable in temperature. The voltage level of the gate off voltage Voff decreases at low temperatures and may increase at high temperatures.

The signal controller 500 of FIG. 1 receives an input image signal R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal Mclk, and a data enable signal DE.

The signal controller 500 generates a data control signal CONT based on the input image signals R, G, and B and the input control signal, and outputs the data control signal CONT and the image data DAT to the data driver 700. Send to).

In addition, the signal controller 500 provides the clock generator 600 with the first clock generation control signal OE, the second clock generation control signal CPV, and the original scan start signal STV. Here, the first clock generation control signal OE is a gate enable signal for enabling the gate signal, the original scan start signal STV is a signal indicating the start of one frame, and the second clock generation control signal CPV is The gate clock signal may determine a duty ratio of the gate signal.

The clock generator 600 responds to the first clock generation control signal OE, the second clock generation control signal CPV, and the original scan start signal STV, and provides a gate-on voltage provided from the voltage generator 800. The first clock signal CKV and the second clock signal CKVB are output using Von and the gate-off voltage Voff. In addition, the raw scan start signal STV is converted into a scan start signal STVP and provided to the gate driver 400. The scan start signal STVP is a signal in which the amplitude of the original scan start signal STV is increased.

The first clock signal CKV and the second clock signal CKVB are signals that swing between the gate on voltage Von and the gate off voltage Voff, and have opposite phases. Here, the first clock signal CKV and the second clock signal CKVB will be further described with reference to FIG. 5.

As described above, the voltage generator 800 may output the gate on voltage Von_L having an increased level at a low temperature, and may output the gate on voltage Von_H having a reduced level at a high temperature. In addition, the gate off voltage Voff_L of the reduced level may be output at low temperature, and the gate off voltage Voff_H of the increased level may be output at high temperature.

Therefore, the clock generator 600 may output the first clock signal CKV and the second clock signal CKVB swinging between the gate-on voltage Von_H and the gate-off voltage Voff_H at a high temperature. In addition, the clock generator 600 may output the first clock signal CKV and the second clock signal CKVB swinging between the gate on voltage Von_L and the gate off voltage Voff_L at a low temperature.

On the other hand, the data driver 700 receives the image signal DAT and the data control signal CONT from the signal controller 500, for example, and transmits the image data voltage corresponding to the image signal DAT to each data line D1. ~ Dm). The data control signal CONT is a signal for controlling the operation of the data driver 700, and includes a horizontal start signal for starting the operation of the data driver 700, a load signal for indicating output of two data voltages, and the like. .

The gate driver 400 receives the first clock signal CKV and the second clock signal CKVB, the scan start signal STVP, and the gate off voltage Voff to receive a gate signal from a plurality of gate lines G1 to Gn. To provide.

Hereinafter, the gate driver 400 will be described in detail with reference to FIGS. 5 to 7. 6 and 7 are examples of the gate driver 400 and are not limited to those illustrated in FIGS. 6 and 7. However, the gate driver 400 may include at least one a-Si TFT.

The gate driver 400 includes a plurality of stages ST ₁ to ST _{n +1} , and each stage ST ₁ to ST _{n + 1} is dependently connected to each other, and the gate signals Gout ₍₁₎ are sequentially _formed. Gout _{(n + 1)} is output, and the gate-off voltage Voff, the first clock signal CKV, and the second clock signal CKVB are input. All stages except the last stage ST _{n +1} are connected one-to-one with a gate line (not shown) of the liquid crystal panel (not shown).

Each stage ST ₁ to ST _{n +1} has a first clock terminal CK1, a second clock terminal CK2, a set terminal S, a reset terminal R, a power supply voltage terminal GV, and a frame reset. It has the terminal FR, the gate output terminal OUT1, and the carry output terminal OUT2.

The carry signal Cout _(j-1) of the front stage ST _j-1 is provided to the set terminal S of each stage ST ₁ to ST _{n +1} , for example, the j th stage ST _j . The gate signal Gout _{(j + 1} ) of the rear stage ST _{j +1} is input to the reset terminal R, and the first clock signal is input to the first clock terminal CK1 and the second clock terminal CK2. The CKV and the second clock signal CKVB are input, the gate-off voltage Voff is input to the power supply voltage terminal GV, and the initialization signal INT is input to the frame reset terminal FR. The gate output terminal OUT1 outputs the gate signals Gout ₍₁₎ to Gout _{(n + 1)} , and the carry output terminal OUT2 outputs the carry signals Cout ₍₁₎ to Cout _{(n + 1)} . do. A final stage carry signal _{(Cout (n + 1))} of the _{(n +1} ST) is provided for each stage (ST ₁ ST ~ _{n +1)} as an initialization signal.

However, the scan start signal STVP is input to the first stage ST ₁ instead of the front carry signal, and the scan start signal STVP is input to the last stage ST _{n +1} instead of the rear gate signal.

Here, the j-th stage STj of FIG. 6 will be described in detail with reference to FIGS. 5 and 7.

Referring to FIG. 7, the j th stage STj includes a buffer unit 410, a charging unit 420, a pull-up unit 430, a carry signal generator 470, a pull-down unit 440, a discharge unit 450, and It may include a holding unit 460. However, the carry signal generator 470 may be omitted. In this case, the gate signal Gout _(j) may function as a carry signal.

The buffer unit 410 has a common drain and gate of the transistor T4 and connects a carry signal Cout _(j-1) of the front stage ST _{n -1} input through the set terminal S to a source. The charging unit 420, the carry signal generator 470, the discharge unit 450, and the holding unit 460 are provided.

One end of the charging unit 420 is connected to the source and the discharge unit 750 of the transistor T4, and the other end includes a capacitor C1 connected to the gate output terminal OUT1. The charging unit 420 is charged with the carry signal Cout _(j-1 ) of the front stage ST _n-1 .

The pull-up unit 430 may include a transistor having a drain connected to the first clock terminal CK1, a gate connected to one end of the capacitor C1, and a source connected to the other end of the capacitor C1 and the gate output terminal OUT1. T1). When the capacitor C1 of the charging unit 420 is charged, the transistor T1 is turned on, and the first clock signal CKV input through the first clock terminal CK1 is gated through the gate output terminal OUT1. Provided as (Gout _(j) ). Here, when the first clock signal CKV is at the high level, that is, the gate-on voltage Von_H or Von_L, the pull-up unit 430 may select the gate signal Gout _(j) having the gate-on voltage Von_H or Von_L level. Output

The pull-up unit 430 is reduced in driving capability at low temperatures. However, at a low temperature, the first clock signal CKV and the second clock signal CKV are signals that swing between the gate on voltage Von_L and the gate off voltage Voff_L, and thus, the first clock signal CKV and the second clock signal. Since the amplitude of the clock signal CKV is large, the driving capability of the pull-up unit 430 does not decrease even at low temperatures.

On the other hand, the carry signal generator 470 has a drain connected to the first clock terminal CK1, a source connected to the gate output terminal OUT1, and a gate connected to the buffer unit 710. And a capacitor C2 connected to the gate and the source. The capacitor C2 is charged in the same manner as the charging unit 420, and when the capacitor C2 is charged, the transistor C2 transfers the first clock signal CKV to the carry signal Cout _(j) through the carry output terminal OUT2. Output

The pull-down unit 440 has a drain connected to the source of the transistor T1 and the other end of the capacitor C1, a source connected to the power supply voltage terminal GV, and a gate connected to the reset terminal R. It includes. The pull-down unit 440 is input through the reset terminal R and then turned on to the gate signal Gout _{(j + 1)} of the stage ST _{j +1} to convert the gate signal Gout _(j ) into a gate-off voltage ( Voff).

The discharge unit 450 has a gate connected to the reset terminal R, a drain connected to one end of the capacitor C1, and a source connected to the power supply voltage terminal GV, so that the gate of the next stage ST _{j +1} is discharged. The transistor T9 discharges the charging unit 420 in response to the signal Gout _{(j + 1)} , the gate is connected to the frame reset terminal FR, and the drain is connected to one end of the capacitor C1. The source includes a transistor T6 connected to the power supply voltage terminal GV to discharge the charging unit 420. That is, the discharge unit 450 gates off the charges charged in the capacitor C1 through the source in response to the gate signal Gout _{(j + 1} ) or the initialization signal INT of the next stage ST _{j +1} . Discharge to voltage Voff.

The holding unit 460 maintains the transistor T3 when the gate signal Gout _(j) is at a high level to perform a hold operation, and the gate signal Gout _(j) moves from a high level to a low level. After the conversion, the transistors T3 and T5 are turned on to perform a hold operation.

That is, even at low temperatures, the amplitudes of the first clock signal CKV and the second clock signal CKVB increase, so that the driving capability of the gate driver 400 does not decrease. Therefore, since the gate signal Gout _(j) of the current and the voltage which can turn on / off a plurality of switching elements (see Q1 in FIG. 2) connected to the plurality of gate lines G1 to Gn is provided, the display quality is improved even at low temperatures. Can be improved.

Hereinafter, a voltage generator and a liquid crystal display including the same will be described with reference to FIGS. 8 through 11. FIG. 8 is a circuit diagram illustrating the driving voltage generator of FIG. 3, FIG. 9 is a block diagram illustrating the PWM generator of FIG. 8, and FIG. 10 illustrates the gate on voltage generator and the gate off voltage generator of FIG. 3. FIG. 11 is a circuit diagram for describing the driving voltage controller of FIG. 3.

First, referring to FIG. 7, the driving voltage generator 810 may include a boost converter 813 and a temperature detector 819.

The boost converter 813 includes an inductor L to which the first input voltage Vin1 is applied, a first diode D1 having an anode connected to the inductor L, and a cathode connected to an output terminal of the driving voltage AVDD. And a first capacitor C1 connected between the first diode D1 and ground, and a pulse width modulation (PWM) signal generator 816 connected to the anode terminal of the first diode D1. Here, the boost converter 813 is an example of a DC-DC converter, and may be another kind of converter.

Referring to the operation, when the PWM signal PWM output to the PWM signal generator 816 is at a high level, the switching element Q2 is turned on, and the both ends of the inductor L according to the current and voltage characteristics of the inductor L. In proportion to the first input voltage Vin1 applied to the current I _L flowing through the inductor L gradually increases.

When the PWM signal PWM is at a low level, the switching element Q2 is turned off so that the current I _L flowing through the inductor L flows through the first diode D1, and the current and voltage of the first capacitor C1 are maintained. According to a characteristic, a voltage is charged in the first capacitor C1. Therefore, the first input voltage Vin1 is boosted to a predetermined voltage and output as the driving voltage AVDD. Here, the duty ratio of the PWM signal PWM varies according to the voltage level of the temperature variable voltage VARV, and the amount of current flowing through the inductor L varies according to the duty ratio of the PWM signal PWM. Accordingly, the driving voltage AVDD and the pulse signal PULSE are boosted or decompressed.

The operation of the PWM signal generator 816 will be described with reference to FIG. 9. The oscillator 814 generates a reference clock signal RCLK of a constant frequency. The comparator 815 compares the reference clock signal RCLK generated from the oscillator 814 with the temperature variable voltage VARV, and when the level of the temperature variable voltage VARV is greater than the level of the reference clock signal RCLK. A high level is output, and a small level is output to generate a PWM signal PWM. Since the frequency of the reference clock signal RCLK is constant, the duty ratio of the PWM signal PWM varies according to the level of the temperature variable voltage VARV. However, the clock generator 740 is not limited thereto, and may be another type of circuit that generates a clock signal CLK whose duty ratio changes according to the control voltage signal VCONT.

For example, the temperature detector 820 outputs a temperature variable voltage VARV that increases when the ambient temperature increases and decreases when the ambient temperature decreases. The temperature detector 819 may include diodes D2 to D4 having threshold voltages that are substantially inversely proportional to changes in ambient temperature. As shown in FIG. 8, the voltage at the reference node NO is dropped through the diodes D2 to D4 to become the temperature variable voltage VARV. When the ambient temperature rises, the threshold voltages of the diodes D2-D4 decrease to increase the temperature variable voltage VARV. When the ambient temperature decreases, the threshold voltages of the diodes D2-D4 increase and the temperature variable voltage ( VARV) decreases. In FIG. 8, the voltage of the reference node NO is a voltage divided by the driving voltage AVDD through the resistors R1 and R2.

In other words, the boost converter 813 and the temperature sensing unit 819 output a pulse signal PULSE and a first driving voltage AVDD in which the voltage level decreases when the ambient temperature increases, and the voltage when the ambient temperature decreases. The pulse signal PULSE and the first driving voltage AVDD having the increased level are output. However, the internal circuits of the boost converter 813 and the temperature sensing unit 819 are not limited to those illustrated in FIGS. 8 and 9.

Referring to FIG. 10, the driving voltage controller 820 includes an operational amplifier OP. It demonstrates with reference to the following formula.

AVDD2 = (R2 / R3) × AVDD1

By the operating characteristics of the operational amplifier OP, when the output of the operational amplifier OP is between the first reference voltage Vref1 and the second reference voltage Vref2, the second driving voltage AVDD_C calculated by the equation may be obtained. Is output. However, if the output of the operational amplifier OP is greater than or equal to the first reference voltage Vref1, the first reference voltage Vref1 is output as the second driving voltage AVDD_C, and if it is less than or equal to the second reference voltage Vref2, the second reference voltage may be generated. The voltage Vref2 is output as the second driving voltage AVDD_C. In addition, the first driving voltage AVDD may be amplified by adjusting the values of the resistors R2 and R3. That is, it is possible to control the amount of change in voltage according to the change in temperature.

Referring to FIG. 11, a case in which the gate on voltage generator 830 and the gate off voltage generator 840 are charge pumping circuits will be described as an example.

The gate-on voltage generator 830 includes fifth and sixth diodes D5 and D6 and second and third capacitors C2 and C3. The temperature variable voltage VARV is provided to the anode of the fifth diode D5, and the cathode of the fifth diode D5 is connected to the first node N1. The second capacitor C2 is connected between the first node N1 and the second node N2 to which the pulse signal PULSE is applied. The anode of the sixth diode D6 is connected to the first node N1, and the cathode of the sixth diode D6 outputs a gate-on voltage Von. The third capacitor C3 is connected between the anode of the fifth diode D5 and the cathode of the sixth diode D6. However, the present invention is not limited thereto and may be made of a combination of three or more diodes and three or more capacitors.

In operation, when the pulse signal PULSE is provided to the second capacitor C2, the first node N1 outputs a pulse raised by the voltage level of the pulse signal PULSE at the temperature variable voltage VARV. . The sixth diode D6 and the third capacitor C3 clamp the voltage of the first node N1 to output the gate-on voltage Von. That is, the gate-on voltage Von becomes a DC voltage in which the temperature variable voltage VARV is shifted by the voltage level of the pulse signal PULSE.

The gate off voltage generator 840 includes seventh and eighth diodes D7 and D8 and fourth and fifth capacitors C4 and C5. The second input voltage Vin2 is provided to the cathode of the seventh diode D7, and the anode of the seventh diode D7 is connected to the third node N3. The fourth capacitor C4 is connected between the third node N3 and the second node N3 to which the pulse signal PULSE is applied. The anode of the eighth diode D8 is connected to the third node N3, and the cathode of the eighth diode D8 outputs a gate off voltage Voff. The third capacitor C3 is connected between the cathode of the seventh diode D7 and the anode of the eighth diode D8. However, the present invention is not limited thereto, and may include a combination of three or more diodes and three or more capacitors.

In operation, when the pulse signal PULSE is provided to the fourth capacitor C4, the third node N3 receives the pulse lowered by the voltage level of the pulse signal PULSE at the second input voltage Vin2. Output The sixth diode N6 and the fifth capacitor C5 clamp the voltage of the third node N3 to output the gate off voltage Voff. That is, the gate-off voltage Voff becomes a DC voltage in which the second input voltage Vin2 is shifted by the voltage level of the pulse signal PULSE.

Since the voltage levels of the temperature variable voltage VARV and the pulse signal PULSE are varied according to the ambient temperature as described above, the gate on voltage Von and the gate off voltage Voff become as shown in FIG. 5. Can be.

According to the voltage generator 800 and the liquid crystal display device 10 including the same, the driving ability of the gate driver does not decrease even at low temperatures, and damage or malfunction of the data driver can be prevented, thereby improving display quality. .

A voltage generator and a liquid crystal display including the same according to another exemplary embodiment of the present invention will be described with reference to FIG. 12. 12 is a circuit diagram illustrating a voltage generator device and a driving voltage controller of a liquid crystal display device including the same according to another embodiment of the present invention.

Unlike the previous embodiment, the driving voltage controller 821 includes an operational amplifier OP and an inverting unit 822. It demonstrates with reference to the following formula.

OUT =-(R2 / R3) × AVDD1

The output of the operational amplifier OP may be represented as in Equation 2. That is, since the operational amplifier OP constitutes a circuit of the inverting amplifier, the output voltage OUT of the operational amplifier OP is in phase with the first driving voltage AVDD. Accordingly, the inverting unit 822 inverts the phase of the output voltage OUT of the operational amplifier OP and outputs a second driving voltage AVDD_C having the same phase as the first driving voltage AVDD.

The driving voltage controller 821 outputs the first reference voltage Vref1 as the second driving voltage AVDD_C when the output of the driving voltage controller 821 is equal to or greater than the first reference voltage Vref1, and the second reference voltage ( If less than Vref2), the second reference voltage Vref2 is output as the second driving voltage AVDD_C. In addition, the first driving voltage AVDD may be amplified by adjusting the values of the resistors R2 and R3. That is, it is possible to control the amount of change in voltage according to the change in temperature.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the voltage generation device and the liquid crystal display including the same according to the embodiments of the present invention as described above has the following advantages.

First, even if the ambient temperature decreases, the driving capability of the gate driver is improved.

Second, damage or malfunction of the data driver can be prevented.

Third, the driving ability of the driver is improved, and damage or malfunction of the data driver is prevented, so that display quality is improved.

Claims (15)

A driving voltage generator configured to output a first driving voltage and a pulse signal whose voltage levels change according to an ambient temperature; A driving voltage controller configured to receive a voltage level of the first driving voltage and output a second driving voltage between a first reference voltage and a second reference voltage having a lower voltage level than the first reference voltage; A gate on voltage generator configured to shift the second driving voltage by a voltage level of the pulse signal to output a gate on voltage; And And a gate off voltage generator configured to output a gate off voltage by shifting a first input voltage by the voltage level of the pulse signal. The method of claim 1, The driving voltage controller outputs the second driving voltage of the first reference voltage level when the first driving voltage is greater than the first reference voltage, and outputs the second driving voltage of the first reference voltage level when the first driving voltage is smaller than the second reference voltage. Outputting the second driving voltage at a second reference voltage level; and outputting the second driving voltage at the first driving voltage level when the first driving voltage is less than the first reference voltage and greater than the second reference voltage. Voltage generator. The method of claim 1, The change in the second drive voltage with respect to the change in the ambient temperature when the first drive voltage is greater than the first reference voltage is 0, and the change in the ambient temperature when the second drive voltage is less than the second reference voltage. The change in the second drive voltage with respect to the change is zero, and when the first drive voltage is less than the first reference voltage and greater than the second reference voltage, the change in the second drive voltage is inversely proportional to the change in ambient temperature. Voltage generator. The method of claim 1, And the first driving voltage decreases when the ambient temperature increases, and increases when the ambient temperature decreases. The method of claim 1, The driving voltage controller includes an operational amplifier. The method of claim 1, wherein the driving voltage generator, A temperature sensing unit for outputting a temperature variable voltage whose voltage level is varied according to the ambient temperature, and boosting a second input voltage to output the first driving voltage and the pulse signal whose voltage level is varied according to the temperature variable voltage; Voltage generating device comprising a boost converter. The method of claim 6, The temperature detector is configured to output the temperature variable voltage increases when the ambient temperature increases, and decreases when the ambient temperature decreases. The method of claim 7, wherein And the temperature sensing unit includes at least one diode having a threshold voltage substantially inversely proportional to a change in the ambient temperature. A driving voltage generator for outputting a first driving voltage and a pulse signal whose voltage level changes according to an ambient temperature, and a voltage level lower than a first reference voltage and the first reference voltage by receiving a voltage level of the first driving voltage; A driving voltage controller configured to output a second driving voltage between a second reference voltage, a gate on voltage generator configured to output a gate on voltage by shifting the second driving voltage by a voltage level of the pulse signal, and a first input voltage; A voltage generator including a gate off voltage generator configured to shift the voltage level of the pulse signal to output a gate off voltage; A clock generator configured to receive the gate on voltage and the gate off voltage and output a first clock signal and a second clock signal; A gate driver configured to receive the first clock signal and the second clock signal and output a gate signal; A gray voltage generator which receives the second driving voltage and outputs a plurality of gray voltages; A data driver which selects and outputs one gray voltage corresponding to an image signal among the plurality of gray voltages; And And a liquid crystal panel having a plurality of pixels turned on / off by the gate signal to display an image according to the selected gray voltage. The method of claim 9, The driving voltage controller outputs the second driving voltage of the first reference voltage level when the first driving voltage is greater than the first reference voltage, and outputs the second driving voltage of the first reference voltage level when the first driving voltage is smaller than the second reference voltage. Outputting the second driving voltage at a second reference voltage level; and outputting the second driving voltage at the first driving voltage level when the first driving voltage is less than the first reference voltage and greater than the second reference voltage. Liquid crystal display. The method of claim 9, The first driving voltage decreases when the ambient temperature increases, and increases when the ambient temperature decreases. The method of claim 9, The driving voltage controller includes an operational amplifier. The method of claim 9, wherein the driving voltage generator, A temperature sensing unit for outputting a temperature variable voltage whose voltage level is varied according to the ambient temperature, and boosting a second input voltage to output the first driving voltage and the pulse signal whose voltage level is varied according to the temperature variable voltage; Liquid crystal display comprising a boost converter. The method of claim 13, The temperature detector is configured to output the temperature variable voltage increases when the ambient temperature increases, and decreases when the ambient temperature decreases. The method of claim 14, And the temperature sensing unit includes at least one diode having a threshold voltage substantially inversely proportional to a change in the ambient temperature.

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