TWI395190B - Display devices capable of automatically adjusting driving voltages and methods of driving the same - Google Patents

Description

Display capable of actively adjusting driving voltage and related driving method

The invention relates to a display and related driving method, in particular to a display capable of actively adjusting a driving voltage and a related driving method.

Liquid crystal display has been widely used in notebook computers and personal digital assistants because it has the advantages of low radiation, small size and low energy consumption. It has gradually replaced the traditional cathode ray tube display. (personal digital assistant, PDA), flat-screen TV, or mobile phone and other information products. The conventional liquid crystal display adopts an external driving chip to drive pixels on the panel to display images, but in order to reduce the number of components and reduce the manufacturing cost, in recent years, the driving circuit structure has been developed directly on the display panel, for example, the gate is The level driver is integrated into the technology of a liquid crystal panel (Gate on Array, GOA).

Please refer to FIG. 1 , which is a schematic diagram of a liquid crystal display 100 in the prior art. As shown in FIG. 1, the liquid crystal display 100 includes a liquid crystal display panel 110, a source driving circuit 120, and a gate driving circuit 130. The liquid crystal display panel 110 of the liquid crystal display 100 is provided with a plurality of pixels PX arranged in an array, a plurality of data lines D ₁ to D _m , and a plurality of gate lines G ₁ to G _n . The source driving circuit 120 is used to drive the data lines D ₁ -D _m , and the gate driving circuit 130 can provide the output voltages V ₁ VV _n to drive the gate lines G ₁ -G _{n , respectively} .

Please refer to Figure 2. Figure 2 is a schematic diagram showing the operational characteristics of a liquid crystal display. In Fig. 2, the vertical axis represents the minimum output voltage (volts) of the gate drive circuit that can operate the panel normally, the horizontal axis represents the usage time (hours), the operating temperature of the liquid crystal display is 85 degrees Celsius, and the curve A represents the positive gate. A characteristic curve when the voltage Vgh=11V and the negative gate voltage Vgl=-11V, and the curve B represents a characteristic curve when the positive gate voltage Vgh=20V and the negative gate voltage Vgl=-11V. Since the minimum output voltage of the normal operation gate drive circuit will gradually increase with the increase of the operation time, see curve A of Fig. 2, under the operating condition of the positive gate voltage Vgh=11V, the liquid crystal display is used for more than about 250 hours. After that, the minimum output voltage of the gate drive circuit can be operated normally beyond the ideal gate voltage (Vgh=11V) of this condition, which is easy to cause abnormal operation; as shown by curve B in Fig. 2, at the positive gate voltage Vgh= Under the operating conditions of 20V, the minimum output voltage of the liquid crystal display remains within the ideal voltage range even after about 800 hours of use. Therefore, increasing the positive gate voltage Vgh can effectively lengthen the use time of the panel.

Please refer to the following chart 1, which shows the power consumption of the liquid crystal display under different operating conditions. In Figure 1, T_stress represents the length of time the bias is applied, and unstress represents that no bias has been applied. Vgh and Vgl represent the positive gate voltage and the negative gate voltage (V), respectively, and Ih and Il represent the application, respectively. The positive gate voltage Vgh and the current (mA) when the negative gate voltage Vg is applied, Ph and Pl represent the power consumption (mW) when the positive gate voltage Vgh is applied and the negative gate voltage Vg is applied, respectively, and P_sum represents the total power. Consumption (mW). Comparing the total power consumption P_sum under the same conditions of T_stress, that is, comparing condition 1 and condition 2 or comparing condition 3 and condition 4, it can be known that the total power consumption P_sum is proportional to the positive gate voltage Vgh. Therefore, increasing the positive gate voltage Vgh can increase the use time while increasing the power consumption of the panel.

The invention provides a display capable of actively adjusting a driving voltage, comprising a display panel for turning on a pixel to display an image according to a complex array gate output voltage and a common voltage; and a gate driving circuit for using a gate Inputting a signal to provide the complex array gate output voltage; a voltage selector coupled to the gate drive circuit to receive an nth gate output voltage of the complex array gate output voltage, the voltage selector capable of Providing a plurality of different positive gate voltages and a plurality of different common voltages, and selecting from the plurality of positive gate voltages according to a relationship between a reference voltage and the nth gate output voltage a corresponding positive gate voltage is used as an output positive gate voltage, and a corresponding common voltage is selected from the common voltages of the complex array as the common voltage; a timing controller is used Generating a clock signal; and a voltage generator for generating a negative gate voltage.

The present invention further provides a voltage compensation circuit for a display panel, comprising a gate driving circuit for generating a complex array gate output voltage to a pixel array; a voltage selector coupled to the gate driving circuit Receiving one of the n-th gate output voltages of the complex array gate output voltage, the voltage selector can provide a common voltage of a complex array of different positive gate voltages and a complex array, and can be based on a reference voltage and the a relationship between the output voltages of the nth gates, selecting a corresponding positive gate voltage from the positive gate voltage of the complex array as an output positive gate voltage, and a common voltage different from the complex array A corresponding common voltage is selected as the common voltage; a timing controller is used to generate a clock signal; and a voltage generator is used to generate a negative gate voltage.

The present invention further provides a method of driving a display panel, comprising: providing an nth gate output voltage of a plurality of gate output voltages; comparing a potential between a reference voltage and the nth gate output voltage; When the output voltage of the nth gate is greater than the reference voltage, a corresponding first positive gate voltage of the positive gate voltage of the complex array is selected as an output positive gate voltage, and the complex array is selected to be different. a corresponding common voltage in the voltage to do And outputting a common voltage; and when the output voltage of the nth gate is not greater than the reference voltage, selecting a second positive gate voltage of the plurality of positive gate voltages greater than the first positive gate voltage to And outputting a positive gate voltage for the output, and selecting a second common voltage of the plurality of common voltages that is less than the first common voltage as the output common voltage.

Referring again to the first chart, the total power consumption P_sum is compared under the same bias voltage, that is, the comparison condition 1 and the condition 3 or the comparison condition 2 and the condition 4, the total power consumption P_sum and the time T_stress applied are known. Inverse ratio. When T_stress exceeds a certain value (for example, 500 hours), the total power consumption P_sum is reduced to one-half of unstress (for example, from 115 mV to 46.2 mV or from 202.9 mV to 111.7 mV) under the same bias conditions. The invention utilizes the panel characteristic to drive the panel with a low positive gate voltage Vgh at the beginning to save power consumption; when the usage time exceeds a predetermined value, the panel is driven with a higher positive gate voltage Vgh. Increases the life of the panel without significantly increasing power consumption.

Due to the feedthrough effect, the common voltage Vcom of the display panel also changes with the value of the positive gate voltage Vgh. Please refer to the following chart 2, which shows the relationship between the common voltage, the positive gate voltage Vgh and the time T_stress applied. As shown in Figure 2, Vcom represents the common voltage when unstressed. The common voltage Vcom is inversely proportional to the positive gate voltage Vgh; Vcom' represents a common voltage when T_stress is greater than a specific value (e.g., 500 hours), and the common voltage Vcom' and the positive gate voltage Vgh are also inversely proportional. Meanwhile, when T_stress exceeds a certain value (for example, 500 hours), the positive gate voltage Vgh needs to be larger than a specific value (for example, 15 V) to operate the display panel normally. Comparing the values of the common voltage under the condition that the positive gate voltage Vgh is the same, that is, comparing Vcom and Vcom', it can be known that there is little difference between Vcom and Vcom'. In other words, the time T_stress applied is not significant to the common voltage, so the present invention only needs to consider the effect of the positive gate voltage Vgh on the common voltage: at the beginning with a lower positive gate voltage Vgh and The high common voltage Vcom is used to drive the panel to save power consumption; when the usage time exceeds a predetermined value, the panel is driven by the higher positive gate voltage Vgh and the lower common voltage Vcom, thereby improving the service life of the panel without Will greatly increase the power consumption, or change the characteristics of the display panel.

Please refer to FIG. 3, which is a schematic diagram of the liquid crystal display 500 of the present invention. The liquid crystal display 500 includes a liquid crystal display panel 510, a source driving circuit 520, a gate driving circuit 530, and a gate compensation circuit 540. The liquid crystal display panel 510 is provided with a plurality of pixels PX arranged in an array, a plurality of data lines D ₁ to D _m , and a plurality of gate lines G ₁ to G _n . The source driving circuit 520 of the liquid crystal display 500. The gate driving circuit 530 operates according to the gate input signal Si. The gate input signal Si includes a voltage signal Vss, a start pulse signal Vst, a clock signal Vck, and a reverse clock signal Vxck. The gate input signal based on Si, the gate driving circuit 530 can be a positive gate voltage Vgh and Vgl negative gate voltage to the corresponding gate driving electrode line ₁ ~ G _n G, the output voltage at this time the gate driving circuit 530, respectively, of It is represented by V ₁ ~V _n . The gate compensation circuit 540 can provide a gate input signal Si to the gate driving circuit 530 and a gate common voltage Vcom to the liquid crystal display panel 510, and correct the gate input signal Si and the common voltage according to the output voltage of the gate driving circuit 530. The value of the voltage Vcom can thus drive the liquid crystal display panel 510 with an optimum bias voltage.

When the liquid crystal display 500 is just starting to operate, the gate driving circuit 530 drives the gate lines G1 to Gn with a predetermined positive gate voltage Vgh1 and a predetermined negative gate voltage Vg1. Since the output of the nth stage of the gate driving circuit 530 is at the end of the signal transmission path, the output voltage of the gate driving circuit 530 usually does not meet the operating conditions at the earliest. Therefore, the present invention can determine the liquid crystal according to the nth output voltage V _{n of the} gate driving circuit 530. Whether the display 500 is functioning properly under such bias conditions. For example, if the output voltage of each stage of the gate driving circuit 530 needs to be greater than the reference voltage V _ref under the condition that the liquid crystal display 500 is normally operated, the gate compensation circuit 540 of the present invention determines whether the output voltage V _{n of} the nth stage is Greater than the reference voltage V _ref : if the nth stage output voltage V _{n is} greater than the reference voltage V _ref , in most cases the output voltage of the other stages of the gate drive circuit 530 will be greater than the reference voltage V _ref , The positive gate voltage Vgh1, the negative gate voltage Vgl, and the common voltage Vcom1 under predetermined bias conditions drive the liquid crystal display panel 510. When the liquid crystal display 500 is used for more than a certain period of time, its characteristics may be degraded, and if the liquid crystal display panel 510 is continuously driven under a predetermined bias condition, the predetermined display quality may not be achieved. Therefore, if the nth stage output voltage Vn _is not greater than the reference voltage _Vref , the gate compensation circuit 540 provides a corresponding gate input signal Si, so that the positive gate voltage Vgh2 and the negative gate can be under a favorable bias condition. The pole voltage Vgl and the common voltage Vcom2 drive the liquid crystal display panel 510. In other words, the gate compensation circuit 540 can actively compensate the gate input voltage Si according to the output voltage of the gate driving circuit 530, so that the gate driving circuit 530 can drive the gate line with the corresponding positive gate voltage Vgh. G1~Gn, and providing a corresponding common voltage Vcom to the liquid crystal display panel 510.

As shown in the first table, the second diagram and the second diagram, in the foregoing embodiment, Vgh2>Vgh1 and Vcom2<Vcom1. That is, when the display quality of the liquid crystal display 500 does not reach a predetermined standard, the present invention has a high positive gate voltage Vgh and The lower common voltage Vcom drives the panel to increase the life of the panel without significantly increasing power consumption.

Please refer to FIG. 4, which is a functional block diagram of the gate compensation circuit 540. The gate compensation circuit 540 includes a voltage selector 50, a timing controller 52, a voltage generator 54, and a level shifter 56. The voltage selector 50 is coupled to the gate driving circuit 530 and the liquid crystal display panel 510 to provide a corresponding positive gate voltage Vgh and a common voltage Vcom according to the output voltage V _{n of the} gate driving circuit 530. The timing controller 52 can provide the logic signal Sc required for the operation of the gate drive circuit 530, and the voltage generator 54 can provide the negative gate voltage Vgl. The voltage level shifter 56 is coupled to the voltage selector 50, the timing controller 52, the voltage generator 54, and the gate driving circuit 530, and is provided according to the logic signal Sc, the positive gate voltage Vgh, and the negative gate voltage Vgl. The gate input signal Si enables the gate driving circuit 530 to operate according to the voltage signal Vss including the gate input signal Si, the start pulse signal Vst, the clock signal Vck, and the reverse clock signal Vxck.

Please refer to FIG. 5. FIG. 5 is a functional block diagram of the voltage selector 50 in the first embodiment of the present invention. The voltage selector 50 of the first embodiment includes a comparator 58, an analog to digital converter (ADC) 60, a counter 62, and a voltage output circuit 64. The comparator 58 is coupled to the gate driving circuit 530 for comparing the potential of the reference voltage V _ref and the output voltage V _n : if the output voltage V _{n is} greater than the reference voltage V _ref , the comparator 58 outputs a high potential analog signal Va; If the output voltage V _n is not greater than the reference voltage V _ref, the comparator 58 outputs a low level analog signal V _a. The analog-to-digital converter 60 is coupled to the comparator 58 to convert the analog signal V _a into a digital signal V _d : if the high-potential analog signal V _{a is} received, the analog-to-digital converter 60 outputs a digital signal V having a logic 1 potential. _d ; if the low potential analog signal Va is received, the analog digital converter 60 outputs a digital signal V _{d having} a logic zero potential. The counter 62 is coupled to the analog-to-digital converter 60 and generates an output count value Co according to the digital signal V _d . The voltage output circuit 64 includes a control circuit 66 and multiplexers MUX1 and MUX2. The control circuit 66 is coupled to the counter 62. The output count value Co and the reference count value Ct can be compared and the corresponding control signal Vt is outputted. The multiplexer MUX1 and MUX2 can output the corresponding positive gate voltage and output common voltage according to the control signal Vt. For example, if the output count value Co is greater than the reference count value Ct, the multiplexer MUX1 outputs a positive gate voltage Vgh1 (eg, 11V) to the voltage level shifter 56, and outputs a common voltage Vcom1 (eg, 3.89V) to the liquid crystal. The display panel 510; if the output count value Co is not greater than the reference count value Ct, the multiplexer MUX1 outputs a positive gate voltage Vgh2 (eg, 20V) to the voltage level shifter 56, and outputs a common voltage Vcom2 (eg, 3.29V) to The liquid crystal display panel 510.

Please refer to FIG. 6. FIG. 6 is a timing chart of the voltage selector 50 of the first embodiment of the present invention in operation. Figure 6 shows the waveforms of the output voltage V _n , the digital signal V _d , the positive gate voltage Vgh and the common voltage Vcom. When the value of the output voltage V _n is greater than the reference voltage V _ref , the counter 62 starts counting until the value of the output voltage V _n is lower than the reference voltage V _ref , and the calculated output count values are respectively C _o1 , C _o2 , C _{o3 .} ,...etc. In the embodiment of FIG. 6, the times when the first three output voltages V _n1 VV _{n3 are} higher than the reference voltage V _ref correspond to the output count values C _o1 to C _o3 , respectively, wherein the output count values C _o1 and C _{o3 are} greater than the reference. The value Ct is counted, and the output count value C _{o2 is} smaller than the reference count value Ct. Since C _o1 >Ct, the liquid crystal display is still driven at the positive gate voltage Vgh1 and the common voltage Vcom1 corresponding to the output voltage V _n1 at this time. Thereafter, the waveform of the output voltage V _n2 deviates from the ideal value such that C _o2 < Ct, and the present invention selects the preferred positive gate voltage Vgh2 and the common voltage Vcom2 to drive the liquid crystal display. In the preferred use of the driving voltage waveform of the output voltage V _n3 of the back to normal, so C _o3> Ct, the present invention will continue to use this time a positive gate voltage and the common voltage Vcom2 Vgh2 to drive a liquid crystal display.

Please refer to FIG. 7. FIG. 7 is a functional block diagram of the voltage selector 50 in the second embodiment of the present invention. The second embodiment is similar to the first embodiment except that the first embodiment in FIG. 5 can provide different bias conditions for Vgh1/Vgl/Vcom1 and Vgh2/Vgl/Vcom2, and FIG. 7 The second embodiment can provide n sets of different bias conditions such as Vgh1/Vgl/Vcom1~Vghn/Vgl/Vcomn. In the second embodiment, the control circuit 66 of the voltage output circuit 64 also compares the output count value Co with the reference count value Ct, and outputs a corresponding control signal Vt. The multiplexers MUX1 and MUX2 can be based on the control signal Vt. The output corresponds to the positive gate voltage and the output common voltage. For example, if the output count value Co is greater than the reference count value Ct, the multiplexer MUX1 outputs a positive gate voltage Vgh1 (eg, 11V) to the voltage level shifter 56, and outputs a common voltage Vcom1 (eg, 3.89V) to the liquid crystal. The display panel 510; when the output count value Co starts to be not greater than the reference count value Ct, the multiplexer MUX1 first outputs a positive gate voltage Vgh2 (for example, 13V) to the voltage level shifter 56, and the multiplexer MUX2 first outputs The common voltage Vcom2 (for example, 3.72V) is applied to the liquid crystal display panel 510, and it is judged whether or not the driving condition is sufficient. If the output voltage V _{n is} greater than the reference voltage V _{ref by the} positive gate voltage Vgh2 and the output common voltage Vcom2, and the output count value Co is still not greater than the reference count value Ct, the multiplexer MUX1 outputs a positive gate. The pole voltage Vgh3 (for example, 15V) to the voltage level shifter 56, and the multiplexer MUX2 outputs a common voltage Vcom3 (for example, 3.53V) to the liquid crystal display panel 510; if the positive gate voltage Vgh2 and the output common voltage Vcom2 are driven When the output voltage Vn _is greater than the reference voltage _Vref , the voltage selector 50 continues to provide the bias condition and periodically performs the aforementioned determining step. In the case of driving with the positive gate voltage Vgh3 and the output common voltage Vcom3, if the output voltage Vn _is again lower than the reference voltage _Vref , the bias condition is changed again, and the multiplexer MUX1 outputs the positive gate voltage Vgh4. (for example, 20V) to the voltage level shifter 56, and the multiplexer MUX2 outputs a common voltage Vcom4 (for example, 3.29V) to the liquid crystal display panel 510. In other words, the second embodiment of the present invention can gradually change the value of the bias voltage depending on the value of the output voltage V _n instead of changing the bias voltage value a large amount.

Please refer to FIG. 8. FIG. 8 is a timing chart of the voltage selector 50 in operation of the second embodiment of the present invention. Figure 8 shows the waveforms of the output voltage V _n , the digital signal V _d , the positive gate voltage Vgh and the common voltage Vcom. When the value of the output voltage V _n is greater than the reference voltage V _ref , the counter 62 starts counting until the value of the output voltage V _n is lower than the reference voltage V _ref , and the calculated output count values are respectively C _o1 , C _o2 , C _{o3 .} , C _o4 , ..., etc. to represent. In the embodiment of FIG. 8, the times when the first four output voltages V _n1 VV _{n4 are} higher than the reference voltage V _ref correspond to the output count values C _o1 to C _o4 , respectively, wherein the output count values C _o1 and C _{o4 are} greater than the reference. The value Ct is counted, and the output count values C _o2 and C _{o3 are} smaller than the reference count value Ct. Since C _o1 >Ct, the liquid crystal display is still driven at the positive gate voltage Vgh1 and the common voltage Vcom1 corresponding to the output voltage V _n1 at this time. Thereafter, the waveform of the output voltage V _n2 deviates from the ideal value such that C _o2 < Ct, and the present invention selects the preferred positive gate voltage Vgh2 and the common voltage Vcom2 to drive the liquid crystal display. After using a positive gate voltage and the common voltage Vcom2 Vgh2, the waveform of the output voltage V _n3 still deviates from the ideal value, C _o3 <Ct, the present invention will select the preferred case of a positive gate voltage and the common voltage Vgh3 again driven Vcom3 LCD Monitor. After using a positive gate voltage and the common voltage Vcom3 Vgh3, the waveform of the output voltage V _n4 back to normal, so C _o4> Ct, the present invention will continue to use this time a positive gate voltage and the common voltage Vcom3 Vgh3 to drive a liquid crystal display.

Please refer to FIG. 9. FIG. 9 is a flow chart of the operation of the voltage selector 50 of the present invention. The flowchart of FIG. 9 includes the following steps: Step 910: providing a complex array positive gate voltage and a complex array common voltage; step 920: outputting a predetermined positive gate voltage and a complex array common voltage in the complex array positive gate voltage The first one of the predetermined common voltage; the step 930: receiving a gate output voltage V _n ; the step 940: determining whether the gate output voltage V _n is greater than a reference voltage V _ref ; if the gate output voltage V _{n is} greater than the reference voltage Vref, performing the steps 960; if the gate output voltage Vn _is not greater than the reference voltage _Vref , step 950 is performed; step 950: outputting another corresponding positive gate voltage of the complex array positive gate voltage and another phase of a complex array common voltage corresponding to the common voltage; step 930; step 960: the gate output corresponding to the output voltage and a positive gate voltage V _n of the joint; step 930.

Please refer to FIG. 10, which is a schematic diagram of a liquid crystal display 550 according to another embodiment of the present invention. The liquid crystal display 550 includes a liquid crystal display panel 510, a source driving circuit 520, two gate driving circuits 531 and 532, and a gate compensation circuit 540. The liquid crystal display 550 is similar to the liquid crystal display 500 except that the liquid crystal display 550 adopts a bilaterally driven architecture, that is, the gate driving circuits 531 and 532 are respectively disposed on both sides of the liquid crystal display panel 510. The gate driving circuits 531 and 532 operate according to the gate input signal Si, and the output voltages thereof are represented by Vl1 to Vln and Vr1 to Vrn, respectively. The liquid crystal display 550 of the present invention simultaneously judges whether or not it can operate normally under a predetermined bias condition in accordance with the nth-order output voltages Vln and Vrn of the gate driving circuits 531 and 532. For example, if one of the nth output voltages Vln and Vrn is not greater than the reference voltage V _ref , the gate compensation circuit 540 provides a corresponding gate input signal Si to simultaneously change the driving conditions of the gate driving circuits 531 and 532 . .

As described above, the present invention can select the n-th output voltage V _n at the end of the signal transmission path as a judgment condition, and can also judge whether the liquid crystal display can operate normally according to other stage output voltages. The structure of the voltage selector 50 in Figures 5 and 6 is merely an embodiment of the present invention and does not limit the scope of the present invention.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

50‧‧‧Voltage selector

52‧‧‧Timing controller

54‧‧‧Voltage generator

56‧‧‧Voltage level shifter

58‧‧‧ comparator

60‧‧‧ADC

62‧‧‧ counter

64‧‧‧Voltage output circuit

66‧‧‧Control circuit

540‧‧‧ gate compensation circuit

D ₁ ~D _m ‧‧‧ data line

G ₁ ~G _n ‧‧‧ gate line

PX‧‧ ‧ pixels

MUX1, MUX2‧‧‧ multiplexer

100, 500‧‧‧ liquid crystal display

110, 510‧‧‧ LCD panel

120, 520‧‧‧ source drive circuit

130, 530~532‧‧‧ gate drive circuit

Figure 1 is a schematic view of a liquid crystal display in the prior art.

Figure 2 is a schematic diagram of the operational characteristics of a liquid crystal display.

Figure 3 is a schematic view of a liquid crystal display of the present invention.

Figure 4 is a functional block diagram of the gate compensation circuit of the present invention.

Fig. 5 is a functional block diagram of a voltage selector in the first embodiment of the present invention.

Fig. 6 is a timing chart showing the operation of the voltage selector of the first embodiment of the present invention.

Figure 7 is a functional block diagram of a voltage selector in a second embodiment of the present invention.

Figure 8 is a timing chart showing the operation of the voltage selector of the second embodiment of the present invention.

Figure 9 is a flow chart showing the operation of the voltage selector of the present invention.

Figure 10 is a schematic view of a liquid crystal display according to another embodiment of the present invention.

500. . . LCD Monitor

510. . . LCD panel

520. . . Source drive circuit

530. . . Gate drive circuit

540. . . Gate compensation circuit

PX. . . Pixel

D ₁ ~ D _m . . . Data line

G ₁ ~ G _n . . . Gate line

Claims (23)

A display capable of actively adjusting a driving voltage, comprising: a display panel for turning on a pixel to display an image according to a complex array gate output voltage and a common voltage; and a gate driving circuit for inputting a signal according to a gate Providing the complex array gate output voltage; a voltage selector coupled to the gate drive circuit to receive an nth gate output voltage of the complex array gate output voltage, the voltage selector capable of providing a plurality a different positive gate voltage and a plurality of different common voltages, and can select a corresponding one of the plurality of positive gate voltages according to a relationship between a reference voltage and the output voltage of the nth gate The positive gate voltage is used as an output positive gate voltage, and a corresponding common voltage is selected from the common voltages of the complex arrays according to the relationship between the reference voltage and the output voltage of the nth gate. As the common voltage; a timing controller for generating a clock signal; and a voltage generator for generating a negative gate voltage. The display device of claim 1, wherein the voltage selector comprises: a comparator coupled to the gate driving circuit for comparing a potential of the reference voltage and the output voltage of the nth gate, and The comparison result produces a analog signal; an analog-to-digital converter coupled to the comparator for the analog signal Converting to a digital signal; a counter coupled to the analog digital converter for generating an output count value according to the digital signal; and a voltage output circuit coupled to the counter for comparing the output count value And a reference count value, and the output positive gate voltage and the common voltage are generated according to the comparison result. The display of claim 2, wherein: when the potential of the output voltage of the nth gate is greater than the reference voltage, the comparator outputs a high potential analog signal; and when the voltage of the output voltage of the nth gate is When not greater than the reference voltage, the comparator outputs a low potential analog signal. The display of claim 2, wherein: when receiving a high potential analog signal, the analog digital converter converts the high potential analog signal into a logical one digital signal; and when receiving a low potential analog signal The analog-to-digital converter converts the low potential analog signal into a logical zero digital signal. The display of claim 2, wherein: when the output count value is greater than the reference count value, the voltage output circuit selects an original positive gate voltage of the complex array positive gate voltage as the output positive gate voltage And select the complex array to be different a common common voltage in the voltage as the common voltage; and when the output count value is less than the reference count value, the voltage output circuit selects a positive gate of the complex array positive gate voltage that is greater than the original positive gate voltage The pole voltage is used as the output positive gate voltage, and a common voltage different from the original common voltage among the common voltages of the complex array is selected as the common voltage. The display device of claim 2, wherein the voltage output circuit comprises: a controller coupled to the counter for comparing the output count value and the size of the reference count value, and generating a control signal according to the comparison result; a first multiplexer coupled to the controller for selecting the output positive gate voltage from the plurality of positive gate voltages according to the control signal; and a second multiplexer coupled to the controller The method is configured to select the common voltage from a plurality of different common voltages according to the control signal. The display of claim 1, wherein the gate drive circuit is integrated in the gate on array (GOA). The display device of claim 1, further comprising: a voltage level shifter coupled to the voltage selector, the timing controller, and the voltage generator for using the clock signal, the negative gate voltage, And outputting a positive gate voltage to generate the gate input signal number. A voltage compensation circuit for a display panel, comprising: a gate driving circuit for generating a complex array gate output voltage to a pixel array; a voltage selector coupled to the gate driving circuit to receive the complex array One of the gate output voltages of the nth stage gate output voltage, the voltage selector can provide a common voltage of the complex gate different positive gate voltage and the complex array, and can be based on a reference voltage and the nth stage The relationship between the gate output voltages selects a corresponding positive gate voltage from the positive gate voltage of the complex array as an output positive gate voltage, and according to the reference voltage and the nth gate output voltage The relationship between the common voltages of the complex arrays is selected as a common voltage; a timing controller is used to generate a clock signal; and a voltage generator is used to generate a Negative gate voltage. The voltage compensation circuit of claim 9, wherein the voltage selector comprises: a comparator coupled to the gate driving circuit for comparing a potential of the reference voltage and the output voltage of the nth gate; And generating a analog signal according to the comparison result; an analog-to-digital converter coupled to the comparator for using the analog signal The number is converted to a digital signal; a counter coupled to the analog digital converter for generating an output count value according to the digital signal; and a voltage output circuit coupled to the counter for comparing the output meter The value and a reference count value are magnituded, and the output positive gate voltage and the common voltage are generated according to the comparison result. The voltage compensation circuit of claim 10, wherein: when the potential of the nth gate output voltage is greater than the reference voltage, the comparator outputs a high potential analog signal; and when the nth gate output voltage When the potential is not greater than the reference voltage, the comparator outputs a low potential analog signal. The voltage compensation circuit of claim 10, wherein: when receiving a high potential analog signal, the analog digital converter converts the high potential analog signal into a logic one digit signal; and when receiving a low potential analogy In the case of a signal, the analog digital converter converts the low potential analog signal into a logical zero digital signal. The voltage compensation circuit of claim 10, wherein the counter generates the output count value according to the width of the digital signal. The voltage compensation circuit of claim 10, wherein: When the output count value is greater than the reference count value, the voltage output circuit selects an original positive gate voltage of the complex array positive gate voltage as the output positive gate voltage, and selects one of the complex array common voltages The original common voltage is taken as the common voltage; and when the output count value is less than the reference count value, the voltage output circuit selects a positive gate voltage of the complex array positive gate voltage that is greater than the original positive gate voltage As the output positive gate voltage, and selecting a common voltage of the complex array common voltage less than the original common voltage as the common voltage. The voltage compensation circuit of claim 10, wherein the voltage output circuit comprises: a controller coupled to the counter for comparing the output count value and the reference count value, and generating a control signal according to the comparison result a first multiplexer coupled to the controller for selecting the output positive gate voltage from the plurality of positive gate voltages according to the control signal, and a second multiplexer coupled to the control And configured to select the common voltage from the plurality of common voltages according to the control signal. The voltage compensation circuit of claim 9, further comprising a voltage level shifter coupled to the voltage selector, the timing controller and the voltage generator for using the clock signal and the negative gate voltage And the output The positive gate voltage generates the gate input signal required to drive the gate drive circuit. A method of driving a display panel, comprising: providing an nth gate output voltage of a plurality of gate output voltages; comparing a potential between a reference voltage and the nth gate output voltage; when the nth When the output voltage of the gate is greater than the reference voltage, a corresponding first positive gate voltage of the positive gate voltage of the complex array is selected as an output positive gate voltage, and one of the common voltages of the complex array is selected. Corresponding first common voltage as an output common voltage; and when the nth gate output voltage is not greater than the reference voltage, selecting the plurality of positive gate voltages to be greater than the first positive gate voltage A second positive gate voltage is used as the output positive gate voltage, and a second common voltage of the plurality of common voltages less than the first common voltage is selected as the output common voltage. The method of claim 17, further comprising: providing an analog signal; converting the analog signal into a logical digit signal; generating an output count value according to a width of the logical digit signal; and comparing the output count value and The size of a reference count value. The method of claim 17, further comprising comparing the magnitude of the nth gate output voltage and the reference voltage. The method of claim 17, wherein providing one of the plurality of gate output voltages, the nth gate output voltage, provides a last one of the plurality of gate output voltages. The method of claim 17, further comprising providing the plurality of positive gate voltages and the plurality of common voltages. The method of claim 17, further comprising driving a display panel according to the output positive gate voltage and the output common voltage. The method of claim 17, further comprising setting the reference voltage according to a characteristic of a display panel.