KR20080039194A - Thin film transistor and method for fabricating the same, liquid crystal display device and organic light emitting diode display device using the same - Google Patents

Abstract

A TFT(Thin Film Transistor), its fabrication method, an LCD(Liquid Crystal Display) using the same, and an OLED(Organic Light Emitting Diode) display are provided to solve a problem that a reduction in a drain current causes a shortage of charged data, which makes a bad influence on picture quality. A gate electrode(1) is formed on an insulation substrate(10). An intrinsic semiconductor layer(2) is formed on the gate electrode with a gate insulating layer(11) interposed therebetween. A source electrode(3A) and a drain electrode(4A) are formed on the intrinsic semiconductor layer with a low-resistance semiconductor layer(12A) interposed therebetween. A channel region is formed at a portion where the source and drain electrodes face each other. The source and drain electrodes are formed to be directly connected with a portion where a channel layer(2a) of the intrinsic semiconductor layer is formed with the low-resistance semiconductor layer interposed therebetween.

Description

A thin film transistor and a method of manufacturing the same, and a liquid crystal display and an organic light emitting diode display using the same.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor having a bottom gate structure, and more particularly, a thin film transistor having a drain current secured by reducing a resistance component between a source electrode and a channel layer and a drain electrode and a channel layer, and a manufacturing method thereof, and a liquid crystal using the same. A display device and an organic light emitting diode display device.

Conventionally, a thin film transistor (TFT) having a bottom gate structure is used for a driving circuit such as a liquid crystal display.

This thin film transistor forms a gate electrode and a gate insulating film on an insulating substrate (glass substrate), and forms an intrinsic semiconductor layer (i-Si layer) and an ohmic contact layer (low resistance semiconductor layer) via a gate insulating film on the gate electrode. n + a-Si layers) are simultaneously patterned, and a source electrode and a drain electrode are formed on a semiconductor layer composed of an intrinsic semiconductor layer and a low resistance semiconductor layer, and the ohmic contact layer in a region excluding the source electrode and the drain electrode is removed. (Patent Document 1; See Japanese Patent Laid-Open No. 2004-356646).

12 is a plan view schematically and schematically showing a conventional thin film transistor shown in Patent Document 1. As shown in FIG.

In FIG. 12, the thin film transistor TFT includes a gate electrode 1 formed to correspond to a channel region of the channel width W and the channel length L, and an amorphous layer formed on the gate electrode 1 via a gate insulating film. amorphous) It consists of the source electrode 3 and the drain electrode 4 arrange | positioned opposingly on the silicon layer (a-Si layer) 2 and the a-Si layer (semiconductor layer) 2.

Although not shown in the plan view of FIG. 12, an ohmic contact layer (low resistance semiconductor) is provided between the source electrode 3 and the drain electrode 4 and the a-Si layer (intrinsic semiconductor layer, i-Si layer) 2. Layer, n + type a-Si layer). As a result, the channel region between the source electrode 3 and the drain electrode 4 forms a thin film transistor structure in which n-channel operation is performed by the application of the gate voltage Vgs under electrostatic charge.

In FIG. 12, in order to avoid the complexity of the drawing, the illustration of the insulating substrate (glass substrate) on which the gate electrode 1 is formed and the gate insulating film covering the surface of the gate electrode 1 are omitted, and the source electrode 3 and the drain electrode are omitted. Each shape of (4) is simplified and shown.

It is sectional drawing by the AA 'line | wire in FIG.

The thin film transistor illustrated in FIG. 13 includes a glass substrate (insulating substrate) 10, a gate electrode 1 formed on the glass substrate 10 so as to correspond to a channel region, and a glass substrate (to cover the gate electrode 1). 10, the a-Si layer 2 formed on the gate electrode 1 via the gate insulating film 11 so as to be located in the channel region of the thin film transistor, and the a-Si layer ( 2) a source electrode 3 and a drain electrode 4 disposed opposite to each other, and an ohmic contact layer 12 formed on a contact surface of the a-Si layer 2 and the source and drain electrodes 3 and 4, respectively. It is.

The ohmic contact layer 12 is formed on the upper surface of the a-Si layer 2. The source electrode 3 and the drain electrode 4 are disposed opposite to each other on the a-Si layer 2 via the ohmic contact layer 12 to form a thin film transistor structure. A contact portion 13 (see dashed line) is formed at the contact portion between the a-Si layer 2 and the ohmic contact layer 12.

The a-Si layer 2 acts as a resistance component without forming a channel and a channel layer 2a for forming a channel having a thickness corresponding to the gate voltage Vgs when the gate voltage Vgs is applied to the electrostatic charge. This can be considered by dividing it into the resistive layer 2b (resistance component).

The manufacturing process of the conventional thin film transistor shown in FIG. 12 and FIG. 13 is outlined.

The gate electrode 1 of the thin film transistor is formed on the glass substrate 10, and the gate insulating layer 11 is formed on the gate electrode 1 by PCVD (Plasma Chemical Vapor Deposition).

Subsequently, an i (intrinsic: intrinsic) -Si layer is formed on the gate electrode 1 via the gate insulating film 11, and subsequently an ohmic formed of an n + a-Si layer on the surface of the i-Si layer by PCVD. The contact layer 12 is formed. Then, an a-Si island composed of the a-Si layer 2 and the ohmic contact layer 12 is formed by photolithography and etching.

Then, the source and drain electrode materials are formed on the a-Si island by the sputtering method, and patterned as shown in FIG. 12 by the photolithography and etching method to form the source electrode 3 and the drain electrode 4. do.

Finally, the ohmic contact layer (n + a-Si layer) 12 other than the source and drain electrodes 3 and 4 is removed using the source electrode 3 and the drain electrode 4 as a mask by dry etching. The thin film transistor shown in FIG. 13 is completed.

Next, the operation of the conventional thin film transistor will be described.

In FIG. 13, when the gate voltage Vgs of the electrostatic charge is applied to the gate electrode 1, a channel serving as an electron path is formed in the channel layer 2a of the a-Si layer 2. At this time, when the drain voltage Vds is applied to the drain electrode 4 and the source electrode 3 is grounded, the a-Si layer 2 is caused by the potential difference between the source electrode 3 and the drain electrode 4. A drain current Ids (see the dashed arrows) flows from the drain electrode 4 to the source electrode 3 with respect to the channel layer 2a of the channel depending on the magnitude of the gate voltage Vgs and the drain voltage Vds. .

By the way, the bottom gate type thin film transistor generally used for a liquid crystal display (LCD) has the a-Si layer 2, the source electrode 3, and the drain electrode 4 as shown in FIG. It is connected via the ohmic contact layer 12 (n + a-Si layer) formed in the surface of (2). As a result, when the drain current Ids flows through the channel layer 2a in the a-Si layer 2, the resistance layer 2b and the channel layer 2a between the drain electrode 4 and the channel layer 2a are formed. ) And the drain current Ids flows through the resistance layer 2b between the source electrode 3 and the source electrode 3. As a result, for example, when the drain voltage Vds falls, the drain current Ids decreases depending on the thickness of the resistive layer 2b in the a-Si layer 2.

For this reason, when data is charged to each liquid crystal cell by a thin film transistor in a liquid crystal display (LCD), a lack of data charging occurs due to a decrease in the drain current Ids, and a direct current bias is applied to the liquid crystal. A phenomenon that adversely affects the image quality such as an afterimage phenomenon occurs.

As described above, in the conventional thin film transistor, the a-Si layer 2 and the ohmic contact layer 12 are simultaneously patterned to form an a-Si island. Thus, the ohmic contact layer 12 is formed of the a-Si layer 2. When the drain current Ids flows through the resistance layer 2b of the a-Si layer 2 through the application of the gate voltage Vgs and not directly connected to the channel layer 2a. There is a decreasing problem.

In particular, when a conventional thin film transistor is used in a liquid crystal display, there is a problem that shortage of data charging occurs due to a decrease in drain current Ids and adversely affects image quality.

Accordingly, the present invention has been made to solve the above-mentioned problems, and the source electrode and the drain electrode are directly connected to the channel layer formed on the i-Si layer (intrinsic semiconductor layer) via an ohmic contact layer (low resistance semiconductor layer). It aims at obtaining the thin film transistor in which favorable drain current flows even in a small drain voltage, its manufacturing method, the liquid crystal display device and organic light emitting diode display device using this thin film transistor.

To this end, the thin film transistor according to the present invention includes a gate electrode formed on an insulating substrate, an intrinsic semiconductor layer disposed on the gate electrode via a gate insulating film, and a source disposed on the intrinsic semiconductor layer through a low resistance semiconductor layer. It is a thin film transistor which has an electrode and a drain electrode, and forms a channel area | region in the opposing part of a source electrode and a drain electrode, The low resistance semiconductor layer is the part in which the channel layer of an intrinsic semiconductor layer is formed (side surface of the island of a-Si layer). And the source electrode and the drain electrode are connected to the channel layer of the intrinsic semiconductor layer via the low resistance semiconductor layer.

In addition, a method of manufacturing a thin film transistor according to the present invention includes forming a gate electrode on an insulating substrate, forming an island of an intrinsic semiconductor layer through a gate insulating film on the gate electrode, and forming an island of the intrinsic semiconductor layer. Forming a low resistance semiconductor layer on the gate insulating film, wherein the source electrode and the drain electrode are formed on the upper portion including the peripheral end of the island of the intrinsic semiconductor layer via the low resistance semiconductor layer. Forming a channel region in an opposite portion and removing the low resistance semiconductor layer except for the lower portions of the source electrode and the drain electrode, so as to cover a portion of the portion where the channel layer of the intrinsic semiconductor layer is formed; Form a layer.

According to the present invention, as in general MOS transistors, the source electrode and the drain electrode form a thin film transistor structure in which the channel layer in the intrinsic semiconductor layer can be directly contacted, thereby reducing the resistance between the source electrode and the drain electrode and the channel layer. Thus, a thin film transistor, a manufacturing method thereof, and a liquid crystal display device and an OLED display device using the thin film transistor, through which a good drain current flows even at a small drain voltage, can be obtained.

Embodiment 1

EMBODIMENT OF THE INVENTION Hereinafter, the thin film transistor which concerns on Embodiment 1 of this invention is demonstrated in detail, referring drawings.

Here, the case where an a-Si layer (amorphous silicon layer) is used as an intrinsic semiconductor layer and a low resistance semiconductor layer as mentioned above is demonstrated, for example.

FIG. 1 is a plan view schematically showing a thin film transistor according to Embodiment 1 of the present invention, and the same reference numerals as those in FIG. 12 are given the same reference numerals as those in FIG. Omit. In addition, in order to avoid the complexity of FIG. 1, illustration of the insulated substrate and the gate insulating film is abbreviate | omitted.

The source electrode 3A and the drain electrode 4A shown in FIG. 1 are formed so as to be directly connected to a part of the portion where the channel layer 2a of the a-Si layer 2 is formed. Although not shown in the plan view of FIG. 1, an ohmic contact layer 12A is interposed in the entire lower surface of the source electrode 3A and the drain electrode 4A.

FIG. 2: is sectional drawing by the BB 'line | wire in FIG. 1. About the same thing as FIG. 13 mentioned above, the same code | symbol is attached | subjected to FIG. 13, or it attaches "A" after a code | symbol, and abbreviate | omits description.

In FIG. 2, the thin film transistor according to Embodiment 1 of the present invention has a gate electrode 1 formed on the glass substrate 10 so as to correspond to a channel region, and on the glass substrate 10 so as to cover the gate electrode 1. The formed gate insulating film 11, the a-Si layer 2 formed on the gate insulating film 11 so as to be located in the channel region, the source electrode 3A and the drain electrode disposed on the a-Si layer 2 facing each other. 4A and an ohmic contact layer 12A formed between the a-Si layer 2, the source electrode 3A, and the drain electrode 4A.

The ohmic contact layer 12A is formed to cover the side surface of the peripheral end of the a-Si layer 2 and is in contact with the side surface of the channel layer 2a. As a result, the ohmic contact layer 12A and the contact portion 13A are also formed on the side of the channel layer 2a. Therefore, when the gate voltage Vgs is applied under the electrostatic charge, the source electrode 3A and the drain electrode 4A are directly connected to the channel layer 2a via the contact portion 13A of the ohmic contact layer 12A. , The drain current Ids (see the dashed arrows) flows through the resistive layer 2b.

Next, the manufacturing method of the thin film transistor which concerns on Embodiment 1 of this invention shown in FIG. 1 and FIG. 2 is demonstrated, referring the top view of FIG. 3 thru | or 6 which shows the manufacturing process of a thin film transistor.

In FIG. 3 (first step), the gate electrode 1 is formed on the glass substrate 10 to correspond to the channel region.

Next, in FIG. 4 (second step), the gate insulating film 11 is formed on the glass substrate 10 so as to cover the entire glass substrate 10 including the surface of the gate electrode 1 by the PCVD method. And successively, an i-Si layer is formed on the gate insulating film 11 so as to be located in the channel region, and successively, an island-like a-Si layer 2 is formed by photolithography and etching.

Next, in Fig. 5 (third step), the n + a-Si layer is formed over the entire surface of the glass substrate 10 including the gate electrode 1, the gate insulating film 11 and the a-Si layer 2 by the PCVD method. Formed ohmic contact layer 12A. Then, the source and drain metal layers are formed on the ohmic contact layer 12A by the sputtering method, and are opposed to each other on the a-Si layer 2 via the ohmic contact layer 12A by the photolithography and etching method. The source electrode 3A and the drain electrode 4A are formed.

In FIG. 5 (third step), only the ohmic contact layer 12A (n + a-Si layer) on the a-Si layer 2 is representatively shown. In this step, the ohmic contact layer 12A is used to form the gate insulating film 11. It is also formed on the glass substrate 10 included.

Finally, all ohmic contact layers 12A except for the lower portions of the source electrode 3A and the drain electrode 4A are removed by dry etching in FIG. 6 (fourth step), and the source electrode 3A and the drain electrode are removed. The ohmic contact layer 12A between (4A) is removed. Thereby, the thin film transistor shown in FIG. 1 and FIG. 2 is comprised.

That is, immediately below the source electrode 3A and the drain electrode 4A, there is necessarily an ohmic contact layer 12A in contact with the side surface of the peripheral end of the a-Si layer 2, so that the source electrode 3A and the drain are provided. The electrode 4A is always a structure overlapping in the form which overlaps with the edge part of the island of the a-Si layer 2.

As described above, according to Embodiment 1 of the present invention, after the gate insulating film 11 and the i-Si layer are formed by the PCVD method, an island shape is formed inside the gate electrode 1 using photolithography and etching techniques. After the a-Si layer 2 is formed, the ohmic contact layer 12A (n + a-Si layer) is formed by a PCVD method, whereby the side portion of the island-like a-Si layer 2 is also an ohmic contact layer ( 12A), and then a source electrode 3A and a drain electrode 4A are formed on the gate electrode 1 via the gate insulating film 11 and the ohmic contact layer 12A, and the exposed ohmic contact is formed. The layer 12A is removed to obtain a TFT structure.

As a result, the channel layer 2a formed in the a-Si layer 2 by the application of the gate voltage Vgs is directly connected to the source electrode 3A and the drain electrode 4A via the ohmic contact layer 12A. Since it is connected, like a general MOS transistor using crystalline silicon, a TFT structure capable of flowing a current without interposing a resistive layer 2b can be realized even in a thin film transistor having a bottom gate structure. Therefore, the thin film transistor according to Embodiment 1 of the present invention can satisfactorily flow the drain current Ids with reduced resistance loss even at a low drain voltage Vds. In addition, due to the decrease in the charging resistance, for example, the lack of data charging into the liquid crystal cell of the liquid crystal display device can be reduced.

Fig. 7 is a characteristic diagram showing an increase effect of the drain current Ids according to the first embodiment of the present invention, and the drain voltage Vds (horizontal axis) at each gate voltage Vgs = 20V, 15V, 10V, and 5V. And the relationship between the drain current Ids (vertical axis) is shown. In FIG. 7, the dotted line curves show the characteristics of the conventional thin film transistor structure shown in FIGS. 12 and 13, and the solid line curves show the characteristics of the thin film transistor structure according to the first embodiment of the present invention shown in FIGS. 1 and 2. Indicates.

Referring to FIG. 7, in the thin film transistor according to the first embodiment of the present invention, the characteristic (solid line curve) of the drain current Ids is low in comparison with the conventional characteristic (dashed line curve) for any gate voltage Vgs. It is clear that the effect of increasing the current is remarkable with respect to the drain voltage Vds < 20V, and even if the drain voltage Vds is low, the drain current Ids flows well.

In the conventional thin film transistor structures shown in FIGS. 12 and 13, the drain voltage Vds is affected by the influence of the resistive layer 2b (resistance component) in the a-Si layer 2 which is the path of the drain current Ids. When this decreases, the drain current Ids decreases like a dotted line curve. In addition, when the gate voltage Vgs applied to the gate electrode 1 is lowered, the thickness of the channel layer 2a in the a-Si layer 2 becomes smaller, and conversely, the resistance layer 2b becomes larger, so that the drain current Ids is obtained. Becomes even smaller.

On the other hand, in the structure of the thin film transistor according to the first embodiment of the present invention shown in Figs. 1 and 2, it is formed in the a-Si layer 2 by the gate voltage Vgs applied to the gate electrode 1. Since the channel layer 2a, the source electrode 3A, and the drain electrode 4A are directly connected through the ohmic contact layer 12A (without a large resistance component), the reduction of current caused by the resistance layer 2b is achieved. Without being affected, the drain current Ids can be flowed well even in a region where the drain voltage Vds is low.

Embodiment 2

Although the thin film transistor of Embodiment 1 mentioned above is not mentioned about a channel protective film, it is naturally applicable to the structure of the channel protective thin film transistor which has a channel protective film.

8 is a plan view showing a thin film transistor according to Embodiment 2 of the present invention, for example, in the case of a channel protected thin film transistor, and FIG. 9 is a cross-sectional view taken along the line CC ′ in FIG. 8. 1 and 2 described above with reference to FIGS. 8 and 9 are denoted by the same reference numerals as those described above, and the description thereof is omitted.

8 and 9, the same as that of the first embodiment except that the channel protective film 14 is formed on the surface of the a-Si layer 2 positioned between the source electrode 3A and the drain electrode 4A.

8 and 9, in the case of forming the channel protective film 14 on the a-Si layer 2, the thickness of the a-Si layer 2 (typically 100 is the case of normal exposure use using a mask). It is not necessary to set the limit below nm).

On the other hand, when the channel protective film 14 is formed by back exposure from the back surface of the glass substrate 10 using a positive resist, light is absorbed by the a-Si layer 2 and the exposure intensity is reduced. Therefore, the thickness of the a-Si layer 2 is limited to around 100 nm at maximum.

Embodiment 3

The thin film transistor according to the first embodiment described above is not particularly mentioned for the planar shape of the a-Si layer 2, the source electrode 3A, and the drain electrode 4A, but it is naturally applicable to the U-shaped thin film transistor structure. .

10 is a plan view showing a thin film transistor according to Embodiment 3 of the present invention, for example, with a U-shaped thin film transistor, and FIG. 11 is a cross-sectional view taken along the line D-D 'in FIG. 1 and 2 described above with reference to Figs. 10 and 11, the same reference numerals are given to the above, or " B "

In FIG. 10, the source electrode 3B is formed in a U-shape in a planar manner to surround both sides of the drain electrode 4B so that a large drain current Ids can flow, and the drain electrode 4B is the source electrode 3B. It is arranged in the U-shaped central part of. As a result, the gate electrode 1, the a-Si layer 2B, the source electrode 3B, and the drain electrode 4B realize a U-shaped TFT structure.

In the case of applying the U-shaped thin film transistor structures shown in FIGS. 10 and 11, a mask used for forming an a-Si layer in an island shape is formed on the lower a-Si layer 2B in which the drain electrode 4B is formed. It is necessary to form the slit 15 using the contact portion 13B so that the ohmic contact layer 12B below the drain electrode 4B and the sidewall of the a-Si layer 2B come into contact with each other. As a result, the drain electrode 4B and the channel layer 2a can be directly connected to each other without the resistance layer 2b of the a-Si layer 2B as described above.

In addition, although the glass substrate 10 was used as an insulated substrate in Embodiment 1-3 mentioned above, another insulated substrate can be used.

In addition, although an a-Si layer was used as an intrinsic semiconductor layer and a low resistance semiconductor layer, another semiconductor layer can be used.

In addition, the thin film transistor may be applied to the peripheral circuit portion or the pixel portion of the liquid crystal display.

Similarly, even when the thin film transistor is applied to an OLED (Organic Light-Emitting-Diode) display device, the charge charge retention characteristics of the OLED display device using the a-Si thin film transistor can be improved.

In addition, the thin film transistor may be used in a peripheral circuit portion of a display device and may be used in a pixel portion where a large current is not required.

1 is a plan view schematically showing a thin film transistor according to Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view taken along line BB ′ in FIG. 1.

3 is a plan view showing a first step in the method for manufacturing a thin film transistor according to Embodiment 1 of the present invention.

4 is a plan view showing a second step in the method for manufacturing a thin film transistor according to Embodiment 1 of the present invention.

5 is a plan view showing a third step of the method for manufacturing a thin film transistor according to Embodiment 1 of the present invention.

6 is a plan view showing a fourth step in the method for manufacturing a thin film transistor according to Embodiment 1 of the present invention.

7 is a characteristic diagram for explaining the effect of the thin film transistor according to Embodiment 1 of the present invention.

8 is a plan view schematically showing a thin film transistor according to Embodiment 2 of the present invention.

9 is a cross-sectional view taken along the line CC ′ in FIG. 8.

10 is a plan view schematically showing a thin film transistor according to Embodiment 3 of the present invention.

It is sectional drawing by the D-D 'line | wire in FIG.

12 is a plan view schematically showing a conventional thin film transistor.

It is sectional drawing by the AA 'line | wire in FIG.

* Description of the symbols for the main parts of the drawings *

1: gate electrode

2, 2B: a-Si layer (amorphous silicon layer, intrinsic semiconductor layer, i-Si layer)

2a: channel layer 3b: resistive layer

3A, 3B: source electrode 4A, 4B: drain electrode

10 glass substrate (insulating substrate) 11 gate insulating layer

12: ohmic contact layer (low resistance semiconductor layer, n + a-Si layer)

13A, 13B: contact portion 14: channel protective film

15: Slit Ids: Drain Current

Vds: Drain Voltage Vgs: Gate Voltage

Claims (11)

A gate electrode formed on an insulating substrate, an intrinsic semiconductor layer disposed on the gate electrode via a gate insulating film, and a source electrode and a drain electrode disposed on the intrinsic semiconductor layer via a low resistance semiconductor layer; A thin film transistor that forms a channel region on an opposite portion of the source electrode and the drain electrode, And the source electrode and the drain electrode are configured to be directly connected to a portion where the channel layer of the intrinsic semiconductor layer is formed via the low resistance semiconductor layer. The method of claim 1, And the intrinsic semiconductor layer and the low resistance semiconductor layer are formed of an amorphous silicon layer. The method of claim 1, A channel protective film formed on a surface of the channel region between the source electrode and the drain electrode, And the thickness of the intrinsic semiconductor layer is set to 100 nm or less. The method of claim 1, And the source electrode is formed in a U shape, and the drain electrode is disposed at a central portion of the U shape of the source electrode. A gate electrode, An amorphous intrinsic semiconductor layer overlaid with the gate electrode and the insulating film interposed therebetween; A source electrode and a drain electrode formed to face the overlapping portion with the intrinsic semiconductor layer on the insulating film on which the intrinsic semiconductor layer is formed; And an ohmic contact layer formed between the source electrode and the drain electrode and the intrinsic semiconductor layer, and covering the top and side surfaces of an overlapping portion of the intrinsic semiconductor layer captured by the source electrode and the drain electrode. Thin film transistor. A gate electrode, An amorphous intrinsic semiconductor layer overlaid with the gate electrode and the insulating film interposed therebetween; A source electrode and a drain electrode using the intrinsic semiconductor layer as a channel; An ohmic contact layer formed between the source electrode and the drain electrode, and the intrinsic semiconductor layer, The intrinsic semiconductor layer has a channel layer between the source electrode and the drain electrode, and a resistance layer positioned below the channel layer. The ohmic contact layer is formed to directly connect with the channel layer and the resistance layer of the intrinsic semiconductor layer; The source electrode and the drain electrode are formed to overlap the channel layer and the resistance layer of the intrinsic semiconductor layer with the ohmic contact layer therebetween. Forming the gate electrode on an insulating substrate; Forming an intrinsic semiconductor layer island on the gate electrode with a gate insulating film interposed therebetween; Forming a low resistance semiconductor layer on the gate insulating film including the intrinsic semiconductor layer island; Forming a source electrode and a drain electrode on the upper portion including the peripheral end of the intrinsic semiconductor layer island through the low resistance semiconductor layer to form a channel region between the opposite portions of the source electrode and the drain electrode; Removing the low resistance semiconductor layer except for the lower portions of the source electrode and the drain electrode; The low resistance semiconductor layer is formed so as to cover a part of the portion where the channel layer of the intrinsic semiconductor layer is formed. The method of claim 7, wherein And forming a channel passivation layer that protects the channel region of the intrinsic semiconductor layer located between the source electrode and the drain electrode. Forming the gate electrode on an insulating substrate; Forming a gate insulating film covering the gate electrode; Forming an intrinsic semiconductor layer pattern overlapping the gate electrode on the gate insulating film; Forming an ohmic contact layer covering the intrinsic semiconductor layer pattern; Forming a source electrode and a drain electrode using the intrinsic semiconductor layer as a channel on the ohmic contact layer; And removing the exposed ohmic contact layer by using the source electrode and the drain electrode as a mask. The thin film transistor according to any one of claims 1 to 6 is used for a pixel portion or a peripheral circuit portion. The thin film transistor according to any one of claims 1 to 6 is used for a pixel portion or a peripheral circuit portion.

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