KR20080038719A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor package and a manufacturing method of the same are provided to reduce a process time and a manufacturing cost by eliminating an additional sealing process. A substrate(1) includes a first surface(11) and a second surface(12). A cavity(15) is formed in the first surface. The second surface is opposite to the first surface. A circuit pattern is formed on the second surface. A conductive bump(51) is electrically connected to circuit patterns(21,22). A semiconductor chip(5) is arranged in the inside of the cavity. A via hole is formed to open a part of the circuit pattern of the substrate. The conductive bump is inserted into the via hole. The cavity is formed to expose the circuit pattern. The conductive bump is formed on the circuit pattern.

Description

Semiconductor package and method for manufacturing same

1 is a cross-sectional view illustrating a semiconductor package according to a first embodiment of the present invention.

2A to 2D are cross-sectional views illustrating a method of manufacturing the semiconductor package shown in FIG. 1.

3 is a cross-sectional view illustrating a state in which the semiconductor packages illustrated in FIG. 1 are stacked.

4 is a cross-sectional view illustrating a semiconductor package in accordance with a second embodiment of the present invention.

5A through 5C are cross-sectional views illustrating a method of manufacturing the semiconductor package shown in FIG. 3.

Explanation of symbols on the main parts of the drawings

1: semiconductor substrate 3: solder ball

5: semiconductor chip 11: first surface

12: second side 13: internal wiring

14: via hole 15: cavity

15a: Bottom surface 21: First circuit pattern

22: second circuit pattern 31: first insulating film pattern

31a: first opening portion 32: second insulating film pattern

32a: second opening 51: conductive bump

52: insulation member

The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package and a method for manufacturing the same that can reduce the size of the semiconductor package, and can effectively stack a plurality of semiconductor packages.

In recent years, with the rapid spread of information media such as computers, semiconductor devices are also rapidly developing. In terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity. In response to these demands, semiconductor processing technologies have been developed in the direction of improving integration, reliability, response speed, and the like of the semiconductor device.

In general, a semiconductor device includes a Fab process for forming an electrical circuit including electrical elements on a silicon substrate used as a semiconductor substrate, and an EDS (electrical) for inspecting electrical characteristics of the semiconductor devices formed in the fab process. die sorting) and a package assembly process for encapsulating and individualizing the semiconductor devices with an epoxy resin.

Recently, chip scale packages (CSPs), stacked packages, and the like have been developed in order to produce higher density semiconductor devices by improving the mounting efficiency per unit volume of semiconductor chips in semiconductor packages.

In the stacked package, at least two or more semiconductor packages are stacked vertically. Each semiconductor package includes a semiconductor chip and a substrate on which the semiconductor chip is mounted. In the stacked package, substrates and semiconductor chips are alternately arranged, and each substrate is electrically connected by a conductive connection member such as solder balls.

In particular, in order to stack a plurality of semiconductor packages, it is important to reduce the thickness of individual semiconductor packages, and research on this is being actively conducted. However, in the conventional semiconductor package, since the semiconductor chip is mounted and the sealing member is formed around the semiconductor chip, there is a practical limit in reducing the thickness of the semiconductor package.

In addition, as technology advances, it is required that the semiconductor device and the semiconductor package have a fast response speed, and have a high level of signal integrity (SI).

One object of the present invention for solving the above problems is to provide a semiconductor package that is thin, can effectively stack a plurality of semiconductor packages, and excellent electrical performance.

Another object of the present invention is to provide a method of manufacturing the semiconductor package.

A semiconductor package according to a preferred embodiment of the present invention for achieving the object of the present invention, a substrate having a first surface with a cavity (cavity), and a second surface opposite to the first surface and the circuit pattern is formed And a semiconductor chip electrically connected to the circuit pattern and disposed inside the cavity.

Via holes may be formed in the substrate to open a portion of the circuit pattern, and the conductive bumps may be accommodated in the via holes.

In example embodiments, the cavity may be formed to expose the circuit pattern, and the conductive bump may be disposed on the circuit pattern.

The semiconductor package may further include an insulating member formed on a bottom surface of the semiconductor chip opposite to the first surface to fill a space between the conductive bumps. An insulating film pattern having an opening that partially exposes the circuit pattern may be formed on the second surface of the substrate, and a conductive connection member may be formed to fill the opening so as to be electrically connected to the circuit pattern. Here, the conductive connecting member is preferably a solder ball (solder ball).

On the other hand, in order to achieve the another object of the present invention, a semiconductor package manufacturing method according to a preferred embodiment of the present invention, forming a circuit pattern on the substrate, the insulating film pattern having an opening for partially exposing the circuit pattern on the circuit pattern To form. Subsequently, a portion of the first surface opposite to the surface on which the circuit pattern is formed is removed to form a cavity, the conductive bumps are disposed to be electrically connected to the circuit pattern, and the semiconductor chip is disposed. Subsequently, a conductive connection member for embedding the opening is attached to be electrically connected to the circuit pattern.

The method of manufacturing a semiconductor package may further include forming a via hole in communication with the cavity and the circuit pattern.

In example embodiments, the conductive bumps may be accommodated in the via holes.

The cavity is formed by removing a substrate until the circuit pattern is exposed.

In some embodiments, the conductive bumps may be disposed to be directly and electrically connected to the circuit pattern.

An insulating member may be formed on the bottom surface of the semiconductor chip opposite to the first surface to fill a space between the conductive bumps.

Hereinafter, a semiconductor package and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements. In the accompanying drawings, the dimensions of the structures are shown in an enlarged scale than actual for clarity of the invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described on the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Example 1

1 is a cross-sectional view of a semiconductor package according to a first exemplary embodiment of the present invention, and FIGS. 2A to 2D are cross-sectional views illustrating a method of manufacturing the semiconductor package of FIG. 1.

As shown in FIG. 1, in the semiconductor package, a cavity 15, which forms a space in which the semiconductor chip 5 is to be mounted, is formed on the first surface 11 and is a second surface that is opposite to the first surface. A semiconductor chip having a substrate 1 having a second circuit pattern 22 formed thereon and a conductive bump 51 electrically connecting the semiconductor chip 5 and the second circuit pattern 22 to each other ( 5) includes.

The substrate 1 has a plate shape and may be, for example, a printed circuit board (PCB) having a thin thickness.

Predetermined circuit patterns 21 and 22 are formed on the first and second surfaces 11 and 12, respectively, and the circuit patterns 21 and 22 are partially exposed on the circuit patterns 21 and 22. The insulating film patterns 31 and 32 having the openings 31a and 32a are formed.

An internal wiring 13 is formed inside the substrate 1 to electrically connect the first circuit pattern 21 and the second circuit pattern 22.

Here, the first circuit pattern 21 and the first insulating film pattern 31 are portions that electrically connect adjacent semiconductor packages to each other when the semiconductor packages are stacked.

The substrate 1 is formed with a cavity 15 having a predetermined volume to remove a portion of the first surface 11 so that the semiconductor chip 5 may be mounted therein. Here, the cavity 15 is preferably formed to have a volume and a cross-sectional area of a size sufficient to accommodate the semiconductor chip 5 therein, and have a cross-sectional shape corresponding to the semiconductor chip 5. It is preferable to form so that.

The conductive bumps 51 are formed on the bottom surface of the semiconductor chip 5 opposite to the first surface 11. In particular, a via hole exposing a part of the second circuit pattern 22 is formed in the substrate 1 between the bottom surface of the semiconductor chip 5 and the second circuit pattern 22. 51 is accommodated in the via hole 14 and electrically connected to the second circuit pattern 22.

The via hole 14 exposes the second circuit pattern 22 by a predetermined portion, and its size and cross-sectional shape are determined by the cross-sectional shape of the conductive bump 51, but preferably has a cylindrical shape.

On the other hand, as the technology advances, the conductive bumps 51 are gradually densely arranged and have a fine size, so that the via holes 14 correspond to the minute conductive bumps 51 so that the minute holes are tightly spaced. Since it should be formed as, it is preferable to form the via hole 14 using a laser.

The conductive bumps 51 are all formed of a metal having high electrical conductivity. For example, the conductive bumps 51 may include gold (Au), silver (Ag), copper (Cu), nickel (Ni), or tin ( Sn) any metal can be used.

In addition, an insulating member 52 may be formed between the bottom surface of the semiconductor chip 5 and the bottom surface 15a to fill a space between the conductive bumps 51. The insulating member 52 not only prevents the conductive bumps 51 from being electrically connected to each other, but also serves to reduce the stress applied to the conductive bumps 51.

Therefore, according to the present invention, since the semiconductor chip 5 is connected to the circuit pattern 22 through the conductive bumps 51, the electrical performance is stable and has characteristics such as a high level of signal integrity.

A conductive connection member electrically connected to the second circuit pattern 22 on the second insulating layer pattern 32 is formed to fill the second opening 32a.

The conductive connection member serves to electrically connect the first circuit pattern of one semiconductor package and the second circuit pattern of another semiconductor package in adjacent semiconductor packages when the semiconductor packages are stacked.

The conductive connecting member preferably uses solder balls 3.

On the other hand, the second insulating layer pattern 32 defines an area in contact with the solder balls 3 in the second circuit pattern 22, and electrically insulates the solder balls 3 from being connected to each other. .

In addition, the second insulating layer pattern 32 serves as a solder mask for forming the solder ball 3. That is, the solder ball 3 is prevented from being formed in an undesired area and influences the shape of the solder ball 3 after reflow.

Hereinafter, a method of manufacturing a semiconductor package according to the first embodiment will be described with reference to FIGS. 2A to 2D.

First, the substrate 1 on which the circuit patterns 21 and 22 and the insulating layer patterns 31 and 32 are formed is formed on the first and second surfaces 11 and 12, respectively.

Subsequently, a portion of the first surface 11 of the substrate 1 is removed to form a cavity 15. Here, the cavity 15 removes the first insulating layer pattern 31 and the first circuit pattern 21, and removes the first insulating layer pattern 31 and the first circuit pattern 21 to a predetermined depth up to the inside of the substrate 1. It is desirable to remove only until not exposed.

For example, the cavity 15 may be drilled at the first surface 11 to form a volume of a sufficient size so that the semiconductor chip 5 may be accommodated therein. It can form by removing (). In addition, the cavity 15 is formed to have a cross-sectional shape corresponding to the shape of the semiconductor chip 5, and preferably has a cross-sectional area larger than the size of the semiconductor chip 5. On the other hand, removing the substrate 1 may use a variety of methods, including using a drill or etching.

Subsequently, a via hole 14 partially exposing the second circuit pattern 22 is formed in the bottom surface 15a of the cavity 15.

For example, the via hole 14 is formed by irradiating a laser onto the substrate 1 forming the bottom surface 15a by removing the substrate 1 until the second circuit pattern 22 is exposed. It is possible. Here, the via hole 14 may be formed in substantially various ways to remove the substrate 1 in addition to the laser.

Next, the semiconductor chip 5 is disposed to be in contact with the second circuit pattern 22 by inserting the conductive bump 51 into the via hole 14.

Subsequently, an insulating member 52 is formed in the space between the bottom surface of the semiconductor chip 5 and the bottom surface of the cavity 15 to fill the space between the conductive bumps 51. The insulating member 52 prevents the conductive bumps 51 from being electrically connected to each other, and reduces the stress applied to the conductive bumps 51.

Subsequently, a solder ball 3 is formed on the second insulating layer pattern 32 to fill the second opening 32a and to be electrically connected to the second circuit pattern 22.

After the solder ball 3 fills the solder ball 3 in the second opening 32a, the solder ball 3 is put into a furnace at about 200 to 250 ° C. to perform a reflow process. As the solder ball 3 is melted, the second opening 32a is embedded and fused to the second circuit pattern 22.

Here, the solder ball 3 may be an alloy of lead (Pb) and tin (Sn) or tin (Sn) -based alloy.

Semiconductor Package Stacking Method

3 is a diagram illustrating a state in which two semiconductor packages illustrated in FIG. 1 are stacked.

Hereinafter, the stacking of the semiconductor package according to the present invention will be described with reference to FIG. 3. Here, although two semiconductor packages are stacked in the drawing, it is possible to stack three or more semiconductor packages, and the method of stacking a plurality of semiconductor packages is also substantially the same. Since the semiconductor package has been described in detail in the first embodiment, redundant description thereof will be omitted.

As shown in FIG. 3, the first semiconductor package A is electrically connected to each other through the solder balls 3b of the second semiconductor package A placed thereon.

In detail, the first circuit pattern 21a of the first semiconductor package A and the second circuit pattern 22b of the second semiconductor package B are solder formed on the second circuit pattern 22b. It is electrically connected with each other by the ball 3b.

That is, the first insulating film pattern 31a of the first semiconductor package A and the second insulating film pattern 22b of the second semiconductor package B are exactly aligned, and then the first semiconductor package A The first circuit pattern 21a and the second circuit pattern 22b of the second semiconductor package B are brought into contact with each other by the solder balls 3b. Subsequently, when heat is applied to the stacked semiconductor packages, the solder balls 3b are fused and the bonding of the semiconductor packages is completed.

Each of the semiconductor packages A and B electrically connects each of the semiconductor chips 5a and 5b through internal wirings 13a and 13b formed therein.

That is, the semiconductor chips 5a and 5b of each of the semiconductor packages A and B are electrically connected to the second circuit patterns 22a and 22b through the conductive bumps 51a and 51b, respectively. The 22a and 22b are electrically connected with the 1st circuit patterns 21a and 21b mutually through the internal wiring 13a and 13b. The first circuit pattern 21a of the first semiconductor package A and the second circuit pattern 22b of the second semiconductor package B are electrically connected to each other through the solder ball 3b.

Example 2

4 is a cross-sectional view illustrating a semiconductor package according to a second embodiment of the present invention, and FIGS. 5A to 5C are cross-sectional views illustrating a method of manufacturing the semiconductor package of FIG. 4.

Hereinafter, the semiconductor package and the manufacturing method according to the second embodiment of the present invention will be described with reference to FIGS. 4 to 5C, and the same components as those in the first embodiment have been given the same names. Omit.

Unlike the first embodiment, in the semiconductor package according to the second embodiment, the substrate is removed to form a cavity until the circuit pattern is exposed, and a conductive bump is directly disposed on the exposed circuit pattern. do.

Although the second embodiment is suitable for the packaging method in the case of mounting a semiconductor chip on a substrate on which three or more metal wiring layers are formed, it is also possible to use the same packaging method as in the first embodiment.

As shown in FIG. 4, the semiconductor package according to the second embodiment includes a semiconductor chip 5, a substrate 100 on which a cavity 115 on which the semiconductor chip 5 is mounted, and the substrate 100 are formed. A semiconductor chip 5 including conductive bumps 151 electrically connected to a circuit pattern of the semiconductor chip 5.

The substrate 100 has a plate shape having a first surface 101 on which the cavity 115 is formed and a second surface 102 that is a surface opposite to the first surface 101. For example, the substrate 100 may be a thin printed circuit board (PCB).

The first circuit pattern 121 and the first insulating film pattern 131 are formed on the first surface 101, and the second circuit pattern 122 and the second insulating film pattern 132 are formed on the second surface 102. ) Is formed. In addition, a third circuit pattern 123 is formed in the substrate 100.

Hereinafter, among the surfaces in which the substrate 100 is in contact with the third circuit pattern 123, the surface formed in the same direction as the first surface 101 may be the third surface 103 (that is, the third pattern in FIG. 4). The upper surface of 123 and the surface opposite to the third surface 103 are referred to as a fourth surface 104.

The first insulating layer pattern 131 may have a first opening 121a that partially exposes the first circuit pattern 121, and the second insulating layer pattern 132 may partially cover the second circuit pattern 122. A second opening 122a is formed to expose. The third circuit pattern 123 includes a third opening 123b for partially exposing the substrate 100 and a connection portion 123a in which the conductive bumps 151 are formed.

An internal wiring 113 is formed in the substrate 100 to electrically connect the circuit patterns 121, 122, and 123, respectively.

The cavity 115 is formed by removing the substrate 100 until the third circuit pattern 123 is exposed. That is, the cavity 115 exposes the connection portion 123a and the third opening portion 123b of the third circuit pattern 123.

Here, the third opening 123b is disposed on the same plane with the surface of the connecting portion 123a and the third opening 123b due to the original shape of the third circuit pattern 123. However, the exposed portion of the third circuit pattern 123 may be processed to change the shape of the third opening 123b and the connecting portion 123a to form a desired pattern.

The semiconductor chip 5 is disposed inside the cavity 115, and the conductive bumps 151 are disposed to be directly and electrically connected to an upper surface of the connection part 123a.

Meanwhile, the semiconductor chip 5 may be directly disposed on the third circuit pattern 123 or the connection portion 123a, but the conductive bump 151 is formed to form the semiconductor chip 5 and the third circuit. The patterns 123 may be spaced apart from each other.

In addition, as shown in FIG. 4, an insulating member 152 that prevents the conductive bumps 151 from being electrically connected to each other in a space between the bottom surface of the semiconductor chip 5 and the conductive bumps 151. Is formed. The insulating member 152 electrically insulates the conductive bumps 151 and reduces the stress applied to the conductive bumps 151.

A solder ball 3 is formed on the second insulating layer pattern 132 to fill the second opening 122a and electrically connect the second circuit pattern 122. The solder balls 3 are formed to completely fill the second openings 122a and electrically connect the semiconductor packages when the semiconductor packages are stacked.

Hereinafter, a method of manufacturing a semiconductor package according to a second embodiment of the present invention will be described with reference to FIGS. 5A to 5C.

First, the circuit patterns 121 and 122 and the insulating film patterns 131 and 132 are formed on the first surface 101 and the second surface 102, respectively, and the substrate 100 having the third circuit pattern 123 formed therein is provided. do.

Subsequently, a portion of the first surface 101 of the substrate 100 is removed to form a cavity 115 on which the semiconductor chip 5 is to be mounted. Here, the cavity 115 is formed by removing the substrate 100 until the third circuit pattern 123 is exposed.

The cavity 115 has a shape corresponding to the shape of the semiconductor chip 5 and forms a volume of a size that the semiconductor chip 5 can be sufficiently accommodated therein. For example, the cavity 115 forms a rectangular parallelepiped space.

Subsequently, the semiconductor chip 5 is disposed by arranging the conductive bumps 151 to be electrically connected to the upper portion of the connection portion 123a in the cavity 115.

Here, the insulating member 152 not only insulates the electrically conductive bumps 151 from being electrically connected to each other, but also maintains a predetermined gap between the semiconductor chip 5 and the third circuit pattern 123. Do it.

On the other hand, when the desired circuit pattern is to be formed on the exposed portion of the third circuit pattern 123, the portion except for the portion to be coupled with the conductive bump 151 in the exposed third circuit pattern 123. The process of removing the substrate 100 may be further performed until the substrate 100 is exposed. That is, the removed portion exposes the substrate 100 to the third opening 123b, and the remaining portion becomes the connection portion 123a connected to the conductive bump 151. In this case, the insulating member 152 is preferably formed to fill the space between the conductive bump 151 and the third opening (123b).

Subsequently, the solder balls 3 electrically connected to the second circuit patterns 122 are formed in the second insulating layer pattern 132.

After the solder ball 3 is filled with the solder ball 3 in the second opening 122a, the solder ball 3 is heated to a temperature of about 200 to 250 ° C., so that the solder ball 3 is connected to the second opening 122a. Is embedded and the solder ball 3 is fused to the second circuit pattern 122.

The semiconductor package according to the second embodiment can also be laminated by electrically connecting the first circuit pattern of one semiconductor package and the second circuit pattern of another semiconductor package through the solder balls 3. Since the stacking method of the semiconductor package has been described in the first embodiment, detailed description thereof will be omitted.

As described above, the semiconductor package according to the preferred embodiment of the present invention can reduce the thickness of the package, it is possible to effectively stack a plurality of semiconductor packages. In addition, since there is no need to perform a separate sealing process after mounting the semiconductor chip, the effect of saving time and cost consumed in the process is great.

In addition, according to the present invention, the response speed of a semiconductor chip is fast, and as a plurality of semiconductor packages are stacked, it is advantageous to improve the integration and performance of a semiconductor product.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (12)

A substrate having a first surface having a cavity and a second surface opposite to the first surface and having a circuit pattern formed thereon; And a semiconductor chip electrically conductively connected to the circuit pattern, wherein the semiconductor chip is disposed in the cavity. The semiconductor package of claim 1, wherein a via hole is formed in the substrate to open a portion of the circuit pattern, and the conductive bump is accommodated in the via hole. The semiconductor package of claim 1, wherein the cavity is formed to expose the circuit pattern, and the conductive bump is disposed on the circuit pattern. The semiconductor package of claim 1, further comprising an insulating member formed on a bottom surface of the semiconductor chip opposite to the first surface to fill a space between the conductive bumps. The semiconductor device of claim 1, further comprising: an insulating layer pattern on the second surface of the substrate, the insulating layer pattern having an opening to partially expose the circuit pattern; And And a conductive connection member filling the opening to be electrically connected to the circuit pattern. The semiconductor package of claim 4, wherein the conductive connection member is a solder ball. Forming a circuit pattern on the substrate; Forming an insulating film pattern having an opening on the circuit pattern to partially expose the circuit pattern; Removing a portion of the first surface opposite to the surface on which the circuit pattern is formed to form a cavity; Disposing a conductive bump so as to be electrically connected to the circuit pattern, and disposing a semiconductor chip; Attaching a conductive connection member to bury the opening to be electrically connected to the circuit pattern. The method of claim 7, further comprising forming a via hole in communication with the cavity and the circuit pattern. The method of claim 8, wherein the conductive bump is accommodated in the via hole. The method of claim 7, wherein the cavity is formed by removing a substrate until the circuit pattern is exposed. The method of claim 10, wherein the conductive bumps are disposed to be directly and electrically connected to the circuit pattern. 8. The method of claim 7, further comprising forming an insulating member on a bottom surface of the semiconductor chip opposite to the first surface to fill a space between the conductive bumps.

Images