KR20080033774A - Plasma display and driving method thereof - Google Patents

Abstract

A plasma display device and a driving method thereof are provided to generate sustain discharge pulses of various phases using a single sustain discharge circuit. A plasma display device includes plural first electrodes, first and second inductors, a capacitor, and first to fourth paths. A first terminal of the first inductor(L1) is connected to a first group of the first electrodes. A first terminal of the second inductor(L2) is connected to a second group of the first electrodes. The capacitor(Cer) is charged by a voltage between high and low level voltages of a sustain discharge pulse. The first path defines a path from the capacitor to a second terminal of the first inductor. The second path defines a path from the second terminal of the first inductor to the capacitor. The third path defines a path from the capacitor to a second terminal of the second inductor. The fourth path defines a path from the second terminal of the second inductor to the capacitor.

Description

Plasma display device and driving method thereof {PLASMA DISPLAY AND DRIVING METHOD THEREOF}

1 is a schematic conceptual diagram of a plasma display device according to an exemplary embodiment of the present invention.

2 is a diagram illustrating various examples of sustain discharge pulses according to an embodiment of the present invention.

3 is a schematic circuit diagram of a sustain discharge circuit according to an embodiment of the present invention.

4 is a signal timing diagram for generating a sustain discharge pulse as shown in FIG. 2A through a sustain discharge circuit according to an exemplary embodiment of the present invention.

5 is a diagram illustrating an operation of the sustain discharge circuit of FIG. 3 according to the signal timing of FIG. 4.

6 is a signal timing diagram for generating a sustain discharge pulse as shown in FIG. 2B through a sustain discharge circuit according to an exemplary embodiment of the present invention.

7 is a diagram illustrating an operation of the sustain discharge circuit of FIG. 3 according to the signal timing of FIG. 6.

8 is a signal timing diagram for generating a sustain discharge pulse as shown in FIG. 2C through a sustain discharge circuit according to an exemplary embodiment of the present invention.

9 is a diagram illustrating an operation of the sustain discharge circuit of FIG. 3 according to the signal timing of FIG. 8.

The present invention relates to a plasma display device and a driving method thereof, and more particularly, to an energy recovery circuit of a plasma display device.

The plasma display device is a device that displays characters or images using plasma generated by gas discharge. In general, a plasma display device is driven by dividing one frame into a plurality of subfields. Cells to be turned on and cells not to be turned on during the address period of each subfield are selected, and sustain discharge is performed on the cells to be turned on to actually display an image during the sustain period.

In particular, a sustain discharge pulse having a high level voltage and a low level voltage is alternately applied to the electrode which performs the sustain discharge during the sustain period. Here, the discharge space acts as a capacitive load between the scan electrode performing sustain discharge and the surface on which the sustain electrode is formed, and is invalid in addition to the power for discharging when the high level voltage and the low level voltage are applied due to the capacitive load. Power is needed. Energy recovery circuits are generally used to recover and reuse these reactive power. On the other hand, when one energy recovery circuit is used, the shape of the sustain discharge pulse that can be applied to the scan electrode or the sustain electrode is fixed to one. However, in order to secure design diversity, it is required to generate sustain discharge pulses having various phase differences by using one energy recovery.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for driving a plasma display device capable of generating sustain discharge pulses having various phase differences through one sustain discharge circuit.

A third diode electrically connected to the sword, wherein the fourth path includes a fourth diode electrically connected to the second end of the second inductor and a cathode of the fourth diode and the capacitor; It may include an eighth transistor electrically connected.

The plasma display device may set the fifth transistor and the seventh transistor to be turned on for a first period, and turn the first transistor and the third transistor to be turned on for a second period of time, and a third The controller may further include a controller configured to set the sixth transistor and the eighth transistor to a turned on state and to set the second transistor and the fourth transistor to a turned on state during a fourth period.

In addition, the plasma display device may set the fourth transistor and the fifth transistor to be turned on during the first period, and set the first transistor and the fourth transistor to be turned on during the second period, and then, during the third period. The first transistor and the seventh transistor are turned on, the third transistor and the sixth transistor are turned on for a fourth period, and the second transistor and the third transistor are turned on for a fifth period. And a controller configured to set the transistor to a turn on state, to set the second transistor and the eighth transistor to a turn on state for a sixth period, and to set the second transistor and the fourth transistor to a turn on state for a seventh period. It may include.

The plasma display device may set the fifth transistor and the eighth transistor to be turned on for a first period, and turn the first transistor and the fourth transistor to be turned on for a second period of time, and may be configured to turn on the third transistor. The controller may further include a controller configured to set the sixth transistor and the seventh transistor to a turned on state and to set the second transistor and the third transistor to a turned on state during a fourth period.

According to another feature of the present invention, a method of driving a plasma display device including a plurality of first electrodes to which a sustain discharge pulse is applied is provided. The driving method may include applying a first voltage to a first electrode of a first group of the plurality of first electrodes, and applying the first voltage to a first electrode of a second group of the plurality of first electrodes during a first period. Applying a voltage; During a second period of time a capacitor is charging a second voltage higher than the first voltage, a first inductor electrically connected between the capacitor and the first electrode of the first group and the first electrode of the first group Forming a first resonance path to raise a voltage of the first electrode of the first group to a third voltage higher than the second voltage; During the second period, a second resonance path is formed by the capacitor, a second inductor electrically connected between the capacitor and the first electrode of the second group, and the first electrode of the second group, thereby forming the second resonance path. Raising the voltage of the first group of electrodes to a fourth voltage higher than the second voltage; During a third period of time, applying a fifth voltage higher than the second voltage to voltages of the first electrode of the first group and the first electrode of the second group; During a fourth period, a third resonant path is formed by the first electrode, the first inductor, and the capacitor of the first group, such that the voltage of the first electrode of the first group is lower than the second voltage. Descending to; And forming a fourth resonance path with the first electrode, the second inductor, and the capacitor of the second group during the fourth period so that the voltage of the first electrode of the second group is lower than the second voltage. Lowering to seven voltages.

According to still another aspect of the present invention, a method of driving a plasma display device including a plurality of first electrodes to which a sustain discharge pulse is applied is provided. In this driving method, the first voltage is applied to a first electrode of a second group of the plurality of first electrodes while a first voltage is applied to a first electrode of a first group of the plurality of first electrodes. Doing; A capacitor charged with a second voltage higher than the first voltage in a state where the first voltage is applied to the first electrode of the second group, and electrically connected between the capacitor and the first electrode of the first group Forming a first resonant path with the first inductor and the first electrode of the first group to raise the voltage of the first group of electrodes to a third voltage higher than the second voltage; A second inductor electrically connected between the capacitor, the capacitor, and the first electrode of the second group in a state where a fourth voltage higher than the second voltage is applied to the first electrode of the first group; Forming a second resonance path with a first electrode of a second group to raise the voltage of the first electrode of the second group to a fifth voltage higher than the second voltage; In the state where the fourth voltage is applied to the first electrode of the second group, a third resonance path is formed by the first electrode, the first inductor, and the capacitor of the first group, thereby forming the first group of the first group. Lowering the voltage of the first electrode to a sixth voltage lower than the second voltage; And forming a fourth resonance path with the first electrode, the second inductor, and the capacitor of the second group while applying the first voltage to the first electrode of the first group. And lowering the voltage of the first electrode to a seventh voltage lower than the second voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, which means that it may further include other components, except to exclude other components unless otherwise stated.

In addition, the expression that voltage is maintained throughout the specification indicates that even if the potential difference between two specific points changes over time, the change is within an acceptable range of the design or the cause of the change is due to parasitic components that are ignored in the design practice of those skilled in the art. Include cases by. In addition, since the threshold voltage of a semiconductor device (transistor, diode, etc.) is very low compared to the discharge voltage, the threshold voltage is regarded as 0V and approximated.

A plasma display device and a driving method thereof according to an embodiment of the present invention will now be described in detail with reference to the drawings.

1 is a schematic conceptual diagram of a plasma display device according to an exemplary embodiment of the present invention, and FIG. 2 is a diagram illustrating various examples of sustain discharge pulses according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a sustain electrode driver 400, and a scan electrode driver 500. It includes.

The plasma display panel 100 includes a plurality of address electrodes A1 to Am extending in the column direction, and a plurality of sustain electrodes X1 to Xn and scan electrodes Y1 to Yn extending in pairs in the row direction. Include. In general, each of the sustain electrodes X1 to Xn is formed corresponding to each of the scan electrodes Y1 to Yn, and the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn are formed of the address electrodes A1 to Am. It is arranged to be orthogonal. At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms the discharge cell 110.

The controller 200 receives a video signal from the outside and outputs a driving control signal, and divides and drives one frame into a plurality of subfields having respective luminance weights. Each subfield includes an address period and a sustain period. The address electrodes, the sustain electrodes, and the scan electrode drivers 300, 400, and 500 respectively correspond to the address electrodes A1 to Am, the sustain electrodes X1 to Xn, and the scan electrodes Y1 to the driving control signals from the controller 200. Yn) is applied a driving voltage.

In detail, in each subfield, the address electrode, the sustain electrode, and the scan electrode driver 300, 400, and 500 select a discharge cell to be turned on and a discharge cell not to be turned on in the corresponding subfield among the plurality of discharge cells 100. .

During the sustain period of each subfield, as shown in FIG. 2, the sustain electrode driver 400 has a high level to an odd number of sustain electrodes (hereinafter, referred to as "Xodd electrodes") among the plurality of sustain electrodes X1 to Xn. A sustain discharge pulse having an alternating voltage Vs and a low level voltage 0V is applied, and a sustain discharge pulse is applied to even-numbered sustain electrodes (hereinafter, "Xeven electrodes") of the plurality of sustain electrodes X1 to Xn. do. As shown in (a), (b) and (c) of FIG. 2, the sustain discharge pulses applied to the Xodd electrode and the Xeven electrode have various phase differences. 2 (a), 2 (b) and (c) show a case where the sustain discharge pulses applied to the Xodd electrode and the Xeven electrode have a phase difference of 0 degrees, a phase difference of 0 to 180 degrees, and a phase difference of 180 degrees, respectively. Although not shown in FIG. 2, the scan electrode driver 500 applies a sustain discharge pulse to the Xodd electrode to apply a sustain discharge pulse to an odd-numbered scan electrode (hereinafter, referred to as a “Yodd electrode”) among the plurality of scan electrodes Y1 to Yn. It is applied in the opposite phase to the pulse, and the sustain discharge pulse is applied to the even-numbered scan electrodes (hereinafter, referred to as "Yeven electrodes") among the plurality of scan electrodes Y1 to Yn in the opposite phase to the sustain discharge pulses applied to the Xeven electrodes. do. In this way, the voltage difference between the Xodd electrode and the Yodd electrode and the Xeven electrode and the Yeven electrode, which form discharge cells with each other alternately has a Vs voltage and a -Vs voltage, so that the sustain discharge is repeatedly repeated a predetermined number of times in the discharge cell to be turned on. Happens.

Next, FIG. 2 is demonstrated in detail with reference to FIGS. 3-9 about the sustain discharge circuit which supplies a sustain discharge pulse.

3 is a schematic circuit diagram of a sustain discharge circuit 410 according to an embodiment of the present invention. In FIG. 3, only the sustain discharge circuit 410 connected to the plurality of sustain electrodes X1 to Xn is illustrated for convenience of description, and the sustain discharge circuit 410 may be formed in the sustain electrode driver 400 of FIG. 1. . In addition, the sustain discharge circuit 510 connected to the plurality of scan electrodes Y1 to Yn may have the same structure as that of the sustain discharge circuit 410 of FIG. 3, and may have a structure different from that of the sustain discharge circuit 410 of FIG. 3. Can be.

The sustain discharge circuit 410 may be connected between the Xodd electrode and the Xeven electrode, or may be connected only between some predetermined storage electrodes of the plurality of sustain electrodes X1 to Xn. In the sustain discharge circuit 410, capacitive components formed between Xodd and Yodd electrodes and Xeven and Yeven electrodes, which form discharge cells, are illustrated as panel capacitors Cp.

As shown in FIG. 3, the sustain discharge circuit 410 according to an exemplary embodiment of the present invention includes transistors Xos, Xog, Xor, Xer, Xes, Xeg, Xof, and Xef, and diodes (Dor, Dof, Der, and Def). Inductors L1 and L2 and a power recovery capacitor Ce are included. In FIG. 3, the transistors Xos, Xog, Xor, Xer, Xes, Xeg, Xof, and Xef are illustrated as n-channel field effect transistors, in particular, n-channel metal oxide semiconductor (NMOS) transistors. Xor, Xer, Xes, Xeg, Xof, and Xef) form a body diode in the direction from the source to the drain. And other transistors having similar functions instead of NMOS transistors may be used as these transistors (Xos, Xog, Xor, Xer, Xes, Xeg, Xof, Xef). In FIG. 3, the transistors Xos, Xog, Xor, Xer, Xes, Xeg, Xof, and Xef are shown as one transistor, but the transistors Xos, Xog, Xor, Xer, Xes, Xeg, Xof, and Xef are shown as one transistor. Each may be formed of a plurality of transistors connected in parallel.

3, the drain of the transistor Xos is connected to a power supply Vs for supplying the high level voltage Vs of the sustain discharge pulse, and the source of the transistor Xos and the drain of the transistor Xog are Xodd electrodes. Is connected to. The drain of the transistor Xes is connected to the power supply Vs, and the source of the transistor Xes and the drain of the transistor Xeg are connected to the Xeven electrode. The source of the transistor Xog and the source of the transistor Xeg are connected to the ground terminal for supplying the low level voltage of the sustain discharge pulse, that is, the ground voltage (0V).

The power recovery capacitor Ce is charged with a voltage between the high level voltage and the low level voltage of the sustain discharge pulse, that is, the voltage Vs / 2 corresponding to half. A drain of the transistor Xor and a drain of the transistor Xer are connected to the first end of the power recovery capacitor Cer, and a diode Dor is connected to a source of the transistor Xor and a source of the transistor Xer, respectively. ) Is connected to the anode of the diode (Der). A source of the transistor Xof and a source of the transistor Xef are connected to the first end of the power recovery capacitor Ce, and the cathode of the diode Dof is respectively connected to the drain of the transistor Xof and the drain of the transistor Xef. And the cathode of the diode Def are connected. A cathode of the diode Dor and an anode of the diode Dof are connected to each other, and an inductor L1 is connected between the contact point and the Xodd electrode. The cathode of the diode Der and the anode of the diode Def are connected to each other, and an inductor L2 is connected between the contact point and the Xeven electrode.

Next, a method of generating a sustain discharge pulse as shown in FIG. 2A through the sustain discharge circuit 410 of FIG. 3 will be described in detail with reference to FIGS. 4 and 5.

4 is a signal timing diagram for generating a sustain discharge pulse as shown in FIG. 2A through the sustain discharge circuit 410 according to an embodiment of the present invention, and FIG. 5 is a view illustrating a signal timing of FIG. 3 according to the signal timing of FIG. 4. It is a figure showing the operation of the sustain discharge circuit 410.

First, it is assumed that a voltage of 0 V is applied to the Xodd electrode and the Xeven electrode before the mode 1 (M1). Here, the 0V voltage may be applied to the Xodd electrode and the Xeven electrode by turning on the transistors Xog and Xeg.

4 and 5, in the mode 1 M1, the transistors Xor and Xer are turned on. The turn-on of the transistor Xor causes resonance to occur in the path of the power recovery capacitor Ce, the transistor Xor, the diode Dor, the inductor L1, and the Xodd electrode (see 1) in FIG. 5). Due to this resonance, the voltage Vx_odd of the Xodd electrode rises from the 0V voltage to the Vs voltage. The turn-on of the transistor Xer causes resonance to occur in the path of the power recovery capacitor Cer, the transistor Xer, the diode Der, the inductor L2, and the Xeven electrode (see ② path in FIG. 5). . Due to this resonance, the voltage Vx_even of the Xeven electrode also rises from the 0V voltage to the Vs voltage.

In mode 2 M2, the transistors Xos and Xes are turned on. By the turn-on of the transistor Xos, the voltage Vs is applied to the Xodd electrode through the path of the power supply Vs, the transistor Xos, and the Xodd electrode (see the path 3 in FIG. 5). Then, by turning on the transistor Xes, the voltage Vs is applied to the Xeven electrode through the path of the power supply Vs, the transistor Xes, and the Xeven electrode (see ④ path in FIG. 5).

In mode 3 M3, the transistors Xof and Xef are turned on. The turn-on of the transistor Xof causes resonance to occur in the paths (see? Path in Fig. 5) of the Xodd electrode, the inductor L1, the diode Dof, the transistor Xof, and the power recovery capacitor Ce. Due to this resonance, the voltage Vx_odd of the Xodd electrode drops from the Vs voltage to the 0V voltage. The turn-on of the transistor Xef causes resonance to occur in the path of the Xeven electrode, the inductor L2, the diode Def, the transistor Xef, and the power recovery capacitor Cer (see ⑥ path in FIG. 5). . By this resonance, the voltage Vx_even of the Xeven electrode also drops from the Vs voltage to the 0V voltage.

In mode 4 M4, the transistors Xog and Xeg are turned on. By the turn-on of the transistor Xog, a 0V voltage is applied to the Xodd electrode via the paths of the Xodd electrode, the transistor Xog, and the ground terminal (see the path 7) in FIG. 5. By the turn-on of the transistor Xeg, a 0V voltage is applied to the Xeven electrode through the path of the Xeven electrode, the transistor Xeg, and the ground terminal (see the path of 8 in FIG. 5).

In this manner, Mode 1 to Mode 4 (M1 to M4) are repeated as many times as the weight of the corresponding subfield during the sustain period, and the sustain discharge pulses applied to the Xodd electrode and the Xeven electrode are in phase with each other (that is, a phase of 0 degrees). )

A method of generating a sustain discharge pulse as shown in FIG. 2B through the sustain discharge circuit 410 of FIG. 3 will be described in detail with reference to FIGS. 6 and 7.

FIG. 6 is a signal timing diagram for generating a sustain discharge pulse as shown in FIG. 2B through the sustain discharge circuit 410 according to an exemplary embodiment of the present invention. FIG. 7 is a signal timing diagram of FIG. 3 according to the signal timing of FIG. 6. It is a figure showing the operation of the sustain discharge circuit 410.

First, it is assumed that a voltage of 0 V is applied to the Xodd electrode and the Xeven electrode before the mode 1 (M1). Here, the 0V voltage may be applied to the Xodd electrode and the Xeven electrode by turning on the transistors Xog and Xeg.

In mode 1 M1 ', the transistors Xor and Xeg are turned on. The turn-on of the transistor Xor causes resonance to occur in the path of the power recovery capacitor Ce, the transistor Xor, the diode Dor, the inductor L1, and the Xodd electrode (see 1 'path in FIG. 7). . Then, the voltage Vx_odd of the Xodd electrode rises from the voltage of 0V to the voltage of Vs. By the turn-on of the transistor Xeg, a 0V voltage is applied to the Xeven electrode through the path of the Xeven electrode, the transistor Xeg, and the ground terminal (see the path '' in FIG. 7).

In mode 2 M2 ', the transistors Xos and Xeg are turned on. By the turn-on of the transistor Xos, the voltage Vs is applied to the Xodd electrode through the path of the power supply Vs, the transistor Xos, and the Xodd electrode (see the path of? 'In FIG. 7). By the turn-on of the transistor Xeg, a 0V voltage is applied to the Xeven electrode through the path of the Xeven electrode, the transistor Xeg, and the ground terminal (see the path '' in FIG. 7).

In mode 3 M3 ', the transistors Xos and Xer are turned on. By the turn-on of the transistor Xos, the voltage Vs is applied to the Xodd electrode through the path of the power supply Vs, the transistor Xos, and the Xodd electrode (see the path of? 'In FIG. 7). The turn-on of the transistor Xer causes resonance to occur in the path of the power recovery capacitor Ce, the transistor Xer, the diode Der, the inductor L2, and the Xeven electrode (see ④ 'path in FIG. 7). do. Due to this resonance, the voltage Vx_even of the Xeven electrode rises from the 0V voltage to the Vs voltage.

In mode 4 M4 ', the transistors Xof and Xes are turned on. The turn-on of the transistor Xof causes resonance to occur in the paths of the Xodd electrode, the inductor L1, the diode Dof, the transistor Xof, and the power recovery capacitor Ce (see ⑤ 'in FIG. 7). do. By this resonance, the voltage Vx_odd of the Xodd electrode drops from the Vs voltage to the 0V voltage. Then, by turning on the transistor Xes, the voltage Vs is applied to the Xodd electrode through the path of the power source Vs, the transistor Xes, and the Xeven electrode (see the path of 6 'in FIG. 7).

In mode 5 M5 ', the transistors Xog and Xes are turned on. By the turn-on of the transistor Xog, a 0V voltage is applied to the Xodd electrode through the path of the Xodd electrode, the transistor Xog, and the ground terminal (see the path of 7 'in FIG. 7). By the turn-on of the transistor Xes, the voltage Vs is applied to the Xodd electrode through the path of the power supply Vs, the transistor Xes, and the Xeven electrode (see the path of 6 'in FIG. 7).

In mode 6 (M6 '), transistors Xog and Xef are turned on. By the turn-on of the transistor Xog, a 0V voltage is applied to the Xodd electrode through the path of the Xodd electrode, the transistor Xog, and the ground terminal (see the path of 7 'in FIG. 7). The turn-on of the transistor Xef causes resonance to occur in the paths of the Xeven electrode, the inductor L2, the diode Def, the transistor Xef, and the capacitor Ce. By this resonance, the voltage Vx_even of the Xeven electrode drops from the Vs voltage to the 0V voltage.

In mode 7 M7 ', the transistors Xog and Xeg are turned on. By the turn-on of the transistor Xog, a 0V voltage is applied to the Xodd electrode through the path of the Xodd electrode, the transistor Xog, and the ground terminal. Then, by turning on the transistor Xeg, a 0V voltage is applied to the Xeven electrode through the path of the Xeven electrode, the transistor Xeg, and the ground terminal.

In this manner, Mode 1 to Mode 7 (M1 'to M7') are repeated as many times as the weight of the corresponding subfield during the sustain period, and the sustain discharge pulses applied to the Xodd electrode and the Xeven electrode are between 0 degrees and 180 degrees. Has a phase of.

A method of generating a sustain discharge pulse as shown in FIG. 2C through the sustain discharge circuit 410 of FIG. 3 will be described in detail with reference to FIGS. 8 and 9.

8 is a signal timing diagram for generating a sustain discharge pulse as shown in FIG. 2C through the sustain discharge circuit 410 according to an embodiment of the present invention, and FIG. It is a figure showing the operation of the sustain discharge circuit 410.

First, it is assumed that a voltage of 0 V is applied to the Xodd electrode and a voltage of Vs is applied to the Xeven electrode before the mode 1 (M1 ″). Here, the 0V voltage may be applied to the Xodd electrode and the Vs voltage may be applied to the Xeven electrode by turning on the transistors Xog and Xes.

In mode 1 M1 ″, transistors Xor and Xef are turned on. By turning on the transistors Xor and Xef, the paths of the Xeven electrode, the inductor L2, the diode Def, the transistor Xef, the transistor Xor, the diode Dor, the inductor L1 and the Xodd electrode are shown (Fig. Resonance occurs at ① '' path in 9). Due to this resonance, the energy charged in the Xeven electrode is recovered to the Xodd electrode through the inductors L1 and L2, so that the voltage Vx_odd of the Xodd electrode rises from 0 V to the Vs voltage and the voltage of the Xeven electrode Vx_even is Vs. Voltage drops to 0V and voltage. In other words, the energy charged in the Xeven electrode is recovered to the Xodd electrode.

In mode 2 M2 ", the transistors Xos and Xeg are turned on. By the turn-on of the transistor Xos, the voltage Vs is applied to the Xodd electrode via the path of the power supply Vs, the transistor Xos, and the Xodd electrode (see the path of? '' In FIG. 9). When the transistor Xeg is turned on, a 0 V voltage is applied to the Xeven electrode through the path of the Xeven electrode, the transistor Xeg, and the ground terminal (see path `` 3 '' in FIG. 9).

In mode 3 (M3 "), the transistors Xof and Xer are turned on. By turning on the transistors Xof and Xer, the paths of the Xodd electrode, the inductor L1, the diode Dof, the transistor Xof, the transistor Xer, the diode Der, the inductor L2 and the Xeven electrode (Fig. Resonance occurs at ④ '' path of 9). Due to this resonance, the energy charged in the Xodd electrode is recovered to the Xeven electrode through the inductors L1 and L2, so that the voltage Vx_odd of the Xodd electrode drops from the Vs voltage to the 0V voltage and the voltage of the Xeven electrode Vx_even is 0V. Rise from voltage to Vs voltage. In other words, the energy charged in the Xodd electrode is recovered to the Xeven electrode.

In mode 4 (M4 "), the transistors Xog and Xes are turned on. By the turn-on of the transistor Xog, a 0V voltage is applied to the Xodd electrode through the paths of the Xodd electrode, the transistor Xog, and the ground terminal (see the 6 'path in FIG. 9). Then, by turning on the transistor Xes, the voltage Vs is applied to the Xeven electrode through the path of the power supply Vs, the transistor Xes, and the Xeven electrode (see '' path in FIG. 9).

As described above, the mode 1 to the mode 4 (M1 '' to M4 '') are repeated as many times as the weight of the subfield during the sustain period, and the sustain discharge pulses applied to the Xodd electrode and the Xeven electrode are 180 degrees out of phase with each other. That is, the opposite phase).

Meanwhile, in the embodiment of the present invention described above, the plurality of sustain electrodes X1 to Xn are divided into Xodd electrodes and Xeven electrodes, and a sustain discharge circuit is disposed between the Xodd electrodes and the Xeven electrodes to sustain sustain discharges at the Xodd electrodes and the Xeven electrodes, respectively. Although the application of the pulse has been described, the sustain discharge circuit according to the embodiment of the present invention described above is divided into a plurality of groups in which the plurality of sustain electrodes X1 to Xn each include at least one sustain electrode. May be located.

As described above, the sustain discharge pulses applied to the Xodd electrode and the Xeven electrode through the sustain discharge circuit 410 according to the embodiment of the present invention may have various phases. As a result, a sustain discharge pulse having various phases can be set through one sustain discharge circuit from a designer's point of view.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the exemplary embodiment of the present invention, sustain discharge pulses having various phase differences may be generated through one sustain discharge circuit.

Claims (15)

A plurality of first electrodes; A first inductor having a first end electrically connected to a first electrode of a first group among the plurality of first electrodes; A second inductor having a first end electrically connected to a first electrode of a second group of the plurality of first electrodes; A capacitor charging a voltage between the high level voltage and the low level voltage of the sustain discharge pulse; A first path for setting a path from the capacitor to a second end of the first inductor; A second path that establishes a path from the second end of the first inductor to the capacitor; A third path routing from the capacitor to the second end of the second inductor; And And a fourth path configured to set a path from the second end of the second inductor to the capacitor. The method of claim 1, A first transistor electrically connected between a first power supply for supplying the high level voltage and a first electrode of the first group; A second transistor electrically connected between the first electrode of the first group and a second power supply for supplying the low level voltage; A third transistor electrically connected between the first power supply and the first electrode of the second group; And And a fourth transistor electrically connected between the first electrode of the second group and the second power source. The method of claim 2, In the first path, an anode is electrically connected to a fifth transistor in which a first end is electrically connected to the capacitor, and an anode is electrically connected to a second end of the fifth transistor, and a cathode is electrically connected to a second end of the first inductor. A first diode, wherein The second path includes a second diode having an anode electrically connected to a second end of the first inductor, and a sixth transistor electrically connected between a cathode of the second diode and the capacitor, In the third path, an anode is electrically connected to a seventh transistor having a first end electrically connected to the capacitor, and an anode is electrically connected to a second end of the seventh transistor, and a cathode is electrically connected to a second end of the second inductor. Including a third diode, The fourth path may include a fourth diode having an anode electrically connected to a second end of the second inductor, and an eighth transistor electrically connected between a cathode of the fourth diode and the capacitor. . The method of claim 3, The fifth transistor and the seventh transistor are turned on during a first period, the first transistor and the third transistor are turned on during a second period, the sixth transistor and And a controller configured to set the eighth transistor to a turn on state and to set the second transistor and the fourth transistor to a turn on state for a fourth period. The method of claim 3, The fourth transistor and the fifth transistor are turned on for a first period, the first transistor and the fourth transistor are turned on for a second period, and the first transistor and the third transistor are turned on for a third period. Setting a seventh transistor in a turn on state, setting the third transistor and the sixth transistor in a turn on state for a fourth period, setting the second transistor and the third transistor in a turn on state for a fifth period, And a controller configured to set the second transistor and the eighth transistor to a turned on state for a sixth period, and to turn the second transistor and the fourth transistor to a turned on state for a seventh period. The method of claim 3, The fifth transistor and the eighth transistor are turned on in a first period, the first transistor and the fourth transistor are turned on in a second period, and the sixth transistor and the third transistor are in a third period. And a controller configured to set the seventh transistor to the on state and to set the second transistor and the third transistor to the on state for a fourth period. The method according to any one of claims 1 to 6, The first electrode of the first group is an odd-numbered first electrode of the plurality of first electrodes, and the first electrode of the second group is an even-numbered first electrode of the plurality of first electrodes. In the method of driving a plasma display device including a plurality of first electrodes to which a sustain discharge pulse is applied, During a first period, applying a first voltage to a first electrode of a first group of the plurality of first electrodes and applying the first voltage to a first electrode of a second group of the plurality of first electrodes ; During a second period of time a capacitor is charging a second voltage higher than the first voltage, a first inductor electrically connected between the capacitor and the first electrode of the first group and the first electrode of the first group Forming a first resonance path to raise a voltage of the first electrode of the first group to a third voltage higher than the second voltage; During the second period, a second resonance path is formed by the capacitor, a second inductor electrically connected between the capacitor and the first electrode of the second group, and the first electrode of the second group, thereby forming the second resonance path. Raising the voltage of the first group of electrodes to a fourth voltage higher than the second voltage; During a third period of time, applying a fifth voltage higher than the second voltage to voltages of the first electrode of the first group and the first electrode of the second group; During a fourth period, a third resonant path is formed by the first electrode, the first inductor, and the capacitor of the first group, such that the voltage of the first electrode of the first group is lower than the second voltage. Descending to; And During the fourth period, a fourth resonant path is formed by the first electrode, the second inductor, and the capacitor of the second group, so that the voltage of the first electrode of the second group is lower than the second voltage. And driving the voltage down to a voltage. The method of claim 8, The plasma display apparatus further includes a plurality of second electrodes configured to perform a sustain discharge operation together with the plurality of first electrodes. And applying the first voltage to the plurality of second electrodes in the second to fourth periods. The method according to claim 8 or 9, And the third voltage and the fourth voltage are the same voltage, and the sixth voltage and the seventh voltage are the same voltage. The method of claim 10, And the first voltage is a low level voltage of the sustain discharge pulse, and the fifth voltage is a high level voltage of the sustain discharge pulse. In the method of driving a plasma display device including a plurality of first electrodes to which a sustain discharge pulse is applied, Applying the first voltage to a first electrode of a second group of the plurality of first electrodes while a first voltage is applied to a first electrode of a first group of the plurality of first electrodes; A capacitor charged with a second voltage higher than the first voltage in a state where the first voltage is applied to the first electrode of the second group, and electrically connected between the capacitor and the first electrode of the first group Forming a first resonant path with the first inductor and the first electrode of the first group to raise the voltage of the first group of electrodes to a third voltage higher than the second voltage; A second inductor electrically connected between the capacitor, the capacitor, and the first electrode of the second group in a state where a fourth voltage higher than the second voltage is applied to the first electrode of the first group; Forming a second resonance path with a first electrode of a second group to raise the voltage of the first electrode of the second group to a fifth voltage higher than the second voltage; In the state where the fourth voltage is applied to the first electrode of the second group, a third resonance path is formed by the first electrode, the first inductor, and the capacitor of the first group, thereby forming the first group of the first group. Lowering the voltage of the first electrode to a sixth voltage lower than the second voltage; And In the state where the first voltage is applied to the first electrode of the first group, a fourth resonance path is formed by the first electrode, the second inductor, and the capacitor of the second group, thereby forming the first group of the second group. And driving the voltage of the first electrode to a seventh voltage lower than the second voltage. The method of claim 12, And the third voltage is the same voltage as the fifth voltage, and the sixth voltage is the same voltage as the seventh voltage. The method according to claim 12 or 13, And the first voltage is a low level voltage of the sustain discharge pulse, and the fourth voltage is a high level voltage of the sustain discharge pulse. The method according to claim 8 or 12, wherein The first electrode of the first group is an odd-numbered first electrode of the plurality of first electrodes, and the first electrode of the second group is an even-numbered first electrode of the plurality of first electrodes. Way.

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