KR20080032980A - Method for manufacturing semiconductor device having bulb-type recessed channel - Google Patents

Abstract

A method for manufacturing a semiconductor device having a bulb type recessed channel is provided to reduce the amount of impurities discharged to the outside by using a buffer layer. A first trench(210) is formed in a semiconductor substrate(200). A first implantation process is performed to implant B18H22 by applying damage to a surface of silicon within a semiconductor substrate of a lower part of the first trench, to increase an etch speed. A second implantation process is performed to implant B18H22 by applying the damage to the surface of the silicon within the semiconductor substrate of both sides of the first trench, to increase the etch speed. A barrier layer is formed on a sidewall of the first trench. A second trench(220) is formed at a lower end of the first trench so that a bulb type recess channel trench(222) is formed by using the first and second trenches. A gate stack(232) is overlapped on the bulb type recess channel trench.

Description

Method for manufacturing semiconductor device having bulb type recess channel {Method for manufacturing semiconductor device having bulb-type recessed channel}

1 is a diagram illustrating a semiconductor device having a bulb type recess channel according to the related art.

2 to 9 are views illustrating a method of manufacturing a semiconductor device having a bulb channel recess channel according to an embodiment of the present invention.

10 and 11 illustrate a method of manufacturing a semiconductor device having a bulb type recess channel according to another exemplary embodiment of the present invention.

The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a bulb type recess channel.

Recently, as the degree of integration of integrated circuit semiconductor devices has increased and design rules have sharply decreased, it is increasingly difficult to secure stable operation of transistors. Therefore, various methods for securing channel lengths without increasing design rules have been studied. In particular, the structure extends the channel length for a limited gate line width. By using a two-step etching process, a semiconductor device having a bulb-type recess channel is formed to extend the channel length. Attempts are being made.

1 illustrates a semiconductor device having a bulb channel recess channel according to the related art.

Referring to FIG. 1, in a semiconductor device having a conventional bulb type recess channel, an active region and an isolation region are divided by an isolation layer 102 formed on the semiconductor substrate 100. Next, a bulb type trench channel trench 103 having a bottom surface having a bulb shape is formed on the active region of the semiconductor substrate 100. Next, a gate stack 112 including a gate insulating film 104 is formed to overlap the trench type trench channel 103. The gate stack 112 may include a gate conductive layer 106, a metal layer 108, and a hard mask layer 110. Junction regions 116 into which impurities are implanted are formed on the semiconductor substrate 100 on both sides of the gate stack 112, and spacer layers (not shown) are disposed on the side surfaces of the gate stack 112.

As described above, in the semiconductor device in which the bulb type trench channel trench 103 is formed, the channel 114 is formed along the trench 103 so that the effective channel length is longer than that of the semiconductor device having a conventional planar channel. do. As the effective channel length increases, the cell threshold voltage increases accordingly. When the cell threshold voltage increases, the planar channel improves the refresh characteristics by reducing the amount of electric field, reducing junction leakage current and gate induced drain leakage (GIDL). It can be increased as compared with the semiconductor device having a.

However, as the size of the semiconductor device becomes smaller, a method for further increasing the channel length formed along the trench is required to improve refresh characteristics.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device having a bulb type recess channel capable of improving refresh characteristics of the device by increasing the length of a sphere at a lower end portion of the recess channel.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device having a bulb type recess channel according to the present invention, forming a first trench in the semiconductor substrate; Performing a first ion implantation process of injecting octadecaborane (B ₁₈ H ₂₂ ) to increase the etching rate by damaging the silicon surface of the semiconductor substrate under the first trench; Performing a second ion implantation process of injecting octadecarborane (B ₁₈ H ₂₂ ) to damage the silicon surface of the semiconductor substrate on both sides of the first trench to increase the etching rate; Forming a barrier layer on the sidewalls of the first trenches; Forming a spherical second trench at a lower end of the first trench to form a bulb type trench channel trench formed by the first trench and the second trench; And forming a gate stack overlapping the bulb type trench channel trench.

In the present invention, the first ion implantation process and the second ion implantation process is preferably performed in a single type of ion implantation equipment.

The first ion implantation process is carried out in the vertical direction, the second ion implantation process has a tilt angle of 4-30 °, the same conditions as the primary second ion implantation process having a rotation angle of 0-360 ° It is preferable to include a secondary secondary ion implantation process performed by rotating the first secondary ion implantation process by 180 °.

The barrier layer may include an oxide layer.

The forming of the barrier layer may include forming a buffer layer on an entire surface of the semiconductor substrate after the second ion implantation process; And selectively removing a buffer layer on a portion of the top, bottom and side surfaces of the first trench.

In the forming of the barrier layer, a buffer layer may be formed before the first ion implantation process, the second ion implantation process may be performed, and then a buffer layer may be formed on a portion of the top, bottom, and side surfaces of the first trench. May optionally include removing.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

2 to 9 are diagrams for explaining a method of manufacturing a semiconductor device having a bulb type recess channel according to an embodiment of the present invention.

Referring to FIG. 2, a buffer film 204 is deposited on the semiconductor substrate 200 in which an active region is set by the device isolation film 202. Next, the first hard mask film 206 and the second hard mask film 207 are sequentially deposited on the buffer film 204. The hard mask layers 206 and 207 serve as ion implantation barrier layers in a subsequent ion implantation process. In addition, it serves as a mask in the etching process to proceed to form a bulb type recess channel. The buffer film 204 may be formed of an oxide film. In this case, the primary hard mask film 206 may include a polysilicon film or a nitride film, and the secondary hard mask film 207 may include an amorphous carbon film.

 Subsequently, a photosensitive film is applied and patterned on the secondary hard mask film 207 to form a photosensitive film pattern 208 exposing a predetermined region of the secondary hard mask film 207. In this case, the photoresist pattern 208 may include an anti-reflection film (not shown).

Referring to FIG. 3, the first and second hard mask layers 206 and 207 and the buffer layer 204 are etched using the photoresist pattern 208 as a mask to selectively expose the semiconductor substrate 200. 204 '), the primary hard mask film pattern 206' and the secondary hard mask film pattern 207 'are formed. The exposed region of the semiconductor substrate 200 is a region where a bulb type recess channel trench is to be formed.

Referring to FIG. 4, a semiconductor substrate having the photoresist pattern 208, the second hard mask layer pattern 206 ′, the first hard mask layer pattern 207 ′, and the buffer layer pattern 204 ′ exposed as an etching mask ( The active region of the layer 200 is etched to form the first trench 210. Here, the first trench 210 corresponds to a neck portion of a bulb type recess channel. The first trench 210 may be formed to an appropriate depth in consideration of the size of the bulb to be formed later. The photoresist pattern 208 is then removed using a strip process. In this case, the second hard mask layer pattern 206 ′ is removed together in the process of removing the photoresist layer pattern 208. Afterwards, the cleaning process is performed to remove foreign substances on the semiconductor substrate 200 generated in the etching process.

Referring to FIG. 5, the first hard mask layer pattern 206 ′ that is not removed in the etching process of forming the first trench 210 is used as an ion implantation buffer layer to inject impurities for channel formation. An ion implantation process (a) is performed. In the first ion implantation process (a), the tilt angle is set to 0 ° in the lower portion of the first trench 210 and impurities are injected at a high dose in the vertical direction. The impurity is octadecarbonane (B ₁₈ H ₂₂ ) having a large mass in order to increase the etching rate by applying damage to the silicon lattice in the semiconductor substrate 200 under the first trench 210. May be implanted with B ₁₈ H + ions used as the source material. Then, a first ion implantation layer 212 is formed in the semiconductor substrate 200 at the lower end of the first trench 210. Here, the first ion implantation layer 212 may be implanted by adjusting ion implantation energy so as to be positioned below the trench for trench type recess channel to be formed later. In this case, when octadecaborane (B ₁₈ H ₂₂ ) is used as a source material, since the ion implantation is performed in a molecular form, excessive damage to the silicon lattice can be reduced.

Referring to FIG. 6, a first ion implantation layer 214 is formed in the semiconductor substrate 200 on one side of the first trench 210 using the first hard mask layer pattern 206 ′ as an ion implantation buffer layer. The second ion implantation step (b) is performed. The primary second ion implantation process (b) has an angle of 4-30 ° and injects impurities at a low dose.

Subsequently, a second secondary ion implantation step (c) of forming the third ion implantation layer 216 in the semiconductor substrate 200 on the other side of the first trench 210 is performed. The secondary second ion implantation step (c) is performed by rotating the device 180 ° under the same conditions as the primary second ion implantation step (b) and the tilt angle is 4-30 °. In this case, impurities implanted in the first and second ion implantation processes (b) and the second and second ion implantation processes (c) may damage the silicon surface of the semiconductor substrate 200 under the first trenches 210. In order to increase the etch rate, a large mass of octadecaborane (B ₁₈ H ₂₂ ) may be injected including B ₁₈ H + ions using the source material. In this case, the first to second ion implantation process (a, b, c) may be performed using a single-type ion implantation equipment (or single sheet type equipment).

In the process of forming the first to third ion implantation layers 212, 214, and 216, when B ₁₈ H + ions are injected using octadecaborane (B ₁₈ H ₂₂ ) as a source material, a conventional ion implantation layer is formed. Since the mass of B ₁₈ H + ions is about 18 times lower than the 11B + ions that are injected for harm, it can inflict more damage to the silicon surface. If the silicon surface is damaged in this way, a later increase in the length of the sphere (sphere) in the etching process for forming a bulb type trench channel trench can improve the refresh characteristics.

Referring to FIG. 7, a barrier layer 218 is formed on sidewalls of the first trench 210.

Specifically, an oxide film is formed on the entire surface of the semiconductor substrate 200. Next, an oxide film of the upper portion, the bottom surface of the first trench 210 and a portion of the trench sidewalls is selectively etched to form a barrier layer 218. Then, the silicon layer Si of the bottom surface of the first trench 210 and a part of the trench sidewall is exposed.

Referring to FIG. 8, a spherical second trench 220 is formed on the lower end of the first trench 210 using the first hard mask layer pattern 206 ′ and the barrier layer 218 as an etch mask. As a result, a bulb type trench channel trench 222 including the first trench 210 and the spherical second trench 220 is formed. Here, the spherical second trench 222 may be etched from the bottom surface of the first trench 114. The etching process of forming the spherical second trench 220 may be etched at the same speed in all directions to proceed to isotropic etching having a curved surface after etching.

In this case, the barrier layer 218 may prevent damage to the semiconductor substrate 200, which may occur due to excessive etching of the side surface of the trench channel trench 222 of the bulb type during isotropic etching. Next, the primary hard mask film pattern 206 'and the barrier film 218 are removed.

Referring to FIG. 9, a gate oxide layer 224 is formed as a dielectric layer on the exposed bulb channel trench 222. In this case, the gate oxide layer 224 is formed on the bulb type trench channel trench 222, thereby reducing the amount of impurities diffused outward.

Next, a gate stack 232 is formed on the gate oxide film 224. In detail, the gate electrode 226, the metal film 228, and the gate hard mask film 230 are sequentially deposited on the gate oxide film 224. Next, a selective etching process for gate patterning is performed to form the gate stack 232.

On the other hand, when B ₁₈ H + ions using a large mass of impurities, for example, octadecaborane (B ₁₈ H ₂₂ ) as a source material, damage may be excessively generated on the silicon lattice in the semiconductor substrate. Accordingly, a method of reducing such damage will be described with reference to FIGS. 10 and 11.

First, as shown in FIGS. 2 to 4, the first trenches 210 are formed in the semiconductor substrate 200. Briefly, the mask layer pattern for selectively exposing the active region of the semiconductor substrate 200 is formed. Next, an etching process using a hard mask layer pattern is performed to form the first trenches 210 in the semiconductor substrate 200. Here, the first trench 210 corresponds to a neck portion of a trench for trench channel recess channels to be formed later.

Next, referring to FIG. 10, a spacer layer 234 is deposited on the entire surface of the semiconductor substrate 200 including the first trenches 210. The spacer layer 234 may be deposited as an oxide layer using a high thermal oxide (HTO) or chemical vapor deposition (CVD) method.

Referring to FIG. 11, a first ion implantation process (a) and a second ion implantation process (b, c) are performed using the spacer layer 234 as an ion implantation buffer layer to form the semiconductor substrate 200 below the first trench 210. ), A first ion implantation layer 212, a second ion implantation layer 214, and a third ion implantation layer 216 are formed.

Specifically, in the first ion implantation process (a), the tilt angle is set to 0 ° under the first trench 210 and impurities are injected at a high dose in the vertical direction. Then, a first ion implantation layer 212 is formed in the semiconductor substrate 200 at the lower end of the first trench 210. Here, the first ion implantation layer 212 may be implanted by adjusting ion implantation energy so as to be positioned below the trench for trench type recess channel to be formed.

Next, the second ion implantation process (b, c) includes a first second ion implantation process (b) for forming the second ion implantation layer 214 in the semiconductor substrate 200 on one side of the first trench 210 and A second second ion implantation process (c) is performed to form a third ion implantation layer 216 in the semiconductor substrate 200 on the other side of the first trench 210. The primary second ion implantation process has an angle of 4-30 °, and impurities are implanted at a low dose, and the secondary second ion implantation process (c) is the first secondary ion implantation process. (b) and the tilt angle is carried out by rotating 180 ° in the same conditions to 4-30 °.

The impurities of the first and second ion implantation processes (a, b, and c) may be subjected to damage to the silicon lattice in the semiconductor substrate 200 under the first trench 210 to increase the etch rate. Hazardous mass octadecaborane (B ₁₈ H ₂₂ ) can be injected including B ₁₈ H + ions using the source material.

In this case, the spacer film 234 formed on the first trench 210 may be formed in the first and second ion implantation processes (a, b, and c) using octadecaborane (B ₁₈ H ₂₂ ) having a large mass as a source material. Excessive damage on the silicon lattice in the semiconductor substrate 200 may be alleviated. In addition, since octadecaborane (B ₁₈ H ₂₂ ) is ion-implanted in a molecular form, excessive damage to the silicon lattice can be reduced. In addition, as the gate oxide film is formed on the trench type trench channel trench to be formed later, the amount of impurities that are out diffused can be reduced.

Next, the spacer layer 234 on the top, bottom and sidewalls of the first trench 210 is selectively etched to form a barrier layer 218 as shown in FIG. 7. Then, the process proceeds in the same manner as in FIGS.

As such, the ion-injection process is performed using octadecaborane (B ₁₈ H ₂₂ ) having a large mass as a source material, thereby increasing the etching rate of the damaged portion in the process of forming a trench for the trench-type recess channel. As a result, the length of the second trench 220 having a spherical shape may be increased. As the length of the bulb type trench channel trench increases, the refresh characteristic can be improved.

As described so far, according to the method for manufacturing a semiconductor device having a bulb type recess channel according to the present invention, a bulb type recess is used by using a large mass of ions to damage the silicon surface during the channel ion implantation process. In the process of forming the trench for the channel, the etching speed of the damaged portion may be increased, thereby increasing the length of the spherical trench. As the length of the bulb type recess channel trench increases, the refresh characteristic may be improved.

In addition, by forming the trench in the neck portion of the bulb-type recess channel trench, forming the buffer film, and then performing an ion implantation process, it is possible to prevent the silicon lattice from being excessively damaged by the buffer film. In addition, the amount of impurities flowing out by the buffer film can be reduced.

Claims (9)

Forming a first trench in the semiconductor substrate; Performing a first ion implantation process of injecting octadecaborane (B ₁₈ H ₂₂ ) to increase the etching rate by damaging the silicon surface of the semiconductor substrate under the first trench; Performing a second ion implantation process of injecting octadecarborane (B ₁₈ H ₂₂ ) to damage the silicon surface of the semiconductor substrate on both sides of the first trench to increase the etching rate; Forming a barrier layer on the sidewalls of the first trenches; Forming a spherical second trench at a lower end of the first trench to form a bulb type trench channel trench formed of the first trench and the second trench; And And forming a gate stack overlapping the trench for trenches of the bulb type recess channel. The method of claim 1, wherein forming the first trench comprises: Sequentially depositing a first hard mask film and a second hard mask film on the semiconductor substrate; Forming a first hard mask layer pattern and a second hard mask layer pattern exposing the semiconductor substrate; Etching the semiconductor substrate using the first and second hard mask layer patterns as a mask to form a first trench; And And removing the secondary hard mask layer pattern. The method of claim 1, The hard mask film pattern may include a polysilicon film, a nitride film, or an amorphous carbon film, wherein the semiconductor device has a bulb type recess channel. The method of claim 1, The first ion implantation process and the second ion implantation process is a semiconductor device manufacturing method having a bulb type recess channel, characterized in that performed in a single type of ion implantation equipment. The method of claim 1, The first ion implantation process is a semiconductor device manufacturing method having a bulb type recess channel, characterized in that performed in the vertical direction. The method of claim 1, The second ion implantation process has a tilt angle of 4-30 ° and is rotated 180 ° with the primary second ion implantation process under the same conditions as the primary second ion implantation process having a rotation angle of 0-360 °. A method of manufacturing a semiconductor device having a bulb type recess channel, comprising a secondary second ion implantation process performed by the method. The method of claim 1, And said barrier film comprises an oxide film. The method of claim 1, wherein the forming of the barrier layer comprises: Forming an oxide film on an entire surface of the semiconductor substrate after the second ion implantation process; And And removing an oxide layer on a portion of the first trench upper, bottom, and side surfaces of the first trench. The method of claim 1, wherein the forming of the barrier layer comprises: Forming an oxide film before performing the first ion implantation process, and removing the oxide film on a portion of the top, bottom and side surfaces of the first trench after performing the second ion implantation process. A method of manufacturing a semiconductor device having a bulb type recess channel.

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