KR20080030838A - Layout of wave type recess gate and method for fabricating recess gate using the same - Google Patents

Abstract

A layout of a waved recess gate and a method for fabricating a recess gate are provided to minimize passing gate effect by reducing an etching amount of a field oxide layer on a passing gate region and a dimension of a passing gate. A field oxide layer(22) for defining an active region(23) is formed on a semiconductor substrate. A hard mask is formed on the semiconductor substrate. A waved recess gate mask is formed on the hard mask to open the filed oxide layer wider than the active region. The hard mask is etched by using the waved recess gate mask as an etch barrier. The active region is etched by using the hard mask as an etch barrier to form recess gate patterns(26A,26B). A gate dielectric is formed on the recess gate patterns. A recess gate covering the recess gate patterns is formed on the gate dielectric. The recess gate mask is provided with a lined first open pattern formed on an upper of the active region, and a lined second open pattern extended in a coaxial direction from the first open pattern and formed on an upper of the field oxide layer. A width of the lined second open pattern is less than that of the first open pattern.

Description

LAYOUT OF WAVE TYPE RECESS GATE AND METHOD FOR FABRICATING RECESS GATE USING THE SAME

1 is a view showing the structure of a semiconductor device by a recess gate process according to the prior art.

2A and 2B are layout views for forming the recess gate pattern of FIG. 1.

3A to 3E are cross-sectional views illustrating a recess gate etching method of a semiconductor device in accordance with an embodiment of the present invention.

4A is a layout diagram of a state in which an active region is formed.

4B is a layout diagram of a recess gate mask.

4C is a layout diagram illustrating a state in which a recess gate pattern is formed.

5 is a detailed view of a recess gate mask.

6 is a detailed view of a recess gate pattern.

* Explanation of symbols for the main parts of the drawings

21 silicon substrate 22 field oxide film

23: active area 24: recess gate hard mask

25: recess gate mask 25A: first open pattern

25B: second open pattern 26A: first recess gate pattern

26B: second recess gate pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a wavy recess gate.

As the degree of integration of semiconductor devices increases, the channel length of the transistor is also very short. As the channel length becomes shorter, a conventional flat panel transistor has a problem in that a so-called short channel effect is increased, in which the threshold voltage of the transistor is drastically lowered.

In addition, in the DRAM as a memory device, as the degree of integration of the device increases, the electric field of the substrate becomes very high due to excessive ion implantation. In particular, the junction leakage current (Junction) at the junction of the storage node contact (SNC) side is increased. There is a fatal problem of increased leakage, which reduces data retention time.

One way to solve this problem is recently a recess gate process that forms a cell transistor of a DRAM after recessing silicon to a predetermined depth. As a result, the data leakage time can be increased by reducing the junction leakage current.

1 is a view illustrating a structure of a semiconductor device by a recess gate process according to the related art, and FIGS. 2A and 2B are layout views for forming a recess gate pattern of FIG. 1.

Referring to FIG. 1, after forming the field oxide layer 12 on the silicon substrate 11 to define the active region 11A, the silicon substrate 11 is selectively etched to form the recess gate pattern 13.

Subsequently, the gate oxide film 14 is formed, the polysilicon 15, the tungsten silicide 16, and the gate hard mask 17 are formed, and then gate patterning is performed to form a gate structure.

In the prior art of FIG. 1, the etching for forming the recess gate pattern 13 is called a recess gate etching, and a straight recess gate mask for forming the recess gate pattern 13 is formed. Use

Referring to FIG. 2A, a field oxide film 12 is formed on the silicon substrate 11 to define a plurality of active regions 11A.

Subsequently, referring to FIG. 2B, after the linear recess gate mask 13A is formed on the active region 11A, the recess gate etching using the recess gate mask is performed to form the linear recess gate pattern 13. ).

However, in the related art, since the recess gate pattern 13 is patterned using a straight type recess gate mask 13A, the linear recess gate pattern 13 is formed of the active region 11A or the field oxide film. Patterned in all of (12), there is a portion to be etched in the field oxide film 12 during the recess gate etching. At this time, a portion formed by etching the field oxide film 12 is referred to as a 'passing gate' (see 'P'), and a subsequent gate structure is also formed in the passing gate region.

An electric field is generated between the transistor operating under the influence of the passing gate P and the gate structure formed in the passing gate, thereby reducing the threshold voltage Vt. This is called a passing gate effect. do.

Due to the effect of the threshold voltage drop (Vt Drop) due to the pass-gate effect as described above, 'LtRAS' is degraded. In addition, since the breakdown voltage of the cell also varies according to the threshold voltage change, it is difficult to control this, which adversely affects device characteristics.

FIG. 2C is a cross-sectional view taken along the line A-A 'of FIG. 2B, and it can be seen that the etching process is performed on the field oxide layer 12 when the recess gate pattern 13 is formed to form the passing gate P. Referring to FIG.

The present invention has been proposed to solve the above problems of the prior art, the layout of the recess gate that can minimize the pass-gate effect by minimizing the amount of field oxide etching in the pass-gate region during the recess gate etching process and using the same It is an object of the present invention to provide a method for manufacturing a recess gate.

The layout of the recess gate of the present invention for achieving the above object comprises a plurality of active regions defined by the field oxide film; And a first line pattern formed on the active region and a second line pattern extending in the same axis direction from the first line pattern and formed on the field oxide layer and having a width smaller than that of the first line pattern. And gate lines of the first line pattern and the second line pattern in the plurality of gate lines, wherein the first line pattern and the second line pattern are straight line patterns, and one side surface of the first line pattern and one side surface of the second line pattern. Is connected without bending, and the other side surface of the first line pattern and the other side surface of the second line pattern are curved and connected to each other to form a wave. The first line pattern and the second line pattern of The connection point may be a point where the active area is changed to the field oxide layer, and the connection point between the first line pattern and the second line pattern is diagonally drawn. It features.

In addition, the method of manufacturing a recess gate of the present invention includes forming a field oxide film defining an active region on a semiconductor substrate; Forming a hard mask on the semiconductor substrate; Forming a wave type recess gate mask on the hard mask to open the field oxide layer more widely than the active region; Etching the hard mask using the recess gate mask as an etch barrier; Forming a recess gate pattern by etching the active region using the hard mask as an etch barrier; Forming a gate insulating film on the recess gate pattern; And forming a recess gate covering the recess gate pattern on the gate insulating layer, wherein the recess gate mask includes a line-type first open pattern formed over the active region and the first gate pattern; A first line pattern and a second line pattern formed on the field oxide layer and extending in the same axial direction from the first open pattern and having a width smaller than that of the first open pattern. The pattern is a straight line pattern, wherein one side of the first open pattern and one side of the second open pattern are connected without bending, and the other side of the first open pattern and the other side of the second open pattern are curved. Are connected to form a wave.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

In the following embodiment, a passivation gate influencing a transistor operating by using a recessed RG instead of a straight line that uses a recessed gate mask RG MASK when forming a recessed gate is used. This is to optimize device characteristics by minimizing the influence of (Passing Gate).

In order to minimize the effect of passing gates, the size of the recess gate pattern used for the recess gate pattern on the active region is applied. For the design, the minimum size is designed so that there is no big issue in patterning, minimizing the electric field of the passing gate during device operation. At this time, if a line pattern is applied at the point where the active region is changed to the field oxide film, there is a risk of short circuit, so this section is drawn diagonally to compensate for the short circuit.

3A to 3E are cross-sectional views illustrating a recess gate etching method of a semiconductor device according to an embodiment of the present invention, and FIGS. 4A to 4C are layout views.

Referring to FIG. 3A, a field oxide layer 22 is formed on a silicon substrate 21 using a shallow trench isolation (STI) process. An active region 23 is defined by the field oxide layer 22, and the active region 23 is an island pattern.

4A is a layout diagram of a state in which an active region 23 is formed.

As shown in FIG. 3B, a recess gate hard mask 24 is formed on the entire surface of the silicon substrate 21 in which the active region 23 is defined. In this case, the recess gate hard mask 24 is to secure a margin insufficient during the recess gate etching process using the photosensitive film, and at least one selected from an oxide film, an amorphous carbon layer, or polysilicon is used. For example, polysilicon is used alone, or a double structure of an oxide film and polysilicon is used, or a triple structure of an oxide film, an amorphous carbon film and a polysilicon is used.

Subsequently, a photoresist film is applied on the recess gate hard mask 24 and patterned by exposure and development to form the recess gate mask 25.

In this case, the open pattern of the recess gate mask 25 becomes a waved pattern because the first linear open pattern 25A and the second linear open pattern 25B are coupled to each other. .

In detail, the first open pattern 25A of the recess gate mask 25 may open the upper portion of the active region 23, and the second open pattern 25B may open the upper portion of the passing gate P region. Pattern. That is, the portion where the recess gate pattern is to be formed is opened by the first open pattern 25A, and the passing gate region is opened by the second open pattern 25B. Here, the widths of the first open pattern 25A and the second open pattern 25B are different from each other, but the width W2 of the second open pattern 25B is greater than the width W1 of the first open pattern 25A. Is defined smaller. Therefore, as the first open pattern 25A and the second open pattern 25B having different widths are combined, the recess gate mask 25 becomes a wave-shaped line pattern.

 Preferably, the width W1 of the first open pattern 25A among the open patterns of the recess gate mask 25 is the same as that of the conventional straight line pattern, and the width W2 of the second open pattern 25B is It is defined smaller than the width of the conventional straight line pattern. As described above, since the second open pattern 25B opened in the passing gate region is small, the second open pattern 25B does not overlap the edge of the adjacent active region of the passing gate region opened below. That is, the active region 23 and the passing gate are disconnected by the second open pattern 25B.

The width W1 of the first open pattern 25A is the width of the recess gate pattern designed in consideration of device characteristics, and the width W2 of the second open pattern 25B is the first open pattern 25A. Draw at 70% or less of the width W1. At this time, the width W1 of the first open pattern 25A is applied to the width considering the overlap margin (O / L Margin), and the width W2 of the second open pattern 25B is a large issue for patterning. Apply a width so that there is no. The width W2 of the second open pattern 25B is based on reducing the passing gate side by ΔW. However, the minimum width is 40% of the first open pattern width W1. That is, the width W2 of the second open pattern 25B is in the range of 40 to 70% of the width W1 of the first open pattern 25A.

The second open pattern 25B extends in the same axial direction from the first open pattern 25A, and the connection portion between the first open pattern 25A and the second open pattern 25B has a triangle shape. The third open pattern 25C is used. The first open pattern 25A is gradually reduced in width, and the second open pattern 25B is gradually increased in width. To do this, draw a diagonal form with a ratio of 1: 1 to form a triangle.

The reason for forming the triangle in this way is the point where the connecting portion of the first open pattern and the second open pattern changes from the active area to the field oxide layer, and if there is a sudden line width change at this point, there is a risk of short circuit. Because. Therefore, the connecting portion of the first open pattern 25A and the second open pattern 25B is drawn in a diagonal shape to compensate for disconnection.

FIG. 4B is a layout view of the recess gate mask, and FIG. 5 is a detailed view of the recess gate mask, and the triangular third open pattern 25C is formed at a connection portion between the first open pattern 25A and the second open pattern 25B. We can see that

In the recess gate mask 25, one side of the open pattern is straight without bending, and the other side has a line width different from each other to form a wave pattern. As a result, the sides facing each other between the adjacent open patterns are straight, and the remaining sides are different in width, so that the wave-shaped open patterns are arranged symmetrically with each other.

As described above, the shape of the open pattern is changed on both sides because the width of the portion overlapping the edge of the adjacent active region is reduced.

As described above, the open pattern of the recess gate mask is composed of the first open pattern 25A and the second open pattern 25B, and in particular, since the width of the second open pattern 25B in the passing gate region is small, During the recess gate etching process, the amount of etching of the field oxide layer in the passing gate region can be reduced.

Next, as illustrated in FIG. 3C, the recess gate hard mask 24 is etched using the recessed gate mask 25 having a wave structure, and as shown in FIG. 3D, the silicon substrate ( A recess gate etching process of etching 21 is performed to form recess gate patterns 26A and 26B. 4C is a layout diagram illustrating a state in which a recess gate pattern is formed, and FIG. 6 is a detailed view of the recess gate pattern.

In the recess gate etching process as described above, the recess gate hard mask pattern 24A is formed by the recess gate mask 25 to form the first open pattern 25A and the second open pattern 25B of the recess gate mask 25. Since the silicon substrate 21 is etched using the recess gate hard mask pattern 24A, the recess gate patterns 26A and 26B finally formed are line-shaped first recesses. It becomes a wave-shaped line pattern consisting of the gate pattern 26A and the second recess gate pattern 26B. The second recess gate pattern 26B extends in the same axial direction from the first recess gate pattern 26A, and the first recess gate pattern 26A and the second recess gate pattern 26B are formed. A triangular recessed gate pattern 26C exists at the connection portion of.

In particular, the second recess gate pattern 26B of the recess gate patterns 26A and 26B formed in the passing gate region does not contact the neighboring active regions 23, and the width of the field oxide layer 22 is small. The amount of etch is minimized. That is, the etching amount is reduced by the reference numeral 'R' than in the prior art.

As described above, when the width of the passing gate is reduced by minimizing the etching amount of the field oxide layer 22 by minimizing the second recess gate pattern 26B in the passing gate region, the electric field with the operating element is reduced.

Meanwhile, the recess gate mask 25 may be consumed and not remain in the recess gate etching process for forming the recess gate patterns 26A and 26B. In this case, the recess gate hard mask pattern 24A may be etched. Play a role.

As shown in FIG. 3E, the remaining recess gate hard mask pattern 24A is removed.

Thereafter, the gate oxide layer 27 is formed, the polysilicon 28, the tungsten silicide 29, and the gate hard mask 30 are formed, and then gate patterning is performed to form a gate structure.

In the above gate structure, the passing gate passing through the field oxide layer has a width of 'P2' whose width is smaller than that of the conventional width 'P1'. As such, reducing the width reduces the electric field with the operating element.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of reducing the electric field with the operating element by reducing the size of the passing gate by reducing the amount of field oxide etching in the passing gate region.

As a result, it is possible to prevent a decrease in yield due to LtRAS while improving the refresh characteristics.

Claims (19)

A plurality of active regions defined by field oxide films; And A plurality of first line patterns formed on the active region and second line patterns extending in the same axial direction from the first line pattern and formed on the field oxide layer and having a width smaller than that of the first line pattern; Gate line The layout of the recess gate comprising a. The method of claim 1, In the plurality of gate lines, The first line pattern and the second line pattern are straight line patterns, one side surface of the first line pattern and one side surface of the second line pattern are connected without bending, and the other side surface of the first line pattern and the first line pattern. The other side of the two-line pattern is a layout of the recess gate connected with a curved line to form a wave. The method of claim 2, In the plurality of gate lines, A layout of a recess gate in which a pair of neighboring gate lines are arranged in a symmetrical structure. The method of claim 3, The pair of gate lines of the symmetrical structure, A layout of a recess gate in which one side surfaces of the first and second line patterns connected without bending face each other. The method according to any one of claims 2 to 4, And a connection point between the first line pattern and the second line pattern is a point where the active area is changed to the field oxide layer. The method of claim 5, The connection point of the first line pattern and the second line pattern, Layout of recess gates drawing diagonally. The method of claim 6, The connection point of the first line pattern and the second line pattern, A layout of a recess gate having a predetermined area with a third pattern having a shape in which a line width decreases from an end of the other side surface of the first line pattern; The method of claim 7, wherein The third pattern is a layout of a recess gate having a triangular shape. The method according to any one of claims 1 to 4, And a width of the second line pattern is in the range of 40 to 70% of the width of the first line pattern. Forming a field oxide film defining an active region on the semiconductor substrate; Forming a hard mask on the semiconductor substrate; Forming a wave type recess gate mask on the hard mask to open the field oxide layer more widely than the active region; Etching the hard mask using the recess gate mask as an etch barrier; Forming a recess gate pattern by etching the active region using the hard mask as an etch barrier; Forming a gate insulating film on the recess gate pattern; And Forming a recess gate covering the recess gate pattern on the gate insulating layer; Recess gate manufacturing method of a semiconductor device comprising a. The method of claim 10, The recess gate mask, A linear first open pattern formed on the active region and a second linear open pattern extending in the same axial direction from the first open pattern and formed on the field oxide layer and having a smaller width than the first open pattern. Recess gate manufacturing method of a semiconductor device provided. The method of claim 11, The first open pattern and the second open pattern are straight line patterns, and one side of the first open pattern and one side of the second open pattern are connected without bending, and the other side of the first open pattern and the first 2. A method of manufacturing a recess gate of a semiconductor device in which the other side of the open pattern is curved and connected to form a wave. The method of claim 12, In the open pattern of the recess gate mask, A recess gate manufacturing method of a semiconductor device in which a pair of neighboring open patterns are arranged in a symmetrical structure. The method of claim 13, The pair of open patterns of the symmetrical structure, A method of manufacturing a recess gate of a semiconductor device in which one side surfaces of the first and second open patterns connected without bending face each other. The method according to any one of claims 12 to 14, And a connection point between the first open pattern and the second open pattern is a point where the active area is changed to the field oxide layer. The method of claim 15, The connection point between the first open pattern and the second open pattern is Recess gate manufacturing method of a semiconductor device drawing diagonally. The method of claim 16, The connection point between the first open pattern and the second open pattern is A method of manufacturing a recess gate of a semiconductor device, wherein a third open pattern having a predetermined area has a predetermined area, the line width of which is reduced from an end of the other side of the first open pattern. The method of claim 17, The third open pattern is a recess gate manufacturing method of a semiconductor device having a triangular shape. The method according to any one of claims 12 to 14, And a width of the second open pattern is in a range of 40 to 70% of a width of the first open pattern.

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