KR100790453B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to stably control degradation of a gate due to HEIP(Hot Electron Induced Punch-Through) by using a thick gate dielectric for increasing a threshold voltage at a boundary region of an active region and an isolation layer. An isolation layer(404) defining an active region is formed in a semiconductor substrate. A first gate dielectric is formed on the semiconductor substrate. The first gate dielectric is etched to remain in a boundary region of an active region and an isolation layer in a channel width direction. A second gate dielectric is formed on the remaining first gate dielectric and the semiconductor substrate. A gate conductive layer and a hard mask layer are formed on the second gate dielectric. The hard mask layer, the gate conductive layer, and the second gate dielectric are etched to form a gate(422) having the gate dielectrics whose boundary region of the active region and the isolation layer in the channel width direction is relatively thicker. A junction region is formed in the active region of the semiconductor substrate at both sides of the gate. Plural bit-line contacts(428) are formed to be contacted to the junction regions. A bit-line(B) is formed to be connected to the bit-line contacts.

Description

[0001] The present invention relates to a manufacturing method of a semiconductor device,

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view and a cross-sectional view of a PMOS in a surrounding region.

FIG. 2 is a sectional view showing a threshold voltage drop in the active region and the boundary region of the device isolation film due to the deterioration of the gate in the peripheral region PMOS. FIG.

3 is a cross-sectional view of a conventional gate tapped PMOS;

FIGS. 4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Description of the Related Art [0002]

404: Element isolation film 406: Surface oxide film

408: surface nitride film 422: gate

424: source region 426: drain region

428: Bit line contact

B: bit line C: junction region

D: Third-stage gate insulating film forming region

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of stably controlling deterioration of a gate in a peripheral area PMOS to maintain a current for signal transmission of a PMOS without decreasing a bit line contact And a method of manufacturing a semiconductor device.

Along with the advancement of semiconductor technology, the speeding up and the high integration of semiconductor devices are rapidly proceeding, and along with this, there is a growing demand for miniaturization of patterns and high precision of pattern dimensions.

As a result of the improvement of the productivity of the DRAM (Dynamic Random Access Memory) and the technological advancement, the design rule for the DRAM has been reduced. As the design rule is reduced, the length of the transistor is getting smaller, Deterioration of PMOS in the surrounding area is getting worse.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top view and a cross-sectional view of a PMOS in a surrounding region.

As shown in the figure, the peripheral region PMOS includes a device isolation film 104 that defines an active region in the semiconductor substrate 102, and a surface oxide film 106 and a surface nitride film 104 are formed in a boundary region between the active region and the device isolation film 104. [ (Not shown). A gate 122 made of a gate insulating film 110, a polysilicon film 116, a metal film 118, and a hard mask film 120 is formed on the semiconductor substrate 102. Source and drain regions 124 and 126 are formed on both sides of the gate 122 and a bit line contact 128 and a bit line B are formed on the active region of the semiconductor substrate 102 .

On the other hand, the signal transmission of the PMOS consists of flowing a carrier, that is, a hole, from the source region 124 to the drain region 126. At this time, the deterioration of the gate due to the hot electron induced punch-through (HEIP) occurs due to the interface property, which occurs in the active region and the boundary region A of the device isolation film 104, And the electrons trapped in the gate insulating film 110 formed on the interface and the upper surface of the gate insulating film 108.

A hole in the PMOS region of the drain region 126 flows from the source region 124 to the drain region 126. In this case, Lattice to cause electron ionization (impact ionization) and generate electron-hole pairs. At this time, the generated holes flow into the drain region 126 together with the current holes to cause no problem. However, some of the generated electrons, which are high in energy, are injected into the active region and the device isolation film 104, The interface between the surface oxide film 106 and the surface nitride film 108 in the boundary region A of the gate insulating film 110 and the gate insulating film 110 are physically trapped and deteriorated.

The threshold voltage Vt drops greatly in the boundary region A between the active region and the device isolation film 104 due to the gate deterioration caused by the trapped electrons.

FIG. 2 is a cross-sectional view illustrating a threshold voltage drop in the active region and the boundary region of the device isolation layer due to the deterioration of the gate in the peripheral region PMOS.

As shown in the sectional view in which the active region and the boundary region A of the isolation film 106 are cut across the source / drain regions 124 and 126 around the gate 222, The electrons trapped in the channel of the PMOS and electrons trapped in the gate insulating film 110 due to the above-described electron ionization are trapped in the channel width direction, Drain regions 124 and 126 are extended by overlapping the trapped electrons in the interface between the oxide film (not shown) and the surface nitride film (not shown) and the gate insulating film 110, _eff is reduced. As a result, the threshold voltage (Vt) drops greatly and a problem occurs in the reliability of the PMOS in the surrounding area.

Meanwhile, in order to prevent deterioration of the above-described gate, a method of forming a gate tab has been used.

3 is a cross-sectional view showing a conventional gate tapped PMOS.

As shown in the figure, when the gate 322 is formed in the PMOS as a method for preventing deterioration of the gate in the conventional PMOS, the gate 322 is formed in the width direction of the channel in the boundary region between the active region and the device isolation film 206 And a gate tab 332 formed so as to protrude was provided and used.

When the gate tab 332 is formed as described above, the length and width of the gate 322 are increased in the boundary region between the active region and the isolation film 304, Even if the channel length is reduced, the PMOS is not damaged by the electron trap.

That is, the length of the gate 322 is locally extended in the boundary region between the active region and the device isolation film 304, and the threshold voltage Vt of the PMOS central portion is maintained, By increasing the threshold voltage in the boundary region, even if a drop of the threshold voltage occurs in the active region in the channel width direction and the boundary region of the device isolation film 304, the PMOS is not damaged.

However, in the case where the gate tab 332 is formed as a method for preventing deterioration of the gate, in order to prevent the etch gate damage of the bit line contact 328 in the peripheral region PMOS, A certain space must be secured between the gate 328 and the gate 322.

Therefore, the number of the bit line contacts 328 for signal transmission of the PMOS must be reduced due to the gate tab 332 formed at the boundary between the active region and the device isolation film 304. Particularly, when the active region width is narrow The problem is more serious. And, due to the reduced number of bit line contacts 328, a decrease in current for signal propagation of the PMOS occurs and the speed of the transistor decreases.

The present invention proposes a method of fabricating a semiconductor device capable of stably controlling the deterioration of a gate in a peripheral region PMOS to maintain a current for signal transmission of a PMOS without reducing a bit line contact.

In one embodiment, a method of manufacturing a semiconductor device includes: forming an isolation film to define an active region in a semiconductor substrate; Forming a first gate insulating film on the semiconductor substrate; Etching the first gate insulating film so as to remain in the active region in the channel width direction and the boundary region of the device isolation film; Forming a second gate insulating film on the remaining first gate insulating film and the semiconductor substrate; Forming a gate conductive film and a hard mask film on the second gate insulating film; Etching the hard mask layer, the gate conductive layer, and the second gate insulating layer to form a gate having a gate insulating layer having a relatively thick boundary region between the active region and the device isolation layer in the channel width direction; Forming a junction region within the semiconductor substrate active region on either side of the gate; Forming a plurality of bit line contacts in contact with the junction regions; And forming a bit line connected to the bit line contacts.

And a thickness of the gate insulating film in the boundary region between the active region and the device isolation film is 50 to 200 ANGSTROM.

The difference in thickness of the gate insulating film between the active region and the active region is 10 to 200 ANGSTROM.

And forming a third gate insulating film on the second gate insulating film.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, a gate insulating film is locally formed in two or three stages in the active region of the peripheral region PMOS and the boundary region of the device isolation film, and the gate insulating film is formed in one or two stages on the other semiconductor substrate, The threshold voltage (Vt) in the boundary region between the gate electrode and the device isolation film is increased to minimize the generation of gate deterioration due to the HEIP.

That is, except for the center part of the PMOS that satisfies the threshold voltage, the threshold voltage of the active region and the device isolation region is locally increased to reduce the flow amount of carriers, which are active regions and device isolation regions, It is possible to reduce the damage of the PMOS by reducing the amount of electrons generated by electron ionization trapped in the region and gate insulating film.

Therefore, by increasing the threshold voltage in the active region in the channel width direction and the boundary region of the device isolation film by the local thickness up method, the same effect as in the case where the gate tab is attached without increasing the additional gate length and width such as the gate tap is obtained It is not necessary to reduce the number of bit line contacts, and therefore, the current for the signal transmission of the PMOS can be conserved, so that the speed reduction of the PMOS transistor can be prevented.

4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

4A, an isolation layer 404 is formed to define an active region by a shallow trench isolation (STI) process. A surface oxide layer 406 is formed in a boundary region A between the active region and the isolation layer 404, The first gate insulating film 410 is formed on the semiconductor substrate 402 on which the surface nitride film 408 is formed.

Referring to FIG. 4B, a mask pattern (not shown) is formed on the first gate insulating layer 410 so that a portion of the active region except for the boundary region A between the active layer and the isolation layer 404 is exposed to the outside, The first gate insulating film 410 is etched so as to remain in the active region in the channel width direction and the boundary region A between the device isolation film 404.

Referring to FIG. 4C, the first gate insulating layer 410 remaining in the boundary region A between the active region and the device isolation layer 404 and the second gate insulating layer 412 are formed on the semiconductor substrate 402.

Referring to FIG. 4D, a third gate insulating layer 414 is formed on the second gate insulating layer 412. Here, the gate insulating films 410, 412, and 414 formed in three stages in the boundary region A between the active region and the device isolation film 404 have a thickness of about 50 to 200 ANGSTROM. The gate insulating films 410, 412 and 414 formed in three stages in the boundary region A between the active region and the device isolation film 404 and the gate insulating films 412 and 414 formed in two stages in the other active region The difference is about 10 to 200 ANGSTROM. The gate insulating films may be formed in two stages and one stage in the active region and in the boundary region A between the active region and the isolation film 404, respectively.

4E, a polysilicon film 416 as a gate conductive film, an electrode film 418, and a hard mask film 420 are sequentially stacked on the third gate insulating film 414. Then, the hard mask film 420, the electrode film 418, the polysilicon film 416 and the first to third gate insulating films 410, 412, and 414 are formed, after forming a mask pattern for forming the gate, So that the active region in the channel width direction and the boundary region A between the device isolation films 404 form the gate 422 having the relatively thick gate insulating films 410, 412, and 414.

4E, after forming a junction region (not shown) in a manner known in the semiconductor substrate active regions on either side of the gate 422, a plurality of bit line contacts (not shown), which are in contact with the junction regions 428 and forms a bit line B that is connected to the bit line contacts 428.

In this manner, in the active region in the channel width direction and the boundary region of the device isolation film 404, a thick film having a gate insulating film (not shown) formed in the third-stage gate insulating film formation region, Thereby increasing the threshold voltage in the region and obtaining the same effect as in the case where the conventional gate tab is attached.

Therefore, since the current for the signal transmission of the PMOS can be conserved without reducing the number of the bit line contacts 316, the speed reduction of the PMOS transistor can be prevented.

While the present invention has been particularly shown and described with reference to specific embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be readily apparent to those skilled in the art that the present invention can be modified and changed without departing from the scope of the present invention.

As described above, according to the present invention, by forming the gate insulating film thicker locally in the active region in the channel width direction and the boundary region of the device separating film in the peripheral region PMOS, the threshold voltage Vt ), It is possible to stably control the deterioration of the gate caused by the HEIP.

Therefore, it is possible to maintain the current for signal transmission without reducing the number of bit line contacts in the peripheral PMOS, thereby preventing the speed reduction of the PMOS.

Claims (4)

Forming an element isolation film defining an active region in a semiconductor substrate; Forming a first gate insulating film on the semiconductor substrate; Etching the first gate insulating film so as to remain in the active region in the channel width direction and the boundary region of the device isolation film; Forming a second gate insulating film on the remaining first gate insulating film and the semiconductor substrate; Forming a gate conductive film and a hard mask film on the second gate insulating film; Etching the hard mask layer, the gate conductive layer, and the second gate insulating layer to form a gate having a gate insulating layer having a relatively thick boundary region between the active region and the device isolation layer in the channel width direction; Forming a junction region within the semiconductor substrate active region on either side of the gate; Forming a plurality of bit line contacts in contact with the junction regions; And Forming a bit line coupled to the bit line contacts; And forming a second insulating film on the semiconductor substrate. The method according to claim 1, Wherein the thickness of the gate insulating film in the boundary region between the active region and the device isolation film is 50 to 200 ANGSTROM. The method according to claim 1, Wherein a difference in thickness of the gate insulating film between the active region and the active region is 10 to 200 ANGSTROM. The method according to claim 1, And forming a third gate insulating film on the second gate insulating film.

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