KR20080027083A - Analog to digital converter - Google Patents

Abstract

An analog to digital converter is provided to decrease the number of pins allocated to an analog input pin by receiving an analog signal by controlling an external channel selector. An analog to digital converter includes a first channel selector(120), an ADC(140), a second channel selector(160), and a memory(180). The first channel selector includes at least one analog channel and at least one analog extension channel and selects one of the channels. The ADC(Analog Digital Converter) converts an analog signal which is applied through the selected channel, to a digital signal. The second channel selector includes at least one digital channel, to which a digital signal is applied, and selects one of the digital channels. The memory includes the same number of registers as the analog channels and the analog extension channels. The memory stores the digital signal on the register corresponding to the selected digital channel.

Description

Analog to Digital Converters {Analog to Digital Converter}

1 is a block diagram schematically illustrating a general analog / digital converter.

2 is a block diagram schematically showing an analog-digital converter according to an embodiment of the present invention.

3 is a detailed block diagram of the analog-digital converter shown in FIG.

* Description of the symbols for the main parts of the drawings *

100: analog / digital converter 120: first channel selector

122: analog channel portion 124: analog expansion channel portion

140: A / D converter 142: signal converter

144: controller unit 160: second channel selection unit

180: storage unit

The present invention relates to an analog-to-digital converter, and more particularly, the same A / D as the analog-to-digital converter before reduction, even though the number of analog channels in the analog-to-digital converter formed of a single chip-set is reduced. The present invention relates to an analog-to-digital converter that achieves high integration while performing a conversion process.

In general, in an image forming system or a digital video system such as a digital TV (DTV) that includes a host device and a printing device and outputs a predetermined image to a print medium such as printing paper, the applied analog signal is output to the print medium or In order to display on the screen, an analog to digital (A / D) conversion process of digitally encoding an analog signal is required.

The A / D conversion process is a process of converting a continuously changing analog signal into a discrete digital signal. An example of a single chip-set A / D converter for performing such an A / D conversion process is shown in FIG. 1.

1 is a block diagram schematically illustrating a general analog / digital converter.

Referring to FIG. 1, a general A / D converter 10 includes a multiplexer 20, an A / D converter 30, a demultiplexer 40, and a register 50.

The multiplexer 20 has n analog channels through which n analog signals ANn applied from the outside are transmitted, and the n multiplexers 20 responds to the first control signal CS1 output from the A / D converter 30. One of the analog channels is selected to output an analog signal input through the selected channel. The output analog signal is input to the A / D converter 30.

The A / D converter 30 controls control signals CS1 and CS2 for controlling the overall driving of the A / D converter 32 and the A / D converter 10 for directly converting an input analog signal into a digital signal. And a controller 34 for outputting CS3).

In response to the third control signal CS3 applied from the controller 34, the A / D converter 32 digitally maps the analog signal output from the multiplexer 20 to an approximation to the phase of the analog signal continuously changing. Convert it to a signal and output it.

The controller 34 outputs the above-described first control signal CS1, the second control signal CS2 for controlling the demultiplexer 40, and the above-described third control signal CS3. Here, the third control signal CS3 is a clock signal, an SOC signal (Start of Conversion) indicating the start time of the A / D conversion process in synchronization with the clock signal, and an EOC indicating the end time of the A / D conversion process. (End of Conversion) signal. In addition, the controller 34 may further output a channel change signal that performs an A / D conversion process by changing a channel in addition to the above-described signals.

First, the register 50 will be described. The register 50 stores digital signals output from the A / D converter 32. For this purpose, the A / D converter 32 is formed of the same number of registers as the number of channels of the multiplexer 20. That is, when the number of channels of the multiplexer 20 is n, it is formed of n registers.

The demultiplexer 40 selects a register for storing the digital signal output from the A / D converter 32 in response to the second control signal CS2 output from the controller 34.

That is, when the analog signal is input through the first channel of the multiplexer 20 under the control of the controller 34, the demultiplexer 40 may convert the digital signal converted through the A / D converter 32 to correspond to the first channel. Select a first channel on demultiplexer 40 coupled with the first register to be stored in the first register. Accordingly, the analog signal input through one channel is converted into a digital signal and stored in a register.

In the case of the general A / D converter 10, the A / D converter 10 formed of a single chip-set must set n signal pins corresponding to n channels as analog input dedicated pins.

However, in the case where the A / D converter 10 is formed in a single chip-set and applied to a system in such a structure, the case in which the entire n channels are not used among the n channels according to the application field of the system is an example. For example, if two analog dedicated input pins are used, the remaining n-2 analog dedicated input pins are configured as unused pins.

In this case, the size of a single chip-set increases due to the n-2 remaining pins and the circuit configuration connected to the n-2 pins, which is contrary to the miniaturization tendency of the product. There is a problem that causes inefficiency in the use of the D converter 10.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to achieve high integration while performing the same A / D conversion process as the analog / digital converter before reduction, even though the number of analog channels is reduced. To provide an analog / digital converter.

In order to achieve the above object of the present invention, an analog / digital converter according to an embodiment of the present invention includes a first channel selector, an analog / digital converter, a second channel selector, and a storage. The first channel selector includes at least one analog channel and an analog extension channel, and selects one of the channels. The analog / digital converter converts an analog signal applied through the selected channel into a digital signal. The second channel selector includes at least one digital channel to which the digital signal is applied, and selects one of the digital channels. The storage unit has the same number of registers as the total number of the analog channel and the analog extension channel, and stores the digital signal in a register corresponding to the selected digital channel.

The first channel selector may be connected to at least one external channel selector connected to each of the analog extension channels, and the analog / digital converter may output an external control signal for controlling the external channel selector. have.

In this case, the analog / digital converter may include at least one digital channel for outputting the external control signal.

In this case, the digital channel may be formed as a general purpose input / output (GPIO) channel when the external control signal is not output.

The analog / digital converter may include a signal converter converting the analog signal into the digital signal, first and second control signals for controlling the first channel selector, and a second channel selector, respectively, and the external control signal. And a controller unit for outputting a third control signal for converting the analog signals into digital signals according to a predetermined period.

According to such an analog-to-digital converter, by controlling an external channel selector to receive an analog signal, the number of pins allocated as analog input pins to a single chip set and the number of analog channels in a single chip set can be reduced. have. Therefore, high integration of a single chip-set can be achieved. In addition, when the external channel selector is not controlled, the digital pin or the digital channel may be switched for various purposes.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram schematically showing an analog-digital converter according to an embodiment of the present invention.

2, the analog / digital converter 100 according to an embodiment of the present invention includes a first channel selector 120, an A / D converter 140, a second channel selector 160, and The storage unit 180 is included.

In detail, the first channel selector 120 includes an analog channel unit 122 and an analog extension channel unit 124.

The analog channel unit 122 is connected to n signal pins among pins allocated as analog input pins among the signal pins formed outside the A / D converter 100 formed as a single chip-set.

The analog expansion channel unit 124 is a signal pin formed outside the A / D converter 100 formed as a single chip-set, except for the pins connected to the analog channel unit 122 among the pins allocated as analog input pins. Signal pins.

In this case, when the analog signal input to the analog expansion channel unit 124 is connected to a multiplexer formed outside the A / D converter 100, at least one signal pin of the m signal pins described above may be inputted. It may have various values according to the external circuit structure, through which the number of analog channels of the A / D converter 100 may be formed in a variable number.

That is, the A / D converter 100 includes n + m analog input pins, but the A / D converter 100 may include n + m or more analog channels according to an external circuit structure. At the same time, more than n + m analog signals can be received.

The first channel selector 120 selects one of the channels to which the analog signal ANn and the extended analog signal ANm are applied in response to the first control signal CS1 applied from the A / D converter 140. The controller outputs one of the analog signal and the extended analog signal applied through the selected channel to the A / D converter 140.

The A / D converter 140 outputs a first control signal CS1 applied to the first channel selector 120 and a second control signal CS2 applied to the second channel selector 160. In addition, the A / D converter 140 converts one analog signal applied through the channel selected by the first channel selector 120 into a digital signal and outputs the digital signal to the second channel selector 160.

First, the storage unit 180 will be described. The storage unit 180 stores the digital signal output from the A / D converter 140. Here, the digital signal output from the A / D converter 140 is a digital signal having a predetermined number of quantized bits obtained by converting an analog signal applied through the channel selected by the first channel selector 120, and the storage unit 180. ) Has at least one register capable of storing each bit number. This will be described in more detail with reference to FIG. 3.

The second channel selector 160 may include a storage unit for storing the digital signal output from the A / D converter 140 in response to the second control signal CS2 output from the A / D converter 140. Select register 180).

That is, by selecting a channel to which the digital signal output from the A / D converter 140 is input, a register of the storage unit 180 in which the digital signal is stored may be selected. For example, when the first analog signal AN1 is input through the first channel of the first channel selector 160, the first digital signal converted through the A / D converter 140 corresponds to the first channel. For example, the first channel of the second channel selector 160 connected to the first register is selected to be stored in the first register.

The A / D converter 100 will be described in more detail as follows.

3 is a detailed block diagram of the analog-digital converter shown in FIG.

2 and 3, the A / D converter 100 according to an embodiment of the present invention may include a first channel selector 120, an A / D converter 140, and a second channel selector ( 160 and the storage unit 180.

In detail, the first channel selector 120 outputs the same number (n + m) of analog signals as the analog input pins connected to the analog channel unit 122 and the analog input pins connected to the analog expansion channel unit 124. At the same time, an analog signal input through the selected channel is output by activating one of the channels formed in each of the channel units 122 and 124 based on the first control signal CS1.

To this end, the first channel selector 120 may be formed as (n + m) × 1 multiplexer (MUX) as shown. Here, it is apparent that the (n + m) × 1 multiplex may be formed of switching elements such as a MOS transistor which is generally connected to an arbitrary node between the resistor string and the resistors included in the resistor string. Detailed description will be omitted.

The n channels included in the analog channel unit 122 are connected to n analog dedicated input pins outside the single chip-set, and the m channels included in the analog expansion channel unit 124 are analog outside the single chip-set. It is connected to m signal pins except pins connected to the analog channel 122 among the pins allocated as dedicated input pins. The m analog dedicated input pins are connected to an external channel selector 200 formed outside the A / D converter 100. In this case, the external channel selector 200 may be formed of, for example, at least one external multiplexer (MUX). The external multiplexer (MUX) includes kn channels, and kn analog signals are provided through each channel. Can be entered.

Here, k denotes the total number of analog signals that can be simultaneously input through the A / D converter 100, that is, the total number of channels of the A / D converter 100. In FIG. 2, only one external channel selector 200 is shown as an example. However, the external channel selector 200 may include one or more external signal pins. As many as the number of external channel selectors 200 may be allocated to the analog input pins. That is, the above-described variables n, m, k can be set to various values by the designer.

Accordingly, in the first channel selector 120, the external channel selector 200 includes one channel among kn channels, that is, one channel of the analog extension channel unit 124 and the channels of the analog channel unit 122. One of them is selected and an analog signal applied through the selected channel is output to the A / D converter 140.

The A / D converter 140 includes a signal converter 142 and a controller 144.

The signal converter 142, for example, receives an analog signal selected by the first channel selector 120, and continuously changes the analog signal in response to the third control signal CS3 applied from the controller 144. It converts and outputs the digital signal mapped to the phase of.

Here, the third control signal CS3 is a clock signal, an SOC signal (Start of Conversion) indicating the start time of the A / D conversion process every predetermined period in synchronization with the clock signal, and the A / D conversion process every predetermined period. It includes an end of conversion (EOC) signal indicating the end time. In addition, the third control signal CS3 includes a channel change signal for performing an A / D conversion process by changing a channel in addition to the above-described signals, and performing an A / D conversion process according to a preset quantization bit number. The control signal may be further included.

The controller 144 may include a first control signal CS1 for controlling one channel to be selected by the first channel selector 120, a third control signal CS3 for controlling the signal converter 142, and The second control signal CS2 for controlling the second channel selector 160 is output.

In addition, the controller unit 144 of the A / D converter 100 according to an embodiment of the present invention controls the external channel selector 200 formed outside the A / D converter 100 to select an external channel. The fourth control signal CS4 for selecting one of the kn channels formed in the unit 200 is output.

In this case, a digital signal pin for inputting the fourth control signal CS4 is assigned to a single chip-set of the A / D converter 100, and the fourth control signal CS4 is not shown, It is formed inside the D converter 100 and is output through a digital channel connected to the above-described digital signal pin.

Here, the first, second and fourth control signals CS1, CS2, CS4 may be formed to have the number of bits corresponding to the minimum natural number among natural numbers of log ₂ (n + m) or more, and the digital signal pin may also be The number of bits equal to the number of bits of the fourth control signal CS4 may be allocated.

The digital signal pin thus formed and the digital channel connected thereto have the fourth control signal when the analog signal is not provided from the external channel selector 200, that is, when the analog signal is applied through only a single chip set. It does not need to be used as a pin to output CS4). Accordingly, the digital signal pin and the digital channel outputting the fourth control signal CS4 may be used as the general purpose input / output (GPIO) pins and channels, respectively, according to the application field or the use aspect of the A / D converter 100. have.

First, the storage unit 180 will be described. The storage unit 180 includes a plurality of registers for storing the digital signal output from the signal converter 140. Preferably, the storage unit 180 includes the same number of registers (registers 1, ..., register k) as the total number of channels that can be simultaneously input to the A / D converter 100, that is, the number of k channels. do.

The second channel selector 160 selects registers for storing the digital signal output from the signal converter 140 in response to the second control signal CS2 output from the controller 144. That is, one of the digital channels on the second channel selector 160 connected with the designated register is selected to store the digital signal in the designated register.

For example, when the first analog signal AN1 is input through the first analog channel, the first digital signal converted correspondingly through the signal converter 140 may be stored in the first register (register 1). The first digital channel on the second channel selector 160 connected to the first register (register 1) is selected.

To this end, the second channel selector 160 receives one digital signal having the number of quantization bits in response to the second control signal CS2 and selects one channel for transmitting one digital signal to one of k registers. k demultiplexer (DMUX).

Here, since the configuration of the second channel selector 160 may be generally formed through a combination of logic gates receiving a control signal and a digital signal, a detailed description thereof will be omitted.

The A / D converter 10 shown in FIG. 1 and the A / D converter 100 shown in FIG. 3 are specifically compared as follows.

For example, when the A / D converters 10 and 100 receive 16 analog signals AN1, ..., and AN16 simultaneously, that is, both have 16 analog channels, FIG. 1. In the case of the A / D converter 10 shown in the figure, 16 analog input pins should be allocated to the outside. However, in the case of the A / D converter 100 shown in FIG. 3, eight analog dedicated input pins connected to any number of eight analog channel units 122 are allocated, and the analog expansion channel unit ( 124) and only one analog dedicated input pin to be connected to the external channel selector 200 need to be allocated a total of nine analog dedicated input pins. As a result, the number assigned to the analog input pins is reduced by seven.

At this time, eight analog signals AN1, ..., AN8 are input through the analog channel unit 122, and the remaining eight analog signals AN8, ..., AN16 are sent to the external channel selector 200. Is entered. As for the analog signal input to the external channel selector 200, only a signal input through the selected channel is input through the analog extension channel unit 124.

That is, the remaining channel obtained by subtracting the channel formed in the analog channel unit 122 from the total number of channels of the A / D converter 100 is formed by the external channel selector 200 connected to the analog extension channel unit 124. . The analog signal input through the channel selected by the external channel selector 200 by the controller unit 144 and the channel of the analog channel unit 122 is input to the signal converter 140.

Accordingly, in the present embodiment, the A / D converter 100 is assigned with nine analog input pins, and a three-bit control signal is selected to select one of eight channels formed in the external channel selector 200. Three are assigned as digital output pins for output. Through this, the number of channels in the A / D converter 100 may be reduced, and the number of input pins allocated to the analog input pins may be reduced.

The newly allocated digital output pin may be used as a GPIO pin when the external channel selector 200 is not used. In addition, even in view of the number of digital output pins, the number of external pins used is reduced compared to the A / D converter shown in FIG.

Also, by having a total number of channels, for example, 16 channels and a corresponding number of registers (registers 1, ..., register 16), it is possible to store the converted digital signal in registers with the same software, The digital signal can be output (D_out) from the same register by external control.

As described above, according to the present invention, by receiving an analog signal by controlling the external channel selector, the number of pins allocated to the analog dedicated input pins to a single chip-set can be reduced.

In addition to reducing the number of analog dedicated input pins, the number of channels formed inside the integrated circuit can be reduced, which is advantageous for high integration of a single chip-set.

In addition, when the external channel selector is not required to be controlled, a digital pin or channel for controlling the external channel selector may be switched for various purposes.

In addition, by reducing the number of pins allocated to the analog dedicated input pins, in the case of integrated circuits having the same number of pins, more GPIO pins can be secured.

While the foregoing has been described with reference to preferred embodiments of the invention, those skilled in the art will be able to make various modifications and changes to the invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (5)

A first channel selector having at least one analog channel and an analog extension channel, the first channel selector configured to select one of the channels; An analog / digital converter for converting an analog signal applied through the selected channel into a digital signal; A second channel selector having at least one digital channel to which the digital signal is applied, and selecting one of the digital channels; And And a storage unit having the same number of registers as the total number of the analog channel and the analog expansion channel, and storing the digital signal in a register corresponding to the selected digital channel. The apparatus of claim 1, wherein the first channel selector is connected to at least one external channel selector connected to each of the analog extension channels, The analog / digital converter, And an external control signal for controlling the external channel selector. The analog-to-digital converter of claim 2, wherein the analog-digital converter comprises at least one digital channel for outputting the external control signal. The apparatus of claim 3, wherein the digital channel is formed as a general purpose input / output (GPIO) channel when the external control signal is not output. The method of claim 2, wherein the analog to digital converter, A signal converter converting the analog signal into the digital signal; And Outputting first and second control signals and the external control signal for controlling the first channel selector and the second channel selector, respectively, and causing the signal converter to convert the analog signals into digital signals according to a predetermined period; And a controller unit for outputting 3 control signals.

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