KR20080026392A - Liquid crystal display and driving method thereof - Google Patents

Abstract

An LCD device and a driving method thereof are provided to prevent the reduction of the image quality of the LCD device by ensuring a time required for charging of data voltages in pixels. An LCD(Liquid Crystal Display) device includes an LCD panel(50), first and second gate drivers(20,25), and first and second data drivers(30,35). The LCD panel includes plural pixels, which are formed in matrix. The first and second gate drivers apply gate voltages to pixels corresponding to odd and even numbered pixel columns respectively. The first and second data drivers apply data voltages to pixels corresponding to the odd and even numbered pixel columns respectively.

Description

Liquid crystal display and driving method thereof

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a liquid crystal panel constituting the liquid crystal display of FIG. 1.

3 is a timing diagram illustrating output signals of the first and second gate drivers of FIG. 1.

<Description of the symbols for the main parts of the drawings>

10: signal controller 20: first gate driver

25: second gate driver 30: first data driver

35: second data driver 40: gray voltage generator

50: liquid crystal panel

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof capable of realizing ultra high resolution.

Recently, due to the trend toward larger display devices such as televisions, liquid crystal displays (LCDs), plasma display panels (PDPs), and organic EL displays (Organic ElectroLuminiscent) instead of cathode ray tubes (CRTs). Flat panel display devices such as Display (OELD) and the like have been developed. Among such flat panel display devices, a liquid crystal display device capable of being lighter and thinner is particularly attracting attention.

A liquid crystal display device injects a liquid crystal material having anisotropic dielectric constant between an upper display panel on which a common electrode, a color filter, a black matrix, and the like is formed, and a lower display panel on which a thin film transistor, a pixel electrode, and the like are formed. A display device that expresses a desired image by adjusting the intensity of an electric field formed in a liquid crystal material by applying different potentials to electrodes, thereby changing the molecular arrangement of the liquid crystal material, and controlling the amount of light transmitted through the transparent insulating substrate. .

The lower panel defines a pixel by crossing a gate line transferring a scan signal and a data line transferring an image signal, and each pixel includes a thin film transistor connected to the gate line and the data line and a pixel electrode connected to the thin film transistor. It is.

In this case, the thin film transistor includes a gate electrode which is a part of the gate line, a semiconductor layer forming a channel, a source electrode and a drain electrode which are part of the data line, and an image signal transmitted through the data line according to a scan signal transmitted through the gate line. It is a switching element for transmitting or blocking the to the pixel electrode.

Such liquid crystal displays are being developed to support ultra high resolutions such as UXGA (1600 × 1200) and QXGA (2048 × 1536) beyond the SXGA (1280 × 1024) resolution. As the resolution increases, the number of gate lines increases, thereby decreasing the gate turn-on time (that is, the time when the gate is turned on) for each gate line. As a result, the time for charging the data voltage to each pixel is shortened, resulting in a problem of deterioration of the image quality of the ultra-high resolution liquid crystal display.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a liquid crystal display device capable of securing a charging rate of a data voltage.

Another object of the present invention is to provide a method of driving such a liquid crystal display.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an exemplary embodiment of the present invention, a liquid crystal panel includes a liquid crystal panel including a plurality of pixels arranged in a matrix, and pixels corresponding to odd-numbered pixel rows among the plurality of pixels. A first gate driver applying a gate voltage to the second gate driver applying a gate voltage to pixels corresponding to even-numbered pixel rows among the plurality of pixels, and an odd-numbered pixel row among the plurality of pixels. A first data driver applies a data voltage to corresponding pixels, and a second data driver applies a data voltage to pixels corresponding to even-numbered pixel rows among the plurality of pixels.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method including: providing a liquid crystal panel including a plurality of pixels arranged in a matrix; Simultaneously applying a gate voltage to a pixel corresponding to the first and second pixel rows, applying a first data voltage to a pixel corresponding to the first pixel row, and applying a gate voltage to the pixel corresponding to the second pixel row. Applying a second data voltage.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, including a plurality of gate lines, a plurality of first and second data lines insulated from and intersecting the plurality of gate lines, Providing a liquid crystal panel including thin film transistors connected to each of the gate lines and the data lines, wherein a pair of the first and second data lines are disposed for each pixel column of the plurality of pixels; Sequentially applying gate voltages to odd-numbered gate lines of the gate lines, sequentially applying gate voltages to even-numbered gate lines of the gate lines, and applying pixels to odd-numbered gate lines. Applying a data voltage through the first data line; and applying the second data to pixels corresponding to the even-numbered gate line. Through the line includes the step of applying a data voltage.

Specific details of other embodiments are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments make the disclosure of the present invention complete and the general knowledge in the technical field to which the present invention belongs. It is provided to fully convey the scope of the invention to those skilled in the art, the invention being defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. 1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of a liquid crystal panel constituting the liquid crystal display of FIG. 1.

The liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel 50 including a plurality of pixels PX, first and second gate drivers 20 and 25 connected to the liquid crystal panel 50, and first and second liquid crystal panels 50. And a second voltage driver 30 and 35, a gray voltage generator 40 connected to the first and second data drivers 30 and 35, and a signal controller 10 for controlling them. The first and second gate drivers 20 and 25 may be disposed to face each other with the liquid crystal panel 50 interposed therebetween, and the first and second data drivers 30 and 35 may face the liquid crystal panel 50. Can be placed to face each other.

The liquid crystal panel 50 includes a plurality of display signal lines G1, ..., G2n, Da1, ..., Dam, Db1, ..., Dbm and a plurality of pixels PX connected thereto and arranged in a substantially matrix form. . The liquid crystal panel 50 includes a lower panel (not shown) facing each other, an upper panel (not shown), and a liquid crystal layer (not shown) interposed therebetween.

The display signal line is provided in the lower display panel and includes a plurality of gate lines G1,..., G2n transmitting the gate signals and data lines Da1,..., Dam, Db1,..., Dbm transmitting the data signals. . The gate lines G1, ..., G2n extend substantially in the row direction and are substantially parallel to each other, and the data lines Da1, ..., Dam, Db1, ..., Dbm extend substantially in the column direction and are substantially parallel to each other.

Here, the gate lines G1,..., G2n are odd-numbered gate lines G2k-1 connected to the first gate driver 20 and even-numbered gate lines G2k connected to the second gate driver 25. It is composed. The first gate driver 20 transmits a gate voltage to the pixels PX constituting the odd pixel rows through the odd-numbered gate lines G2k-1, and the second gate driver 25 supplies the even-numbered gate lines ( The gate voltage is transmitted to the pixels PX constituting the even-numbered pixel rows through G2k.

The data lines Da1, ..., Dam, Db1, ..., Dbm each include a pair of first data lines Dai and second data lines Dbi arranged for each pixel column. The first data line Dai is connected to the first data driver 30, and the second data line Dbi is connected to the second data driver 35. The first data driver 30 transmits a data voltage to the pixel PX corresponding to the odd pixel row through the first data line Dai, and the second data driver 35 transmits the second data line Dbi. The data voltage is transmitted to the pixel PX corresponding to the even-numbered pixel row through the pixel PX.

Therefore, the pixel PX corresponding to the odd pixel row is connected to the first gate driver 20 and the first data driver 30 through the odd gate line G2k-1 and the first data line Dai, respectively. It is. The pixel PX corresponding to the even-numbered pixel row is connected to the second gate driver 25 and the second data driver 35 through the even-numbered gate line G2k and the second data line Dbi, respectively. .

In addition, the liquid crystal panel 50 is provided with a pixel electrode and a common electrode for applying an electric field to the liquid crystal layer. The pixel electrode is formed on the lower panel in pixel units, and the common electrode is formed on the entire upper panel. In some embodiments, the common electrode may be provided on the lower panel, and at least one of the pixel electrode and the common electrode may be formed in a linear or bar shape. A liquid crystal capacitor having such a pixel electrode and a common electrode as two terminals and a liquid crystal layer between the pixel electrode and the common electrode as a dielectric is formed.

The storage capacitor, which serves as an auxiliary part of the liquid crystal capacitor, is formed by overlapping the storage electrode line and the pixel electrode provided on the lower panel with the insulator interposed therebetween. The storage voltage Vcom provided to the storage electrode line maintains an output signal of the thin film transistor (that is, a data voltage transmitted to the pixel electrode).

On the other hand, in order to implement color display, each pixel uniquely displays one of the primary colors (spatial division) or each pixel alternately displays three primary colors over time (time division) so that the spatial and temporal combinations of these three primary colors can be achieved. To recognize the desired color. Examples of primary colors include red, green and blue. As an example of spatial division, each pixel may include a color filter representing one of the primary colors in an area of the upper panel. In addition, the color filter may be formed above or below the pixel electrode of the lower panel.

The signal controller 10 may control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync. ), A main clock MCLK, a data enable signal DE, and the like. Based on the input image signals R, G, and B and the input control signal of the signal controller 10, the image signals R, G, and B are properly processed according to the operating conditions of the liquid crystal panel 50, and the gate control signal ( After generating the CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the first and second gate drivers 20 and 25, and the data control signal CONT2 and the processed image signal DAT are generated. Is exported to the first and second data drivers 30 and 35.

The gate control signal CONT1 includes a scan start signal STV indicating the start of scanning and at least one clock signal controlling the output time of the gate-on voltage Von. The gate control signal CONT1 may also include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 applies a corresponding data voltage to the horizontal synchronization start signal STH and the data lines Da1,..., Dam, Db1,. Includes a load signal LOAD and a data clock signal HCLK. The data control signal CONT2 also inverts the signal RVS, which inverts the polarity of the data voltage with respect to the common voltage Vcom, where "polarity of the data voltage with respect to the common voltage" means "polarity of the data voltage." It may include.

According to the data control signal CONT2 from the signal controller 10, the first and second data drivers 30 and 35 receive the image data DAT for the pixel PX, and the gray voltage generator 40 By converting the image data DAT to the corresponding data voltage by selecting the gradation voltage corresponding to the image data DAT from), it is applied to the corresponding data lines Da1, ..., Dam, Db1, ..., Dbm. .

The first and second gate drivers 20 and 25 apply the gate-on voltage Von to the gate lines G1,..., G2n in response to the gate control signal CONT1 from the signal controller 10. The thin film transistor connected to (G1, ..., G2n) is turned on, and accordingly, the data voltage applied to the data lines Da1, ..., Dam, Db1, ..., Dbm is turned on to the pixel PX through the turned-on thin film transistor. Is approved. Thereafter, the first and second gate drivers 20 and 25 apply the gate-off voltage Voff to the gate lines G1, G2n and G2n according to the gate control signal CONT1. Turn off the thin film transistor connected to

The difference between the data voltage applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage. Accordingly, the polarization of light passing through the liquid crystal layer changes, which is represented by a change in the transmittance of light.

Hereinafter, a driving method of a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3. 3 is a timing diagram illustrating output signals of the first and second gate drivers of FIG. 1.

1 to 3, the odd-numbered gate line G2k-1 is connected to the first gate driver 20, and the even-numbered gate line G2k is connected to the second gate driver 25. It is.

First, the first and second gate drivers 20 and 25 simultaneously output high gate driving signals Vg1 and Vg2 to the first gate line G1 and the second gate line G2, respectively. Both thin film transistors connected to the first gate line G1 and the second gate line G2 are turned on. Therefore, the data voltage is applied to the pixel PX connected to the first gate line G1 through the first data lines Da1,..., Dam, and the second voltage is applied to the pixel PX connected to the second gate line G2. The data voltage is applied through the data lines Db1, ..., Dbm.

Subsequently, the first and second gate drivers 20 and 25 simultaneously output high gate driving signals Vg3 and Vg4 to the third gate line G3 and the fourth gate line G4, respectively. Both the thin film transistors connected to the third gate line G3 and the fourth gate line G4 are turned on. Accordingly, the data voltage is applied to the pixel PX connected to the third gate line G3 through the first data lines Da1,..., Dam, and the second voltage is applied to the pixel PX connected to the fourth gate line G4. The data voltage applied to the data lines Db1, ..., Dbm is applied.

As described above, the first and second gate drivers 20 and 25 simultaneously apply the gate driving signal having the high state to the 2k-1 th gate line G2k-1 and the 2k th gate line G2k, and the two gate lines. The gate driving signals of the high state are sequentially applied in units of. Therefore, the frequency of the gate driving signal of one frame is reduced by 1/2, so that the time when the gate driving signal of each high state is applied, that is, the gate turn-on time can be doubled. Therefore, the charging time of the data voltage can be sufficiently secured by doubling the time that the data voltage can be charged in each pixel.

In addition, even if two gate lines are turned on at the same time, different data lines are allocated to each gate line, and different data voltages are applied to each data line, thereby achieving high resolution.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

As described above, according to the liquid crystal display and the driving method thereof, the image quality of the ultra-high resolution liquid crystal display can be prevented by ensuring sufficient time for each pixel to be charged with the data voltage.

Claims (11)

A liquid crystal panel composed of a plurality of pixels arranged in a matrix form; A first gate driver configured to apply a gate voltage to pixels corresponding to odd-numbered pixel rows among the plurality of pixels; A second gate driver configured to apply a gate voltage to pixels corresponding to even-numbered pixel rows among the plurality of pixels; A first data driver configured to apply a data voltage to pixels corresponding to odd-numbered pixel rows among the plurality of pixels; And And a second data driver configured to apply a data voltage to pixels corresponding to even-numbered pixel rows among the plurality of pixels. According to claim 1, The liquid crystal panel includes a plurality of gate lines, a plurality of first and second data lines that are insulated from and cross the plurality of gate lines, and thin film transistors connected to the gate lines and the data lines, And a pair of the first and second data lines for each pixel column of the plurality of pixels. The method of claim 2, And the first gate driver is connected to the odd-numbered gate lines, and the first data driver is configured to transfer data voltages to pixels corresponding to the odd-numbered pixel rows through the first data lines. The method of claim 2, And the second gate driver is connected to the even-numbered gate lines, and the second data driver is configured to transfer data voltages to pixels corresponding to the even-numbered pixel rows through the second data lines. The method of claim 2, And the first and second gate drivers sequentially apply a gate driving signal of a high state in units of two adjacent gate lines. According to claim 1, And the first and second gate drivers are disposed to face each other with the liquid crystal panel therebetween. According to claim 1, And the first and second data drivers are disposed to face each other with the liquid crystal panel therebetween. Providing a liquid crystal panel composed of a plurality of pixels arranged in a matrix; Simultaneously applying a gate voltage to pixels corresponding to neighboring first and second pixel rows among the plurality of pixels; And And applying a first data voltage to a pixel corresponding to the first pixel row, and applying a second data voltage to a pixel corresponding to the second pixel row. The method of claim 8, The liquid crystal panel includes a plurality of gate lines, a plurality of first and second data lines that are insulated from and cross the plurality of gate lines, and thin film transistors connected to the gate lines and the data lines, And a pair of the first and second data lines for each pixel column of the plurality of pixels. A plurality of gate lines, a plurality of first and second data lines insulated from and intersecting the plurality of gate lines, and thin film transistors connected to the gate lines and the data lines, wherein each of the plurality of pixels Providing a liquid crystal panel in which a pair of the first and second data lines are arranged per column; Sequentially applying gate voltages to odd-numbered gate lines of the gate lines; Sequentially applying gate voltages to even-numbered gate lines of the gate lines; Applying a data voltage to the pixels corresponding to the odd-numbered gate lines through the first data line; And And applying a data voltage to the pixels corresponding to the even-numbered gate line through the second data line. The method of claim 10, And a gate voltage applied to two adjacent gate lines among the gate lines at the same time.

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