KR20080025577A - Lcd and drive method thereof - Google Patents

Abstract

An LCD(Liquid Crystal Display) device and a driving method thereof are provided to reduce a time required for discharging a charge voltage by discharging rapidly the charge voltage of respective pixels. An LCD(Liquid Crystal Display) device includes a voltage detector(210), a timing controller(220), and a gate driver(240). The voltage detector detects the level of a source voltage supplied from outside. The timing controller controls the generation of a charging scan pulse or blocks the supplement of a data voltage according to the level of the source voltage detected in the voltage detector. The gate driver supplies the charging scan pulses or generates the discharging scan pulse under control of the timing controller.

Description

Liquid crystal display and driving method thereof

1 is an equivalent circuit diagram of a pixel formed in a general liquid crystal display device.

2 is a block diagram of a conventional liquid crystal display device.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a signal characteristic diagram at power-on of the liquid crystal display according to the present invention.

5 is a signal characteristic diagram at power off of the liquid crystal display according to the present invention;

<Description of Symbols for Main Parts of Drawings>

100 and 200: liquid crystal display 110: liquid crystal display panel

120, 230: data driver 130, 240: gate driver

140: gamma reference voltage generator 150: backlight assembly

160: inverter 170: common voltage generator

180: gate driving voltage generation unit 190, 220: timing controller

210: voltage detection unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of quickly discharging charging voltages of pixels at power off.

A liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal, and an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell enables active control of the switching element. This is advantageous for video implementation. As the switching element used in the active matrix liquid crystal display device, a thin film transistor (hereinafter referred to as TFT) is mainly used as shown in FIG. 1.

Referring to FIG. 1, an active matrix type liquid crystal display converts digital input data into an analog data voltage based on a gamma reference voltage and supplies it to the data line DL and simultaneously supplies scan pulses to the gate line GL. The liquid crystal cell Clc is charged.

The gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and one electrode of the storage capacitor Cst. Connected.

The common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc.

The storage capacitor Cst charges a data voltage applied from the data line DL when the TFT is turned on to maintain a constant voltage of the liquid crystal cell Clc.

When the scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode so that the voltage on the data line DL is applied to the pixel electrode of the liquid crystal cell Clc. Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc modulate the incident light by changing the arrangement by the electric field between the pixel electrode and the common electrode.

A configuration of a conventional liquid crystal display device having pixels having such a structure will be described with reference to FIG. 2.

2 is a block diagram of a conventional liquid crystal display device.

Referring to FIG. 2, the liquid crystal display 100 according to the related art includes a thin film for driving the liquid crystal cell Clc at the intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. A liquid crystal display panel 110 having a TFT (TFT: Thin Film Transistor) formed thereon, a data driver 120 for supplying data to the data lines DL1 to DLm of the liquid crystal display panel 110, and a liquid crystal display panel ( A gate driver 130 for supplying scan pulses to the gate lines GL1 to GLn of the 110, a gamma reference voltage generator 140 for generating a gamma reference voltage and supplying the gamma reference voltage to the data driver 120; The backlight assembly 150 for irradiating light to the liquid crystal display panel 110, the inverter 160 for applying an alternating voltage and current to the backlight assembly 150, and a common voltage Vcom are generated to generate the liquid crystal display panel. Common voltage generation for supplying the common electrode of the liquid crystal cell Clc of (110) A gate driving voltage generator 180 for generating the gate high voltage VGH and the gate low voltage VGL and supplying the gate high voltage VGL to the gate driver 130, the data driver 120, and the gate driver 120. A timing controller 190 for controlling 130.

In the liquid crystal display panel 110, liquid crystal is injected between two glass substrates. The data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal to the lower glass substrate of the liquid crystal display panel 110. TFTs are formed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scan pulse. The gate electrodes of the TFTs are connected to the gate lines GL1 to GLn, and the source electrodes of the TFTs are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst.

The TFT is turned on in response to the scan pulse supplied to the gate terminal via the gate lines GL1 to GLn. When the TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The data driver 120 supplies data to the data lines DL1 to DLm in response to the data driving control signal DDC supplied from the timing controller 190, and digital video data supplied from the timing controller 190. After sampling and latching the RGB, the liquid crystal cell Clc of the liquid crystal display panel 110 is converted into an analog data voltage capable of expressing gray scale based on the gamma reference voltage supplied from the gamma reference voltage generator 140. Supply to the data lines DL1 to DLm.

The gate driver 130 sequentially generates scan pulses, that is, gate pulses, in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 190 to generate the gate lines GL1 to GLn. Feed the fields. In this case, the gate driver 130 determines the high level voltage and the low level voltage of the scan pulse based on the gate high voltage VGH and the gate low voltage VGL supplied from the gate driving voltage generator 180.

The gamma reference voltage generator 140 receives a high potential power supply voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and output the same to the data driver 120.

The backlight assembly 150 is disposed on the rear surface of the liquid crystal display panel 110 and emits light by an AC voltage and a current supplied from the inverter 160 to irradiate light to each pixel of the liquid crystal display panel 110.

The inverter 160 converts the square wave signal generated therein into a triangular wave signal and compares the triangular wave signal with a DC power supply voltage (VCC) supplied from the system to generate a burst dimming signal proportional to the comparison result. . When a burst dimming signal determined according to an internal square wave signal is generated, a driving IC (not shown) for controlling the generation of AC voltage and current in the inverter 160 is supplied to the backlight assembly 150 according to the burst dimming signal. Control the generation of alternating voltage and current.

The common voltage generator 170 receives the high potential power voltage VDD to generate the common voltage Vcom and supplies the common voltage Vcom to the common electrodes of the liquid crystal cells Clc of each pixel of the liquid crystal display panel 110.

The gate driving voltage generator 180 receives the high potential power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL to supply the gate driver 130 to the gate driver 130. Here, the gate driving voltage generation unit 180 generates a gate high voltage VGH that is greater than or equal to the threshold voltage of the TFTs provided in each pixel of the liquid crystal display panel 110, and the gate low voltage that is less than or equal to the threshold voltage of the TFT. VGL). The gate high voltage VGH and the gate low voltage VGL generated in this way are used to determine the high level voltage and the low level voltage of the scan pulse generated by the gate driver 130, respectively.

The timing controller 190 supplies digital video data RGB, which is supplied from an image processing scaler (not shown) included in a system such as a television receiver or a computer monitor, to the data driver 120, and also provides a clock signal CLK. The data driving control signal DDC and the gate driving control signal GDC are generated using the horizontal / vertical synchronizing signals H and V and supplied to the data driver 120 and the gate driver 130, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

In the conventional liquid crystal display having such a configuration and function, since the thin film transistor of each pixel is kept turned off when the power is turned off, the charging voltage of each pixel is discharged for a long time and about several seconds. There is a problem that an abnormal screen is generated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to turn on the thin film transistor of each pixel for a very short period of time in a state in which the data voltage supply is interrupted during power-off, thereby rapidly increasing the charging voltage of each pixel. The present invention provides a liquid crystal display device and a driving method thereof that can be discharged easily.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a method of driving the same, which can greatly shorten the time required for discharging the charging voltage by quickly discharging the charging voltage of the pixels at power off.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of preventing abnormal generation of a screen due to a discharging delay by greatly shortening the time required for discharging the charging voltage of each pixel.

The present invention for achieving the above object, the voltage detection unit for detecting the level of the power supply voltage supplied; A timing controller for controlling generation of charging scan pulses or interrupting supply of data voltages according to the power supply voltage level detected by the voltage detector; And a gate driver for supplying the charging scan pulse or generating the charging scan pulse under the control of the timing controller.

The voltage detector generates an enable signal and supplies the enable signal to the timing controller when the detected power supply voltage level is greater than a predetermined reference voltage level.

When the enable signal is input, the timing controller determines that the power is on, and supplies a charging gate clock used to supply the charging scan pulse to the gate driver.

The charging gate clock is characterized in that one horizontal period.

The gate driver may receive the charging gate clock and generate the charging scan pulse.

The voltage detector generates a disable signal and supplies the disable signal to the timing controller when the detected power supply voltage level is smaller than a predetermined reference voltage level.

When the disable signal is input, the timing controller determines that the power is off, and supplies a discharging gate clock used to supply the discharging scan pulse to the gate driver.

The discharging gate clock is characterized in that it is 1 ~ 2㎲ period.

The gate driver may receive the discharge gate clock and generate the discharge scan pulse.

A method of driving a liquid crystal display device having a liquid crystal display panel having a plurality of gate lines and a plurality of data lines, the method comprising: detecting a level of a power supply voltage supplied; And sequentially charging charging pulses to the plurality of gate lines or blocking data voltages supplied to the plurality of data lines according to the detected power supply voltage level. Supplying the gate lines sequentially.

The detecting step may include detecting the power supply voltage; Comparing the detected power supply voltage level with a predetermined reference voltage level; Generating an enable signal when the detected power supply voltage level is greater than the predetermined reference voltage level as a result of the comparison; And generating a disable signal when the detected power supply voltage level is less than the predetermined reference voltage level as a result of the comparison.

The supplying step may include generating a charging gate clock in response to the enable signal; And sequentially supplying the charging scan pulse to the plurality of gate lines according to the charging gate clock. Alternatively, the supplying step may include generating a discharge gate clock in response to the disable signal; And sequentially supplying the discharging scan pulses to the plurality of gate lines according to the discharging gate clock.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention. However, in the liquid crystal display device 200 of the present invention, the gamma reference voltage generator 140, the backlight assembly 150, the inverter 160, and the common voltage are the same as the liquid crystal display device 100 shown in FIG. 2. Although the generator 170 and the gate driving voltage generator 180 are provided, these components are not shown in FIG. 3 for convenience of description.

Referring to FIG. 3, in the liquid crystal display 200 of the present invention, the data lines DL1 to DLm and the gate lines GL1 to GLn cross each other and drive the liquid crystal cell Clc at an intersection thereof. The enable signal EN or the disable signal DEN according to the detected power supply voltage level by detecting the level of the power supply voltage VCC supplied from the system and the liquid crystal display panel 110 having the TFTs formed therein. Controlling the generation of charging scan pulses or blocking the supply of data voltages in response to the enable signal from the voltage detection unit 210 and the enable signal from the voltage detection unit 210. The timing controller 220 and the data driver 230 for converting digital data supplied from the timing controller 220 into analog data voltages and supplying them to the data lines DL1 to DLm, and the timing controller 220. The charging gate pulse is input to supply charging scan pulses to the gate lines GL1 to GLn, or the charging gate clock is input from the timing controller 220 to receive the charging gate clock. The gate driver 240 sequentially supplies the scanning pulses to the gate lines GL1 to GLn.

The voltage detector 210 detects the level of the power supply voltage VCC supplied from the system, compares the detected power supply voltage level with a predetermined reference voltage level, and according to the comparison result, the enable signal EN or the disable signal DEN. Will occur). Here, the predetermined reference voltage may be set to 2V.

As a result of the comparison, if the detected power supply voltage level is greater than the predetermined reference voltage level, as shown in FIG. 4, the voltage detector 210 generates an enable signal EN instructing supply of the charging gate clock CCLK. Supply to the timing controller 220.

As a result of the comparison, if the detected power supply voltage level is smaller than the predetermined reference voltage level, as illustrated in FIG. 5, the voltage detector 210 may provide the disable signal DEN instructing the supply of the discharging gate clock DCLK. Is generated and supplied to the timing controller 220.

The timing controller 220 supplies the digital video data RGB supplied from the system to the data driver 230, and also the horizontal / vertical synchronization signals H and V from the system in accordance with the clock signal CLK from the system. The data driving control signal DDC and the gate driving control signal GDC may be generated and supplied to the data driver 230 and the gate driver 240, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

As shown in FIG. 4, when the enable signal EN is input from the voltage detector 210, the timing controller 220 determines that the power is on, and uses the charging gate clock CCLK used to supply the scanning scan pulse. Are sequentially supplied to the gate driver 240. At the same time, the timing controller 220 supplies digital data input from the system to the data driver 230. Here, the charging gate clock CCLK is characterized in that it is one horizontal period (about 20 ms) or two horizontal periods.

In addition, as shown in FIG. 5, when the disable signal DEN is input from the voltage detector 210, the timing controller 220 determines that the power is off, and thus the discharge gate clock used for supplying the scan pulse for discharge ( DCLK) is sequentially supplied to the gate driver 240. At the same time, the timing controller 220 cuts off the data supply to the data driver 230. Here, the discharging gate clock DCLK is characterized by a period of 1 to 2 ms.

The data driver 230 supplies data to the data lines DL1 to DLm in response to the data driving control signal DDC supplied from the timing controller 220, and digital video data supplied from the timing controller 220. After sampling and latching the RGB, the liquid crystal cell Clc of the liquid crystal display panel 110 is converted into an analog data voltage capable of expressing gray scale based on the gamma reference voltage supplied from the gamma reference voltage generator 140. Supply to the data lines DL1 to DLm. Of course, the data driver 230 stops the supply of the analog data voltage when the digital data is not supplied from the timing controller 220.

As shown in FIG. 4, the gate driver 240 sequentially generates charging scan pulses using the charging gate clock CCLK supplied sequentially from the timing controller 220, thereby providing the gate lines GL1 to GLn. To feed.

As shown in FIG. 5, the gate driver 240 sequentially generates the scan pulses for discharging using the discharging gate clock DCLK sequentially supplied from the timing controller 220, and thus the gate lines GL1 to GLn. ) To feed them. At this time, since the data voltages are not supplied to the data lines DL1 to DLm as described above, the voltages of the data lines DL1 to DLm are lower than the charging voltage of each pixel, which causes the charging voltage of each pixel. The discharge pulses are discharged very quickly through the thin film transistor of each pixel turned on.

As described above, according to the present invention, the thin film transistor of each pixel is turned on for a very short period in a state in which the data voltage supply is interrupted at the time of power-off, thereby quickly discharging the charging voltage of each pixel. This greatly reduces the time required, thereby preventing the occurrence of abnormal screens due to discharging delays.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (15)

A voltage detector for detecting a level of a supplied power supply voltage; A timing controller for controlling generation of charging scan pulses or interrupting supply of data voltages according to the power supply voltage level detected by the voltage detector; And A gate driver for supplying the charging scan pulse or generating the charging scan pulse under the control of the timing controller Liquid crystal display comprising a. The method of claim 1, And the voltage detector generates an enable signal and supplies the enable signal to the timing controller when the detected power supply voltage level is greater than a predetermined reference voltage level. The method of claim 2, And the timing controller determines power-on when the enable signal is input, and supplies a charging gate clock used to supply the charging scan pulse to the gate driver. The method of claim 3, wherein And the charging gate clock is one horizontal period. The method of claim 3, wherein And the gate driver receives the charging gate clock to generate the charging scan pulse. The method of claim 1, And the voltage detector generates a disable signal and supplies the disable signal to the timing controller when the detected power supply voltage level is smaller than a predetermined reference voltage level. The method of claim 6, And the timing controller determines that the power is off when the disable signal is input, and supplies a discharging gate clock to the gate driver for supplying the discharging scan pulse. The method of claim 7, wherein And said discharging gate clock has a period of 1 to 2 ms. The method of claim 7, wherein And the gate driver is configured to receive the discharge gate clock and generate the discharge scan pulse. A driving method of a liquid crystal display device having a liquid crystal display panel having a plurality of gate lines and a plurality of data lines formed therein, Detecting a level of a supplied power supply voltage; And According to the detected power supply voltage level, charging scan pulses are sequentially supplied to the plurality of gate lines or data voltages supplied to the plurality of data lines are blocked, and discharge scan pulses are simultaneously supplied to the plurality of gate lines. Feeding the lines sequentially Method of driving a liquid crystal display comprising a. The method of claim 10, The detecting step, Detecting the power supply voltage; Comparing the detected power supply voltage level with a predetermined reference voltage level; Generating an enable signal when the detected power supply voltage level is greater than the predetermined reference voltage level as a result of the comparison; And Generating a disable signal when the detected power supply voltage level is less than the predetermined reference voltage level as a result of the comparison; Method of driving a liquid crystal display comprising a. The method of claim 11, The supply step, Generating a charging gate clock in response to the enable signal; And Sequentially supplying the charging scan pulse to the plurality of gate lines according to the charging gate clock Method of driving a liquid crystal display comprising a. In claim 12 And the charging gate clock is one horizontal period. The method of claim 11, The supplying step, Generating a discharge gate clock in response to the disable signal; And Sequentially supplying the discharging scan pulses to the plurality of gate lines according to the discharging gate clock Method of driving a liquid crystal display comprising a. The method of claim 14, And said discharging gate clock has a period of 1 to 2 ms.

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