KR20080024368A - Circuit of redundancy address for nand flash memory - Google Patents

Abstract

A redundancy address fuse circuit of a NAND flash memory is provided to reduce the size of the circuit by reducing the number of NMOS transistors constituted in a redundancy address circuit of the NAND flash memory. A redundancy address fuse block(52) stores a column address of a defective cell. A guard fuse block(51) enables the redundancy address fuse block according to the cutting of a guard fuse, and provides the route of a current discharge path generated by the redundancy address fuse block to output repair address information. The guard fuse block includes the guard fuse, an inverter, a first transistor and a second transistor. The first transistor provides the route of the current discharge path generated by the redundancy address fuse block. The second transistor has a gate connected to a first node and a drain and a source connected to a ground line in common.

Description

Redundancy address fuse circuit of NAND flash memory

1 is a block diagram showing the structure of a conventional NAND flash memory.

FIG. 2 is a circuit diagram illustrating a redundancy address fuse circuit of the redundancy controller of FIG. 1.

3 is a circuit diagram illustrating a redundancy address fuse circuit of a NAND flash memory according to an exemplary embodiment of the present invention.

* Brief description of the main parts of the drawings *

100: guard fuse block 200: address fuse block

The present invention relates to a redundancy address fuse circuit of a NAND flash memory. In particular, the present invention relates to a redundancy address fuse circuit of a NAND flash memory capable of reducing the chip size by reducing the number of elements constituting the redundancy address fuse circuit used for a repair operation. It is about.

In general, a NAND flash memory device adds a redundancy cell to a main memory cell in order to improve yield. A repair scheme is used to replace the redundancy cell.

1 is a block diagram showing the structure of a conventional NAND flash memory.

Referring to FIG. 1, a NAND flash memory includes a memory cell array 10, a redundancy cell array 20, a page buffer and a column decoder 30, a redundancy decoder 40, and a redundancy controller.

The memory cell array 10 may include a plurality of memory cells (not shown) to store data, and the redundancy cell array 20 may replace the defective cell in the memory cell array 10. It consists of a cell.

The page buffer and the column decoder 30 program, verify, read, and erase data in the memory cell array 10 according to the input address, and the redundancy recorder 40 repairs the input address. In this case, the address of the redundancy cell array 20 connected to the corresponding address may be connected to operate.

The redundancy controller 50 determines whether the input address is the address of the repaired cell, and informs the page buffer and column decoder 30 or the redundancy decoder 40 of this.

The redundancy control unit 50 includes a plurality of redundancy address fuse circuits (not shown) which employ the fuse element to program the repaired address information. Therefore, when the input address is a repaired address, the redundant fuse circuit outputs repair address information.

The redundancy control unit uses a method of replacing all memory cells of the same row or column with redundancy cells for a single memory cell failure due to the characteristics of the NAND cell. The redundancy control unit 50 replaces the redundancy cell array with respect to the column. Replace.

The redundancy address fuse circuit of the redundancy control unit 50 is configured as follows.

FIG. 2 is a circuit diagram illustrating a redundancy address fuse circuit of the redundancy controller of FIG. 1.

Referring to FIG. 2, the redundancy address fuse circuit includes a discharge pass path providing a guard fuse block 51, a redundancy address fuse block 52, and a current discharge pass of the redundancy address fuse block 52. It consists of a control unit 53.

The guard fuse block 51 is also referred to as a master fuse block and performs a function of enabling the redundancy address fuse block 52. The guard fuse block 51 includes a guard fuse GF, first to third inverters IN1 to IN3, an NMOS transistor N1, and an NMOS capacitor N2.

The redundancy address fuse block 52 includes the first to eighth fuses AF1 to AF8 configured to double the column address, the third to tenth NMOS transistors N3 to N10, the PMOS transistor P1, and the fourth and It consists of 5th inverters IN4 and IN5. The discharge path controller 53 is configured of the eleventh NMOS transistor N11 to provide a path of the current discharge path of the redundancy address fuse block 52.

2 shows a redundancy address fuse circuit in the case of four column addresses (<3: 0>).

In order to repair a defective cell in a NAND flash memory device, a total of eight fuses AF1 to AF8 are required, including four redundancy line addresses (RLA) <3: 0> and four RLAb <3: 0>. The redundancy address fuse block 52 stores address information of a defective cell through fuse cutting.

In FIG. 2, when a defect occurs in a memory cell having an address RLA <3: 0> of '0101' and a repair is to be performed, the first fuse AF1, the fourth fuse AF4, and the fifth The fuse AF5 and the eighth fuse AF8 are cut to store the defective cell address.

Next, when the guard fuse GF is cut and the power is turned off to the redundancy address fuse circuit and then turned back on, the node A becomes low in the guard fuse block 51, so that the node B becomes high. ), The eleventh NMOS transistor N11 of the discharge path providing unit 53 is turned on to provide the path of the current discharge path to the redundancy address fuse block 52.

The redundancy address fuse block 52 forms a current discharge path from the node C in the direction of the arrow P, and current flows. At this time, the repair signal REPb becomes low due to the current of the node C, and sends out information that the corresponding address is the repaired address.

By the above process, the corresponding address is accessed toward the repair cell. In this way, the redundancy circuit is configured to receive the information of the column-address to be repaired, and to blow the fuse corresponding to the column address to output the repaired information.

In general, redundant address fuse circuits occupy an insurmountable area on a memory chip. And since NAND flash memory uses 256 or 512 of these circuits, it is important to reduce the size of the redundancy address circuit in order to reduce the chip size in the future.

Accordingly, an aspect of the present invention is to provide a redundancy address circuit of a NAND flash memory capable of reducing the size of a circuit by reducing the number of NMOS transistors configured in the redundancy address circuit of the NAND flash memory.

Redundant address circuit of the NAND flash memory according to an aspect of the present invention for achieving the above technical problem,

A redundancy address fuse block for storing a column address of a defective cell; And

And a guard fuse block for enabling the redundancy address fuse block according to whether a guard fuse is cut and providing a path of a current discharge path generated by the redundancy address fuse block to output repair address information.

The guard fuse block includes: a guard fuse connected between a power supply voltage and a first node connected to a current discharge path of the redundancy circuit; An inverter having the first node as an input node; A first transistor connected between the first node and a ground voltage and having a gate connected to an output node of the inverter, the first transistor providing a path of a current discharge path generated by the redundancy address fuse block; And a second transistor having a gate connected to the first node and a drain and a source connected to a ground line in common.

The address fuse block may further include: a first switching device unit including a plurality of switching units connected in series between a second node and a third node connected to a power supply voltage and operated by a plurality of address signals, respectively; And a second switching unit including a plurality of switching units connected in series between the second node and the fourth node side by side and respectively operated by inverted signals of the plurality of address signals.

The lowermost switching unit operated by the lowest address signal in the first and second switching units may be connected to the first node of the guard fuse block to generate a current discharge path.

The switching unit may include a transistor operated by each of the plurality of addresses and an inverted signal corresponding thereto; And an address fuse connected in series with the transistor.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 is a circuit diagram illustrating a redundancy address circuit of a NAND flash memory according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the redundancy address fuse circuit includes a guard fuse block 100 and a redundancy address fuse block 200.

The guard fuse block 100, also referred to as a master fuse block, performs a function of enabling the redundancy address fuse block 200. The guard fuse block 100 includes a guard fuse 101, a first inverter 102, and first and second NMOS transistors 103 and 104.

The redundancy address fuse block 200 includes the first to eighth fuses 212 to 219 configured to double the column address, the third to tenth NMOS transistors 202 to 209, the PMOS transistors 201, and the fourth and the like. And fifth inverters 210 and 211.

3 shows a redundancy address fuse circuit in the case of four column addresses (<3: 0>).

To repair a defective cell in a NAND flash memory device, eight redundancy line addresses (RLAs) <3: 0> and four RLAb <3: 0> are required, for a total of eight fuses (212-219). The redundancy address fuse block 200 stores address information of a defective cell through fuse cutting.

In the case of FIG. 3, when a defect occurs in a memory cell having an address RLA <3: 0> of '0101' and a repair is to be performed, the first fuse 212, the fourth fuse 215, and the fifth fuse are to be repaired. 216 and the eighth fuse 219 are cut to store the defective cell address.

Then, when the power is turned off to the redundancy address fuse circuit and then turned on again, the node 1 and the node 2 become low in the guard fuse block 100, and the first inverter 102 makes a first operation. 2 NMOS transistor 104 is turned on. Accordingly, the node 1-node 2 and the node 3 are connected, and the current discharge pass along the first to eighth fuses 212 to 219 in the direction of the currents I1 and I2 at the node 4. Is generated.

The current discharge pass causes the node 4 to go low level, and accordingly, the repair signal REPb goes low to emit information indicating that the address becomes a repair.

Meanwhile, the first and second NMOS transistors 103 and 104 connected to the guard fuse 101 may prevent the guard fuse 101 from being floated in the cut state and maintain the node 1 at a low level. It is to provide a function of the current discharge pass by the first to eighth fuses 212 to 219.

However, as described in the embodiment of the present invention, the second transistor (which is connected to the guard fuse 101) has a function of the NMOS transistor that opens and closes the current charge path that is connected to the first to eighth fuses 212 to 219. 104 allows the guard fuse 101 to prevent floating due to cutting and to provide a current discharge pass while maintaining node 1 at a low level, thereby reducing the elements of the NMOS transistors of the redundancy circuit. Do the same for the original function.

In addition, the number of NMOS transistors is reduced, which reduces the size of the redundancy circuit.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the redundancy address fuse circuit of the NAND flash memory according to the present invention reduces the number of NMOS transistors for turning on / off the operation of the redundancy address fuse block and replaces the functions with the NMOS transistors of the guard fuse block. It is possible to reduce the size of the redundancy address fuse circuit by performing the conventional operation while reducing the number of times.

Claims (5)

A redundancy address fuse block for storing a column address of a defective cell; And The guard fuse block enables the redundant address fuse block according to whether a guard fuse is cut, and provides a path of a current discharge path generated by the redundant address fuse block to output repair address information. The redundancy address fuse circuit of the NAND flash memory. The method of claim 1, The guard fuse block, A guard fuse connected between a power supply voltage and a first node connected to the current discharge path of the redundancy address fuse block; An inverter having the first node as an input node; A first transistor connected between the first node and a ground voltage and having a gate connected to an output node of the inverter, the first transistor providing a path of a current discharge path generated by the redundancy address fuse block; And a second transistor having a gate connected to the first node and a drain and a source connected to a ground line in common. The method of claim 2, And the first and second transistors are NMOS transistors. The method according to claim 1 or 2, The address fuse block, A first switching element unit including a plurality of switching units connected in series between a second node and a third node connected to a power supply voltage and operated by a plurality of address signals, respectively; And a second switching unit including a plurality of switching units connected in series between the second node and the fourth node side by side and respectively operated by inverted signals of the plurality of address signals. Redundancy address fuse of the NAND flash memory, characterized in that the lowest switching unit operating by the lowest address signal in the first and second switching unit is connected to the first node of the guard fuse block to generate a current discharge path. Circuit. The method of claim 4, wherein The switching unit Transistors each operated by the plurality of addresses and corresponding inverted signals; And an address fuse serially connected to the transistor.

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