KR20080024318A - Plasma display device and driving method thereof - Google Patents

Abstract

A plasma display apparatus and a driving method thereof are provided to reduce the power loss of address by measuring the data variation amount of address for each blocks. A plasma display apparatus includes a plasma display panel(100), a controller(200), and plural address drivers(300). The plasma display panel includes plural address electrodes divided into plural groups. The controller compares the total data variation amount of the address electrodes based on first image signal data with a threshold value and generates compensated second image signal data according to the comparison result. The address drivers, which are connected to the address electrodes, apply address discharge pulses. Address drivers, connected to address electrodes of the same group among the address drivers, are implemented in the same IC(Integrated Circuit).

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 is a schematic plan view of a plasma display device according to an exemplary embodiment of the present invention.

2 is a schematic view of a portion of a plasma display device according to an exemplary embodiment of the present invention.

3 is a diagram illustrating an address electrode driver according to an exemplary embodiment of the present invention.

4 is a schematic block diagram of a controller of a plasma display device for reducing address power consumption according to an exemplary embodiment of the present invention.

5 is a block diagram showing an internal configuration of an address APC level determination unit according to an embodiment of the present invention.

6 is a diagram illustrating an operation of an address APC level determiner according to an exemplary embodiment of the present invention.

The present invention relates to a plasma display device and a driving method thereof, and more particularly, to a plasma display device for controlling an address power consumption and a driving method thereof.

A plasma display device is a flat display device that displays characters or images by using plasma generated by gas discharge. The display panel has a matrix of tens to millions or more of discharge cells (hereinafter referred to as "cells") according to its size. It is arranged in the form.

In general, the plasma display device divides one frame into a plurality of subfields having respective weights, and time-division controls them to implement gray scale. Each subfield consists of an address period and a sustain period. The address period is a period for distinguishing cells to be turned on from cells not to be turned on among the plurality of cells through address discharge. That is, in the address period, scan pulses are sequentially applied to the plurality of scan electrodes, and address pulses are applied to the address electrodes. At this time, address discharge occurs in a cell to which a scan pulse and an address pulse are simultaneously applied. In the sustain period, sustain discharge occurs as many times as the number corresponding to the weight of the corresponding subfield in the cell to be turned on to display an image.

Here, when each operation of each subfield is performed in the above manner, the discharge space between the scan electrode and the sustain electrode, the surface on which the address electrode is formed and the surface on which the scan and sustain electrode are formed act as a capacitive load. There is capacitance in the panel. Therefore, in order to apply the waveform for addressing, a lot of reactive power for charge injection that generates a predetermined voltage in capacitance other than power for address discharge is required. At this time, when the number of switching of the address electrodes is large, address power is consumed even more.

Therefore, when the change amount of the address data is large, a method of lowering the gain value of the subfield data or reducing the number of sustain discharge pulses is used to reduce the address power consumption. However, when the amount of change in the address data in a particular portion of the screen displayed by the plasma display panel is large, there is a problem that distortion occurs in the gradation representation of the entire screen when the conventional method is used for the entire screen.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above-described problems of the related art, and to provide a plasma display device and a method of driving the plasma display device for controlling address power consumption.

According to one aspect of the present invention for achieving the above object, there is provided a plasma display device. The plasma display device includes a plasma display panel including a plurality of address electrodes divided into a plurality of groups; A control unit for comparing the total of the on / off data change amounts of the address electrodes included in each group obtained from the first image signal data of one frame to be input with a threshold, and generating second image signal data corrected according to the result; ; And a plurality of address driving circuits connected to the plurality of address electrodes to apply an address discharge pulse. In this case, the address driving circuits connected to address electrodes included in the same group among the plurality of address driving circuits are connected in the same integrated circuit form.

According to another aspect of the present invention, there is provided a driving method of a plasma display device which corrects and displays an input first video signal, divides one frame into a plurality of subfields, and displays a gray scale according to the combination of the subfields. do. The driving method includes dividing a plurality of address electrodes into a plurality of groups; Receiving a value of an address automatic power level corresponding to the first image signal data of one input frame and generating a first gain value corresponding thereto; Comparing a total of on / off data change amounts of address electrodes included in each group obtained from the first image signal data with a threshold value; Applying a second gain value smaller than the first gain value to a plurality of address electrodes included in a group whose sum of on / off data change amounts of the address electrodes is larger than the threshold value; Applying the first gain value to a plurality of address electrodes included in a group whose sum of on / off data change amounts of the address electrodes is equal to or less than the threshold value; And outputting a corrected second image signal by displaying the first gain value or the second gain value corresponding to the first image signal, and displaying the corrected second image signal on the plasma display device. In this case, the address driving circuits connected to the plurality of address electrodes included in the same group are connected in the same integrated circuit form.

According to still another aspect of the present invention, there is provided a method of driving a plasma display device which corrects and displays an input video signal, divides one frame into a plurality of subfields, and displays a gray scale according to the combination of the subfields. . The driving method includes dividing a plurality of address electrodes into a plurality of groups; Comparing a total of on / off data change amounts of address electrodes included in each group obtained from the first image signal data with a threshold value; And all the address data of the subfield having the smallest gray scale weight among the plurality of subfields are the same for the plurality of address electrodes included in the group whose sum of on / off data change amounts of the address electrodes is larger than the threshold value. Steps. In this case, the address driving circuits connected to the plurality of address electrodes included in the same group are connected in the same integrated circuit form.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A plasma display device and a method of driving the plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a schematic plan view of a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a scan electrode driver 400, and a sustain electrode driver 500. ).

The plasma display panel 100 includes a plurality of address electrodes A1 to Am extending in the vertical direction, and a plurality of sustain electrodes X1 to Xn and scan electrodes Y1 to Yn extending in pairs in the horizontal direction. Include. The sustain electrodes X1 to Xn are formed corresponding to the scan electrodes Y1 to Yn. At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms a discharge cell. The structure of the plasma display panel 100 is an example, and a panel having another structure to which the driving waveform described below may be applied may also be applied to the present invention.

The controller 200 receives an image signal from the outside and outputs an address electrode driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. The controller 200 controls to drive a frame by dividing a frame into a plurality of subfields, and the gray level is expressed by a combination of weights of the subfields.

The address electrode driver 300 receives an address electrode driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The scan electrode driver 400 receives a scan electrode driving control signal from the controller 200 and applies a driving voltage to the scan electrode.

The sustain electrode driver 500 receives the sustain electrode driving control signal from the controller 200 and applies a driving voltage to the sustain electrode.

2 is a schematic view of a portion of a plasma display device according to an exemplary embodiment of the present invention. As shown in FIG. 2, a plurality of address electrodes included in the plasma display panel 100 are divided into n groups G1, G2,..., Gn to drive a plurality of addresses for address electrodes included in each group. The circuit 310 may be configured in the form of an integrated circuit.

That is, the plurality of address driving circuits 310 connected to the plurality of address electrodes corresponding to each group are integrated in each IC circuit 311 in the form of a chip on film (COF), and the IC circuit 311 is The power recovery capacitors C1, C2, ..., Cn are connected in sequence.

3 is a diagram illustrating an address electrode driver 300 according to an exemplary embodiment of the present invention.

In FIG. 3, only the address driving circuit 310 connected to one address electrode will be described for convenience.

Each address driving circuit 310 includes switches S1, S2, and S3. In FIG. 3, the switches S1, S2, and S3 may be formed of a field effect transistor, an insulated gate bipolar transistor, or the like, respectively. In this case, body diodes may be formed in the transistors. When a body diode is formed in the switch S3, the switch S3 may be formed of transistors connected in a back-to-back form to block a path caused by the body diode.

The switch S1 is connected between the Va power supply for supplying the address voltage Va and the address electrode of the panel capacitor Cp. The switch S2 is connected between a power supply (a ground end supplying a ground voltage in FIG. 2) supplying a voltage lower than the address voltage and an address electrode of the panel capacitor Cp.

On the other hand, when on data is applied to the address electrode. A signal for turning on the switch S1 is input to the control terminal of the switch S1, and when off data is applied, a signal for turning on the switch S2 is input to the control terminal of the switch S1. In addition, the switch S3 is connected between the address electrode of the panel capacitor Cp and the power recovery capacitor C1.

At least one capacitor C1 may be commonly connected to the plurality of address electrodes A1 to Am, and a separate capacitor C1 may be connected to each predetermined number of address electrodes. At this time, since the size of the capacitor C1 is larger than that of the panel capacitor Cp, when the switch S3 is turned on, the voltage change of the capacitor C1 due to the current charged or discharged in the panel capacitor Cp is small. Assume The capacitor C1 supplies a voltage between the voltage Va and 0V.

4 is a schematic block diagram of a controller 200 of a plasma display device for reducing address power consumption according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the control unit 200 of the plasma display device according to an exemplary embodiment of the present invention may include an inverse gamma correction unit 210, an error diffusion unit 220, an APC level determination unit 230, and a sustain discharge pulse allocation. A unit 240, a holding and scanning driving control section 250, an address APC level determining section 260 and an address data generating section 270 are included.

The inverse gamma correction unit 210 maps n-bit R, G, and B image input data, which are currently input image data, to an inverse gamma curve and corrects the m-bit (m≥n) image signal. In a typical plasma display device, n is 8 and m is 10 or 12.

In this case, the video signal input to the inverse gamma correction unit 210 is a digital signal. When an analog video signal is input to the plasma display device, the analog video signal may be converted into a digital video signal by an analog-to-digital converter (not shown). There is a need. The inverse gamma correction unit 210 may generate a lookup table (not shown) that stores data corresponding to an inverse gamma curve for mapping an image signal, or a logic circuit for generating data corresponding to an inverse gamma curve by a logical operation. (Not shown).

The error diffusion unit 220 may inversely gamma correct the inverse gamma correction unit 210 and error-diffuse the lower m-n bit image of the expanded bit m image to surrounding pixels. Error diffusion is a method of displaying an image of a lower bit by separating an image of a lower bit to be diffused into adjacent pixels and a detailed description thereof is described in Korean Patent Laid-Open Publication No. 2002-0014766.

The APC (Automatic Power Control) level determiner 230 detects the load rate using the image data output from the error diffusion unit 220, calculates the APC level according to the detected load rate, and calculates the calculated APC. The number of sustain discharge pulses corresponding to the level is calculated and output.

In this case, the APC level means the amount of power consumed when driving one frame in driving the plasma display device, and the APC level determiner 230 determines the number of sustain discharge pulses according to the size of the APC level. Control the power consumption by adjusting.

The sustain discharge pulse allocator 240 allocates sustain discharge pulses to each subfield by using the sustain discharge pulse number information transmitted from the APC level determiner 230.

The sustain / scan drive control unit 250 generates a control signal corresponding to the number of sustain discharge pulses output from the sustain discharge pulse allocating unit 240 and outputs the control signal to the sustain / scan driver 300. In this case, the sustain discharge pulse allocating unit 240 and the sustain and scan driving control unit 250 have been described separately, but the two may be simultaneously implemented in one block.

The address APC level determiner 260 determines whether the address data of one frame is data that consumes a lot of address power in a specific portion of the screen displayed by the plasma display panel 100 from the output data of the inverse gamma correction unit 210. To judge. In this case, in the case of a block that consumes a large amount of address power, a control signal for turning on or off both of a data gain value for resetting address data and an address data value of the lowest subfield in order to control power consumption. The address APC flag is output to the address data generation unit 270.

5 to 6, when the amount of change in address data is large in a specific portion of the screen displayed by the plasma display panel 100, the address power consumption is reduced for the specific portion. The operation of the address APC level determination unit 260 will be described in detail.

First, a plurality of address electrodes forming the plasma display panel 100 are divided into blocks, and the controller 200 measures an amount of change in address data for each block. In this case, as shown in FIG. 2, each IC circuit 311 corresponding to each of the capacitors C1 to Cn may be designated as one block, and the plurality of IC circuits 311 may be designated as one block.

5 is a block diagram illustrating an internal configuration of the address APC level determiner 260 according to an embodiment of the present invention.

As shown in FIG. 5, the address APC level determiner 260 according to an exemplary embodiment of the present invention includes a line memory 261, a subfield data difference adder 262, a gain storage unit 263, and a gain determiner ( 264 and the mode determination unit 265.

The subfield data difference adder 262 of the address APC level determiner 260 converts the input video signal into on / off data for each subfield, that is, the data in the column direction using data converted into subfield data. The difference between subfield data between adjacent upper and lower lines (that is, a row line) is added.

That is, by comparing the on / off data of the previous line stored in the line memory unit 261 and the on / off data of the currently input line in the same column direction, the difference between the subfield data is obtained and summed.

The subfield data difference adder 262 calculates, for each block, the difference between the subfield data values of the adjacent upper and lower lines, that is, the row lines, from the video signals converted into on / off data for each subfield in the line memory unit 261. The sums are added to all subfields of one frame with respect to the values of the summed subfields.

That is, the change in the switching state that generates a large amount of address power consumption occurs when one of the discharge cells adjacent to each other in the column direction is on and the other discharge cell is off, so that the subfield data difference adder 262 is used. As shown in Equation 1, the total sum of the on / off data of two discharge cells adjacent in the column direction may be calculated as a subfield.

Here, R _ij , G _ij , and B _ij are on / off data of R (red), G (green), and B (blue) discharge cells of i rows and j columns, respectively. At this time, the subfield data difference adding unit 262 obtains the value of each subfield by using Equation 1, and adds the values of each subfield to all subfields forming one frame.

Accordingly, the subfield data difference adder 262 compares the total value of the on / off data for the address electrodes included in each block with a predetermined threshold and compares the result with the gain determiner 264 and the mode determiner. Output to (265).

The gain determiner 264 multiplies the gain value corresponding to the sum obtained by the subfield data difference adder 262 when the sum obtained by the subfield data difference adder 262 is equal to or greater than the threshold value.

At this time, the gain determination unit 264 determines the final gain value by referring to the lookup table stored in the gain bottom part 263.

The gain value multiplied by the gain determiner 264 is in inverse proportion to the total sum of the subfield data differences, and is between 0 and 1. The large sum of the differences means that the address power consumption is large. Therefore, the gain value between 0 and 1 is multiplied to lower the gray level value represented by the corresponding block.

On the other hand, in the case of a block in which the sum of the subfield data differences is smaller than the threshold value, the gain value is 1, and the gradation value represented by the corresponding block does not change.

Therefore, in the case of a block in which the sum of the subfield data differences is smaller than the threshold value, the gain value stored in the gain storage unit 263 is used as it is.

This gain value can also be set through experimentation and stored in the form of a lookup table. Such a gain value may be changed in a range that does not deform the original video signal as necessary. In addition, the threshold represents a value corresponding to the sum of the subfield data differences corresponding to the address electrodes corresponding to the respective blocks for the case where a large amount of address power consumption occurs based on experimental data.

Meanwhile, the mode determining unit 265 determines whether to output the address APC flag signal of the subfield having the smallest gray scale weight by using the sum of the subfield data differences of the respective blocks obtained by the subfield data difference adding unit 262. do.

That is, when the sum obtained by the subfield data difference adder 262 is a block having a threshold value or more, it is determined that a large amount of address power is consumed, and thus the address data of the subfield having the smallest gray scale weight is turned on the same. Alternatively, address power consumption may be reduced by generating and outputting an address APC flag signal to be turned off.

In the case of a block below the threshold value, it is determined that the address power consumption is low and does not generate an address APC flag signal.

The address data generator 270 outputs the correction data by multiplying the image signal by the data gain value output from the address APC level determiner 260. Subfield data corresponding to the correction data is generated, the subfield data is rearranged into address data for driving the plasma display device, and an address control signal for controlling the address electrode driver 300 is generated to generate the address driver 300. Will output In addition, when the address APC flag signal is input from the mode determining unit 265 of the address data generating unit 260, the subfield data is generated by recalibrating the data so as to be on or off in the same subfield with the smallest gray scale weight. can do.

In addition, in the case of the block determined by the mode determining unit 265 to have high power consumption as in the above-described embodiment of the present invention, the address data generating unit 270 ensures that only the address data of the subfield having the lowest gray scale weight is the same. As described above, the lower few bits can be made the same so as not to affect the gradation.

6 is a diagram illustrating an operation of the address APC level determiner 260 according to an exemplary embodiment of the present invention.

In this case, the address electrode forming the plasma display panel 100 is divided into a plurality of blocks so that the APC level determiner 260 controls the respective blocks.

As illustrated in FIG. 6, subfield data allocated to one frame for each block is generated using the input image data (S210 to S220).

Then, the difference between the subfield data that changes for one block for each frame is measured using the generated subfield data (S230).

That is, the APC level determiner 260 sequentially associates on / off data with address electrodes included in each block for one frame, and calculates the sum of the differences between two adjacent data among data corresponding to each address electrode. The total difference of subfield data of the plurality of address electrodes included in each block is summed up.

The sum obtained in this manner is added to a plurality of address electrodes to obtain a change amount of address data, and the comparison is made with a predetermined threshold value (S240).

In this case, when the total sum of the measured subfield data differences is greater than the threshold value, the subfield data of the corresponding block is corrected (S250).

That is, the gray level is lowered by multiplying the gray level to be expressed for one frame by a gain value between 0 and 1, and rearranges the subfield data accordingly. Alternatively, address power consumption is reduced by making the address data of the subfield having the low gray scale weight equal.

On the other hand, in the case of a block in which the total sum of the difference of the measured subfield data is smaller than the threshold value, the corresponding subfield data is kept as it is (S260). That is, the grayscale value to be expressed is maintained for one frame of the corresponding block.

As described above, according to the exemplary embodiment of the present invention, the address electrode is divided into a plurality of blocks, so that the image gray scale value is lowered only for a block in which the change amount of the address data is larger than the threshold value. Therefore, it is possible to reduce the consumption of the address power consumption and to minimize the distortion of the gradation representation of the entire screen.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, by dividing the address electrode into a plurality of blocks and measuring the change amount of address data for each block, it is possible to reduce the consumption of address power and to reduce distortion of the gradation representation of the entire screen.

Claims (12)

A plasma display panel including a plurality of address electrodes divided into a plurality of groups; A control unit for comparing the total of the on / off data change amounts of the address electrodes included in each group obtained from the first image signal data of one frame to be input with a threshold, and generating second image signal data corrected according to the result; ; And A plurality of address driving circuits connected to the plurality of address electrodes to apply an address discharge pulse; And an address driving circuit connected to address electrodes included in the same group among the plurality of address driving circuits is connected in the same integrated circuit form. The method of claim 1, The control unit, The first image is generated by generating a gain value corresponding to the sum of the on / off data change amounts for a plurality of address electrodes in which the sum of the on / off data change amounts of the address electrodes is included in a group larger than the threshold value. And generating the second image signal data by mapping signal data to the gain value. The method of claim 2, And the gain value decreases as the total sum of on / off data changes of the address electrode increases. The method of claim 3, And the gain value is greater than zero and less than one. The method of claim 2, And a gain value of 1 for a group in which the sum of on / off data change amounts of the address electrodes is equal to or less than the threshold value. The method of claim 1, The control unit, Plasma generating second video signal data so that the data of the subfield having the lowest weight is the same, corresponding to the plurality of address electrodes included in the group whose sum of on / off data change amounts of the address electrodes is larger than the threshold value. Display device. The method according to any one of claims 1 to 6, And an integrated circuit connected to the address electrodes included in the same group, corresponding to one power recovery capacitor. A driving method of a plasma display device which corrects and displays an input first video signal, divides one frame into a plurality of subfields, and displays a gray scale according to the combination of the subfields. Dividing the plurality of address electrodes into a plurality of groups; Receiving a value of an address automatic power level corresponding to the first image signal data of one input frame and generating a first gain value corresponding thereto; Comparing a total of on / off data change amounts of address electrodes included in each group obtained from the first image signal data with a threshold value; Applying a second gain value smaller than the first gain value to a plurality of address electrodes included in a group whose sum of on / off data change amounts of the address electrodes is larger than the threshold value; Applying the first gain value to a plurality of address electrodes included in a group whose sum of on / off data change amounts of the address electrodes is equal to or less than the threshold value; And Outputting the corrected second image signal by displaying the first gain value or the second gain value corresponding to the first image signal, and displaying the corrected second image signal on the plasma display device; An address driving circuit connected to the plurality of address electrodes included in the same group is connected in the same integrated circuit form. The method of claim 8, And the second gain value decreases as the sum of on / off data change amounts of the address electrodes increases. The method according to claim 8 or 9, And integrated circuits connected to the address electrodes included in the same group are connected to one power recovery capacitor. A driving method of a plasma display device which corrects and displays an input video signal, divides one frame into a plurality of subfields, and displays a gray scale according to the combination of the subfields. Dividing the plurality of address electrodes into a plurality of groups; Comparing a total of on / off data change amounts of address electrodes included in each group obtained from the first image signal data with a threshold value; And Equalizing all address data of a subfield having the smallest gray scale weight among the plurality of subfields with respect to a plurality of address electrodes whose total sum of on / off data change amounts of the address electrodes is included in a group larger than the threshold value; Wherein the address driving circuits connected to the plurality of address electrodes included in the same group are connected in the same integrated circuit form. The method of claim 11, And integrated circuits connected to the address electrodes included in the same group are connected to one power recovery capacitor.

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