KR20080023678A - Shift register circuit and display drive device - Google Patents

Abstract

There is disclosed a shift register circuit including plural stages of signal holding circuits (FF' n) which are cascade-connected to hold a signal based on a supplied input signal, to output an output signal (out) based on the held signal based on the supplied input signal, and to supply the output signal as an input signal to a subsequent stage, each of the plural stages of signal holding circuits including an output circuit which is supplied with two types of clock signals consisting of a first clock signal (ck) and a second clock signal (ck'), a timing of the second clock signal is delayed by a predetermined delay time with respect to a timing of applying the input signal (IN), which is supplied with a signal at a timing delayed by the delay time of the second clock signal from the timing of applying the input signal, and which outputs the output signal (OUT) at a timing responsive to the first clock signal. Also disclosed is a display drive device including the shift register circuit. ® KIPO & WIPO 2008

Description

SHIFT REGISTER CIRCUIT AND DISPLAY DRIVE DEVICE}

TECHNICAL FIELD The present invention relates to a shift register circuit and a display driver including such a circuit, and more particularly, to a shift register circuit and a display driver suitable for application to a drive circuit of a display element such as a liquid crystal display.

In recent years, information devices such as computers, mobile phones, or personal digital assistants and image processing-related devices such as digital video cameras, digital still cameras, or scanners have been widely used.

For example, an active matrix liquid crystal display device has the following configuration. First, display pixels (liquid crystal pixels) having pixel transistors such as thin film transistors are arranged in a matrix. For a display panel having scan lines connected to each display pixel in the row direction and data lines connected to the column direction, each scan line is sequentially selected by the gate driver, and predetermined for each data line by the source driver. By applying a signal voltage to the display pixels in the selected state according to the image information, a signal voltage of is controlled in accordance with the image information, thereby controlling the alignment state of the liquid crystal in each display pixel to display desired image information with a predetermined contrast. Here, a shift register circuit is provided in the gate driver as a configuration for sequentially outputting a scan signal for setting each scan line to a selected state. The source driver is also provided with a shift register circuit for setting the sampling and acquisition timing of the display data to be supplied.

FIG. 8A shows an example of a conventional shift register circuit configuration, and FIG. 8B is a timing chart for explaining the operation of the shift register of FIG. 8A. FIG. 9A is a circuit diagram showing the configuration of the signal holding section constituting the conventional shift register circuit, and FIG. 9B is a timing chart for explaining the operation of the signal holding section in FIG. 9A.

As shown in Fig. 8A, such a shift register circuit is constituted by a plurality of signal holding portions connected in series. The signal held in each signal holding section is output to the outside as an output signal OUTn, and is sequentially transmitted (shifted) to the signal holding section at the next stage.

)에 접속된다. 그리 고, 출력 신호(OUT)는 양 MOS 트랜지스터(T1n, T2n) 사이의 접속 접점으로부터 출력된다. Each signal holding part is composed of a set / reset flip-flop FFn and two MOS transistors T1n, T2n, n = 1, 2, 3, 4, ... as shown in Fig. 8A. It consists of a combination with a push / pull circuit. That is, the input signal IN is supplied to the flip / flop FFn set signal input terminal S, and the reset signal RST is supplied to the reset signal input terminal R. Further, the first and second MOS transistors T1n and T2n constituting the push / pull circuit are connected in series between a terminal to which a predetermined clock signal CK is applied and a power supply terminal to which a low potential power supply Vss is applied. Connected. The gate electrode of the first MOS transistor T1n is connected to the output terminal Q of the flip flop FFn, and the gate electrode of the second MOS transistor T2n is the inverted output terminal of the flip flop FFn (

) Is connected. Then, the output signal OUT is output from the connection contact between both MOS transistors T1n and T2n.

)에서는 로우 레벨의 신호가 출력된다. 플립 플랍(FFn)의 이러한 출력 신호 상태는, 상기 입력 신호(IN)가 로우 레벨로 반전되는 경우에도 유지된다.As shown in the timing chart of Fig. 8B, the signal holding portion having such a configuration is flip-flop FFn when the input signal IN supplied to the set signal input terminal S of the flip-flop FFn is high level. ) Is set; A high level signal is output from the output terminal Q, and an inverted output terminal (

), A low level signal is output. This output signal state of the flip flop FFn is maintained even when the input signal IN is inverted to a low level.

)에서는 하이 레벨의 신호가 출력된다.When the reset signal RST supplied to the reset signal input terminal R becomes high level, the signal is reset and a low level signal is output from the output terminal Q of the flip-flop FFn. Inverted output terminal

), A high level signal is output.

)에서는 로우 레벨의 신호가 출력되기 때문에, 푸쉬/풀 회로의 제 2 MOS 트랜지스터(T2n)는 오프 상태가 된다. 따라서, 하이 레벨 펄스 신호(CK)가 푸쉬/풀 회로에 인가되면, 출력 신호(OUT)는 하이레벨에서 획득된다. When the high level signal is output from the output terminal Q of the flip flop FFn according to the high level of the input signal IN, the high level voltage is applied to the gate of the first MOS transistor T1n of the push / pull circuit. The first MOS transistor T1n is applied to the electrode to operate. At this time, the inverting output terminal of the flip flop FFn (

), The low level signal is output, so that the second MOS transistor T2n of the push / pull circuit is turned off. Therefore, when the high level pulse signal CK is applied to the push / pull circuit, the output signal OUT is obtained at the high level.

)에서 각각 출력된다. 이러한 방식으로, 제 1 MOS 트랜지스터(T1n)는 오프 상태가 되고, 제 2 MOS 트랜지스터(T2n)는 온 상태가 된다. 따라서, 출력 신호(OUT)는 로우 레벨에서 획득된다.When the reset signal RST is at the high level, the low level signal and the high level signal are output terminal Q of the flip-flop FFn and the inverted output terminal (

Are printed respectively. In this manner, the first MOS transistor T1n is turned off and the second MOS transistor T2n is turned on. Thus, the output signal OUT is obtained at the low level.

As shown in Fig. 8A, the shift register circuit is connected in series with the signal holding portion having such a configuration, that is, the output signal OUTn is obtained from the push / pull circuit of the signal holding portion of the nth stage. It is supplied to the set terminal S of the flip flop FFn + 1 of the signal holding | maintenance part of the n + 1 stage. In addition, a connection is made to the reset terminal R of the flip-flop FFn of the signal holding portion of the nth stage so as to feed back the output signal of the output signal OUTn + 1 from the signal holding portion of the n + 1th stage. . Here, a predetermined start signal ST is supplied to the set terminal S of the flip flop FFn of the signal holding portion of the first stage. In addition, a reset signal is externally supplied to the reset terminal R of the flip-flop FFn of the signal holding portion of the final stage. Then, the first pulse signal CK1 is supplied to the odd-numbered signal holding portion, and the second pulse signal CK2 having the inverted waveform with the first pulse signal CK1 is pushed / Supplied to the pull circuit.

According to the shift register circuit having such a configuration, as shown in the timing chart of Fig. 8B, after the start signal ST is supplied, the high level output signals OUT1, OUT2, OUT3, OUT4, ... are sequentially Is transmitted (shifted), and is output in synchronization with the high level application timing of the pulse signals CK1 and CK2. Thus, for example, when scan signals based on such output signals OUT1, OUT2, OUT3, OUT4, ... are sequentially applied to the scan lines of the liquid crystal display device, display pixels connected to each scan line are terminated. A sequential selection operation can be executed in such a way that the selection state is up.

In this signal holding section, the first MOS transistor T1n of the push / pull circuit plays an important role in the output of the signal and the transfer to the next stage. That is, it is no exaggeration to say that the characteristics of the first MOS transistor T1n determine the performance of the entire shift register circuit.

On the other hand, by using a thin film transistor made of amorphous silicon (a-Si) or polysilicon (p-Si), a driving circuit such as a gate driver and a source driver of an active matrix liquid crystal display device is integrated on the display panel substrate (TFT substrate). In order to reduce the cost of the display device and to reduce the thickness of the display device, research and development have been conducted. In particular, amorphous silicon has an advantage in terms of cost reduction because it is formed at the same time when the TFTs constituting the pixel are formed.

However, when the signal holding portion having the above structure is composed of a transistor made of an amorphous silicon TFT or a polysilicon TFT, in such a MOS transistor, the bipolarity of the time integration value (or integrated voltage) of the signal level applied to the gate electrode and Since the threshold characteristics are very variable due to the heterogeneity of the negative electrode, the variation in the time that the on-current decreases for a transistor made of single crystal silicon is relatively large. Therefore, when a shift register circuit is constructed using such a MOS transistor, in particular, the characteristics of the first MOS transistor T1n of the push / pull circuit which perform an important function in outputting a signal and transferring to the next stage are determined by time. Deteriorates over time; The signal level of the output signal OUT decreases with time; The switching operation of each transistor is not performed correctly; And malfunction of the shift register circuit or deterioration of operating characteristics may occur.

In the shift register and the display drive device with the circuit according to the present invention, variations in the characteristics of the transistors responsible for signal output and transmission to the next stage are suppressed, thereby improving long-term reliability of the shift register circuit and the display drive device with such a circuit. can do.

In order to achieve the above advantages, the first shift register circuit of the present invention is connected in series: to store and hold a signal based on a supplied input signal, and to based on a signal stored and held based on a supplied input signal. And a plurality of signal holding circuits for outputting an output signal and supplying an output signal as an input signal of the next stage. Each of the plurality of stages of signal holding circuits is provided with two types of clock signals including: a first clock signal and a second clock signal having a timing delayed by a predetermined delay time with respect to the timing of applying the input signal; And an output circuit for supplying a signal at a timing delayed by a delay time of the second clock signal from a timing of applying the input signal, and outputting an output signal at a timing responsive to the first clock signal.

In order to achieve the above-mentioned advantages, the second shift register according to the present invention is: an input signal is supplied, connected in series, to output an output signal based on the input signal, and to supply the output signal as an input signal to the next stage. And a plurality of stages of signal holding circuits. Each of these multi-stage signal holding circuits includes two types of clocks including a first clock signal and a second clock signal having a timing delayed by a predetermined delay with respect to a timing of applying an input signal and a reset signal. A signal is supplied, and each of the plurality of stages of signal holding circuits: stores and holds an input signal at a timing delayed by a delay time in response to a second clock signal, and returns a signal stored and held in response to a reset signal. A latch circuit to be set and an output circuit for outputting a stored and held input signal as an output signal at a timing in response to the first clock signal.

In order to achieve the above-mentioned advantages, the third shift register according to the present invention is: an input signal is supplied, connected in series, to output an output signal based on the input signal, and to supply the output signal as an input signal to the next stage. And a plurality of stages of signal holding circuits. Each of these multi-stage signal holding circuits includes two types of clocks including a first clock signal and a second clock signal having a timing delayed by a predetermined delay with respect to a timing of applying an input signal and a reset signal. A signal is supplied, and each of the plurality of stages of signal holding circuits includes: a latch circuit for storing and holding an input signal and resetting the stored and held signal in response to a reset signal, and a second clock signal. And an output circuit for outputting a stored and held input signal as an output signal at a timing delayed by a delay time.

In order to achieve the above-described advantages, the display driving device according to the present invention is a display driving device for outputting a signal for displaying a desired image on a display panel having a plurality of display pixels in a matrix form, the display driving device receiving a signal. And a shift register circuit for sequentially outputting control signals for output. Such a shift register circuit is connected in series: to store and hold a signal based on a supplied input signal, to output an output signal based on a stored and held signal based on a supplied input signal, and to input an input signal of the next stage. And a plurality of stages of signal holding circuits for supplying output signals. Further, each of the plurality of stages of signal holding circuits is provided with two types of clock signals including: a first clock signal and a second clock signal having a timing delayed by a predetermined delay with respect to the timing of applying the input signal. And an output circuit for supplying a signal at a timing delayed by a predetermined delay time from the timing of applying the input signal, and outputting an output signal at a timing responsive to the first clock signal. A signal for displaying a desired image is output to a display panel having display pixels of.

1A is a block diagram showing an example of the configuration of one embodiment of a signal holding section constituting a shift register circuit according to the present invention;

1B is a timing chart for explaining the operation of the signal holding portion of FIG. 1A;

2 is a timing chart for explaining the relationship between the output clock signal and the driving clock signal supplied to the signal holding portion of the present embodiment;

3A is a block diagram of another embodiment of a signal holding section with a shift register circuit according to the present invention;

3B is a timing chart for explaining the operation of the signal holding portion of FIG. 3A;

4A is a circuit diagram showing a specific configuration example of the signal holding portion according to the present embodiment;

4B is a timing chart for explaining the operation of the signal holding portion in FIG. 4A;

5 is a circuit diagram showing an example of the configuration of a shift register using the signal holding unit according to the present embodiment;

FIG. 6 is a timing chart illustrating the operation of the shift register circuit of FIG. 5;

Fig. 7A is a simplified diagram showing the overall configuration of a liquid crystal display device to which a shift register circuit according to the present invention is applied;

7B is a diagram showing in detail the configuration of main parts of the liquid crystal display device according to this application example;

8A is a circuit diagram showing an example of a conventional shift register circuit configuration;

FIG. 8B is a timing chart for explaining the operation of the shift register of FIG. 8A;

Fig. 9A is a circuit diagram showing the construction of a signal holding portion constituting a conventional shift register circuit; And,

FIG. 9B is a timing chart for explaining the operation of the signal holding portion of FIG. 9A.

Now, with reference to the accompanying drawings, a shift register and a display drive device with a circuit according to the present invention will be described.

Various technical limitations which are preferable for carrying out the present invention have been applied to this embodiment, but the scope of the present invention is not limited to the following embodiments and illustrated examples.

FIG. 1A is a block diagram showing an example of the configuration of an embodiment of the signal holding section constituting the shift register circuit according to the present invention, and FIG. 1B is a timing chart for explaining the operation of the signal holding section of FIG. 1A.

FIG. 2 is a timing chart for explaining the relationship between the output clock signal CK (first clock signal) and the driving clock signal (second clock signal) supplied to the signal holding unit of the present embodiment.

4, the shift register circuit according to the present invention has a configuration in which a plurality of signal holding portions (signal holding circuits) FFP shown in FIG. 1A are connected in series. As in the conventional shift register circuit, a signal stored in the signal holding portion is output to the outside as an output signal, and sequentially transmitted (shifted) to the signal holding portion of the next stage as an input signal.

As shown in Fig. 1A, each signal holding section FFPn constituting the shift register circuit of the present invention includes a set / reset type flip flop FF'n, a two-input AND circuit 10, And a push / pull circuit composed of a first MOS transistor (first transistor) T1n and a second MOS transistor (second transistor) T2n (n = 1, 2, 3, 4, ...). It is composed. This push / pull circuit forms an output circuit in the present invention.

The input signal IN is supplied to one signal input terminal (first signal input terminal) of the AND circuit 10, and the driving clock signal (second clock signal) CK 'is supplied to the other signal input terminal (second signal). Input terminal), and the connection is made in such a manner that the output of the AND circuit 10 is supplied to the set signal input terminal S of the flip flop FF'n. Further, the connection is made in such a manner that the reset signal RST is supplied to the reset signal input terminal (second signal input terminal) of the flip flop FF'n.

)에 접속된다. MOS 트랜지스터(T1n, T2n) 사이의 접속 접점이 출력 단자로서 제공되어, 그 접점을 통해 출력 신호(OUT)가 출력된다.The first and second MOS transistors T1n and T2n constituting the push / pull circuit have an output clock signal (first clock) having a timing different from that of the driving clock signal (second clock signal) CK '. Signal) is connected in series between the terminal (first clock signal input terminal) to which the signal is applied and the power supply terminal to which the low potential power supply Vss is applied. The gate electrode of the first MOS transistor T1n is connected to the output terminal Q of the flip flop FF'n, and the gate electrode of the second MOS transistor T2n is the inverted output terminal of the flip flop FF'n. (

) Is connected. The connection contact between the MOS transistors T1n and T2n is provided as an output terminal, through which the output signal OUT is output.

The operation of the signal holding unit FFPn of this embodiment will now be described with reference to the timing chart of FIG. 1B.

)로부터 출력된다.First, the high level input signal IN is supplied to one side signal input terminal (first signal input terminal) of the AND circuit 10. At this time, when the driving clock signal (second clock signal) CK 'supplied to the other signal input terminal (second clock signal input terminal) of the AND circuit 10 is at a low level, the output of the AND circuit 10 is also reduced. Low level. In this manner, the low level signal is supplied to the set signal input terminal S of the flip flop FF'n, where the flip flop FF'n is not set. The low level signal is output from the output terminal Q, and the high level signal is inverted output terminal (

Is output from

)로부터 획득된다. 이러한 플립 플랍(FF'n)의 출력 단자(Q,

)로부터 출력된 신호의 상태는, 입력 신호(IN) 또는 구동용 클럭 신호(CK')가 로우 레벨로 반전되는 경우에도 유지된다. 이러한 방식으로, 하이 레벨 전압이 푸쉬/풀 회로의 제 1 MOS 트랜지스터(T1n)의 게이트 전극에 인가되고, 로우 레벨 전압이 제 2 MOS 트랜지스터(T2n)의 게이트 전극에 인가되어, 제 1 MOS 트랜지스터(T1n)가 온이 되고, 제 2 MOS 트랜지스터(T2n)는 오프가 된다. 이때, 푸쉬/풀 회로의 제 1 및 제 2 MOS 트랜지스터(T1n, T2n)에서, 출력 클럭 신호(제 1 클럭 신호)(CK)가 제 1 MOS 트랜지스터(T1n)의 드레인 전극(제 1 클럭 신호 입력 단자)에 공급되고, 저전위 전원(Vss)이 제 2 MOS 트랜지스터(T2n)의 소스 전극에 인가된다. MOS 트랜지스터(T1n, T2n) 사이의 접점의 출력 단자로부터 취한 출력 신호(OUT)가 출력 클럭 신호(CK)에 반응하는 레벨을 갖는 신호로서 획득된다. 즉, 출력 클럭 신호(CK)가 로우 레벨에서 획득되는 동시에, 출력 신호(OUT)도 로우 레벨에서 획득되며, 출력 클럭 신호(CK)가 하이 레벨일 때, 출력 신호(OUT)도 하이 레벨에서 획득된다. 하이 레벨 리세트 신호(RST)가 리세트 신호 입력 단자(제 2 신호 입력 단자)(R)에 공급될 때, 플립 플랍(FF'n)이 리세트되어, 로우 레벨 신호가 출력 단자(Q)로부터 출력되고, 하이 레벨 신호가 반전 출력 단자(

)로부터 출력된다. 이러한 경우, 푸쉬/풀 회로의 제 1 MOS 트랜지스터(T1n)가 오프되고, 제 2 MOS 트랜지스터(T2n)가 온 되어, 로우 레벨에서 출력 단자로부터 출력 신호(OUT)가 획득된다.When the input signal IN goes high and the driving clock signal CK 'goes high, the output of the AND circuit 10 is also obtained at the high level. In this case, the high level signal is supplied to the set signal input terminal S of the flip flop FF'n, so that the flip flop FF'n is set. Accordingly, the high level signal is output from the output terminal Q of the flip flop FF'n, and the low level signal is output from the inverted output terminal (

Is obtained from The output terminal Q of the flip-flop FF'n,

The state of the signal outputted from N) is maintained even when the input signal IN or the driving clock signal CK 'is inverted to the low level. In this manner, a high level voltage is applied to the gate electrode of the first MOS transistor T1n of the push / pull circuit, and a low level voltage is applied to the gate electrode of the second MOS transistor T2n, so that the first MOS transistor ( T1n is turned on, and the second MOS transistor T2n is turned off. At this time, in the first and second MOS transistors T1n and T2n of the push / pull circuit, the output clock signal (first clock signal) CK is the drain electrode of the first MOS transistor T1n (first clock signal input). Terminal), and a low potential power supply Vss is applied to the source electrode of the second MOS transistor T2n. The output signal OUT taken from the output terminal of the contact between the MOS transistors T1n and T2n is obtained as a signal having a level responsive to the output clock signal CK. That is, while the output clock signal CK is acquired at the low level, the output signal OUT is also acquired at the low level, and when the output clock signal CK is the high level, the output signal OUT is also acquired at the high level. do. When the high level reset signal RST is supplied to the reset signal input terminal (second signal input terminal) R, the flip-flop FF'n is reset so that the low level signal is output to the output terminal Q. Is output from the inverted output terminal (

Is output from In this case, the first MOS transistor T1n of the push / pull circuit is turned off, and the second MOS transistor T2n is turned on to obtain the output signal OUT from the output terminal at the low level.

As described above, the signal holding unit FFPn of the present embodiment has another clock signal (driving clock signal CK ': second clock signal) to the output clock signal (first clock signal) CK. It is used as an additional clock signal and has a structure in which the first MOS transistor T1n of the push / pull circuit is turned on when each of the input signal IN and the driving clock signal CK 'is high level. Further, as the timing at which the driving clock signal CK 'becomes high is delayed than the timing at which the input signal IN becomes high, as shown in D2 of FIG. 1B, the voltage is increased in the push / pull circuit. The time applied to the gate electrode of the first MOS transistor T1n may be set at a time D2 shorter than the conventional time D1 described with reference to FIG. 8B. For comparison, D1 described with reference to FIG. 8B is shown in FIG. 1B. In this way, it is possible to reduce the voltage stress applied to the gate electrode which is the main cause of the characteristic deterioration with time when the amorphous silicon TFT is used, and the characteristic deterioration of the first MOS transistor T1n of the push / pull circuit is reduced. Can be suppressed.

Referring to Fig. 2, the relationship between the timing required between the output clock signal (first clock signal) CK and the driving clock signal (second clock signal) CK 'will be described.

As described above, in the signal holding portion FFPn and the shift register circuit having such a member, the timing at which the driving clock signal CK 'becomes high is much higher than the timing at which the input signal IN becomes high. By delaying, the time for which the voltage is applied to the gate electrode of the first MOS transistor T1n of the push / pull circuit is reduced in comparison with the conventional configuration. In addition, the input signal IN is obtained as an output of the signal holding portion FFPn at the front end of the second or next stage in the shift register circuit, and as a signal in response to the timing of the output clock signal CK. . That is, as shown in Fig. 1A, the input signal IN is obtained as a high level signal at the timing when the clock signal CK becomes low level, and is low at the timing when the output clock signal CK becomes high level. Obtained as a level signal.

Accordingly, as shown in Fig. 2 (1), the timing at which the driving clock signal CK 'rises needs to be behind the timing at which the output clock signal CK falls. Also, as shown in Fig. 2, the timing is earlier than the timing at which the output clock signal CK rises.

)로부터 출력되는 타이밍은, 하이 레벨 리세트 신호(RST)가 리세트 신호 출력 단자(R)에 공급되는 타이밍에 따라 결정된다. 상기 타이밍은 구동용 클럭 신호(CK')가 떨어지는 타이밍과 관련이 없다. 그에 따라, 구동용 클럭 신호(CK')이 떨어지는 타이밍은 출력 클럭 신호(CK)가 떨어지는 타이밍과 동일하거나, 또는 그보다 이를 수 있다. 즉, 도 2의 (3)에 지시된 시간은 영(0)이 될 수 있다. 즉, 도 1A 및 2에서, 구동용 클럭 신호(CK')는, 출력 클럭 신호(CK)의 듀티비와 동일한 듀티비를 갖으며 서로 다른 위상을 갖는 파형을 포함하는 반면, 상승 타이밍이 상술된 조건을 만족하는 범위에서 구동용 클럭 신호(CK')는 출력 클럭 신호(CK)와 동일한 듀티비를 갖지 않을 수도 있다. 예를 들면, 도 2의 점선에 의해 지시된 바와 같이, 구동용 클럭 신호(CK')는 출력 클럭 신호(CK)와 다른 듀티비를 갖으며, 출력 클럭 신호(CK)가 떨어지는 타이밍과 동일한 하락 타이밍을 갖는 파형을 생성할 수 있다.In addition, flip-flop FF'n is reset so that the low level signal is output from output terminal Q, and the high level signal is inverted output terminal (

) Is determined in accordance with the timing at which the high level reset signal RST is supplied to the reset signal output terminal R. The timing is not related to the timing at which the driving clock signal CK 'falls. Accordingly, the timing at which the driving clock signal CK 'falls may be equal to or earlier than the timing at which the output clock signal CK falls. That is, the time indicated in (3) of FIG. 2 may be zero. That is, in FIGS. 1A and 2, the driving clock signal CK 'includes a waveform having a duty ratio equal to the duty ratio of the output clock signal CK and having different phases, while the rising timing is described above. The driving clock signal CK 'may not have the same duty ratio as the output clock signal CK in a range satisfying the condition. For example, as indicated by the dotted line in FIG. 2, the driving clock signal CK 'has a duty ratio different from that of the output clock signal CK, and is the same drop as the timing at which the output clock signal CK falls. A waveform with timing can be generated.

In Fig. 1A, the signal holding section FFPn is provided with two inputs provided on the set signal input terminal S side of the set / reset type flip flop FF'n and the flip flop FF'n, respectively. While composed of an AND circuit 10 and a combination of push / pull circuits, such retainers may include other component members within a range that functions in the same manner as described above.

Fig. 3A is a block diagram of another embodiment of a signal holding section having a shift register circuit according to the present invention.

3B is a timing chart for explaining the operation of the signal holding portion in FIG. 3A.

The description of the structural example shown in Figs. 1A and 1B is simplified or omitted.

)에 각각 제공되는 2-입력 AND 회로(12); 두 개의 AND 회로(11, 12) 사이에 제공되는 인버터 회로(인버터)(13); 및 제 1 MOS 트랜지스터(T1n) 및 제 2 MOS 트랜지스터(T2n)로 구성된 푸쉬/풀 회로의 조합으로 구성된다. Each signal holding section FFPn constituting the shift register circuit of the present invention has a set / reset type flip-flop FF'n and flip-flop FF'n as shown in FIG. 3A. Two-input AND circuits 11 provided at terminals Q, respectively; Inverting output terminal of flip flop (FF'n)

A two-input AND circuit 12, each of which is provided to An inverter circuit (inverter) 13 provided between two AND circuits 11 and 12; And a push / pull circuit combination composed of the first MOS transistor T1n and the second MOS transistor T2n.

)는 AND 회로(12) 중 일측의 신호 입력 단자에 접속된다. 구동용 클럭 신호(CK')가 AND 회로(11) 중 타측의 신호 입력 단자에 공급되고, 구동용 클럭 신호가 인버터 회로(13)를 통해 AND 회로(12)의 타측의 신호 입력 단자에 공급된다. AND 회로(11)의 출력이 푸쉬/풀 회로를 구성하는 제 1 MOS 트랜지스터(T1n)의 게이트 전극에 공급되고, AND 회로(12)의 출력이 제 2 MOS 트랜지스터(T2n)의 게이트 전극에 공급되는 방식으로, 접속이 이루어진다.The input signal IN is supplied to the set signal input terminal S of the flip flop FF'n, and the reset signal RST is supplied to the reset signal input terminal R of the flip flop FF'n. The connection is made in such a way. In addition, the output terminal Q of the flip flop FF'n is connected to the signal input terminal of one side of the AND circuit 11, and the inverted output terminal (

) Is connected to the signal input terminal on one side of the AND circuit 12. The driving clock signal CK 'is supplied to the signal input terminal on the other side of the AND circuit 11, and the driving clock signal is supplied to the signal input terminal on the other side of the AND circuit 12 through the inverter circuit 13. . The output of the AND circuit 11 is supplied to the gate electrode of the first MOS transistor T1n constituting the push / pull circuit, and the output of the AND circuit 12 is supplied to the gate electrode of the second MOS transistor T2n. In a manner, a connection is made.

)로부터 출력된다. 이러한 방식으로, 하이 레벨 신호가 AND 회로(11) 일측의 신호 입력 단자로 공급되고, 로우 레벨 신호가 AND 회로(12) 일측의 신호 입력 단자로 공급된다. 이때, 구 동 클럭 신호(제 2 클럭 신호)(CK')가 로우 레벨이다. 이후, 로우 레벨 신호가 AND 회로(11)의 타측 신호 입력 단자에 공급되고, 하이 레벨 신호가 AND 회로(12)의 타측 신호 입력 단자에 공급되어, AND 회로(11)의 출력은 로우 레벨에서 획득되고, AND 회로(12)의 출력은 하이 레벨에서 획득된다.In the operation of the signal holding unit FFPn of the present embodiment, as shown in the timing chart of Fig. 3B, first, the high level input signal IN is the set signal input terminal S of the flip flop FF'n. ), The flip-flop FF'n is set, the high level signal is output from the output terminal Q, and the low level signal is inverted.

Is output from In this manner, the high level signal is supplied to the signal input terminal of one side of the AND circuit 11, and the low level signal is supplied to the signal input terminal of one side of the AND circuit 12. At this time, the driving clock signal (second clock signal) CK 'is at a low level. Thereafter, the low level signal is supplied to the other signal input terminal of the AND circuit 11, and the high level signal is supplied to the other signal input terminal of the AND circuit 12, so that the output of the AND circuit 11 is obtained at the low level. And the output of the AND circuit 12 is obtained at a high level.

Then, when the input clock signal IN is at the high level, when the driving clock signal CK 'is at the high level, the high level signal is supplied to the other signal input terminal of the AND circuit 11, and the low level signal is supplied. It is supplied to the other signal input terminal of the AND circuit 12. Thus, the output of the AND circuit 11 is obtained at the high level, and the output of the AND circuit 12 is obtained at the low level. In this way, a high level voltage is applied to the gate electrode of the first MOS transistor T1n of the push / pull circuit; A low level voltage is applied to the gate electrode of the second MOS transistor T2n; Then, as a signal having a level that reacts with the output clock signal CK, the output signal OUT is obtained from the output terminal of the connection contact between the MOS transistors T1n and T2n.

)로부터 출력된다. 이러한 방식으로, 로우 레벨 신호가 AND 회로(11)의 일측 신호 입력 단자에 공급되고, 하이 레벨 신호가 AND 회로(12)의 일측 신호 입력 단자에 공급된다. AND 회로(11)의 출력은 로우 레벨에서 획득되고, AND 회로(12)의 출력은 하이 레벨에서 획득되며, 출력 단자로부터 출력되는 출력 신호(OUT)는 로우 레벨이 된다.On the other hand, when the reset signal RST is at the high level, the flip-flop FF'n is reset, the low level signal is output from the output terminal Q, and the high level signal is inverted at the output terminal (

Is output from In this manner, the low level signal is supplied to one signal input terminal of the AND circuit 11 and the high level signal is supplied to one signal input terminal of the AND circuit 12. The output of the AND circuit 11 is obtained at the low level, the output of the AND circuit 12 is obtained at the high level, and the output signal OUT output from the output terminal is at the low level.

In the above configuration, as in the configuration shown in Fig. 1A, the following configuration is provided. Using the output clock signal CK and the other driving clock signal CK 'as the clock signal, the timing at which the driving clock signal CK' becomes high is higher than the timing at which the input signal IN becomes high. Much more delay. Subsequently, the input signal IN and the driving clock signal CK 'both become high levels, and the time for which the voltage is applied to the gate electrode of the first MOS transistor T1n of the push / pull circuit will be described with reference to FIG. 8B. It can be set at D2 shorter than the conventional time D1. In this way, the deterioration of the characteristics of the first MOS transistor T1n of the push / pull circuit can be suppressed.

A specific circuit configuration example for implementing the signal holding section constituting the shift register circuit according to the present embodiment will now be described.

4A is a circuit diagram showing a specific configuration example of the signal holding portion according to the present embodiment.

4B is a timing chart for explaining the operation of the signal holding portion in FIG. 4A.

In Fig. 4A, reference symbols? 2 of the plurality of MOS transistors constituting the signal holding portion are shown, and the letter "n" is omitted.

Each of the signal holding portions FFPn basically includes: a first MOS transistor T1n and a second MOS transistor T2n constituting the push / pull circuit described above; And six MOS transistors T11 to T16). The MOS transistors T11 to T16 each have a function similar to the above-described AND circuit and set / reset type flip flop. In addition, the first and second MOS transistors T1 and T2 constituting the push / pull circuit form the output circuit of the present invention.

Here, the MOS transistor T11 forms a third transistor of the present invention; The MOS transistor T12 forms a fourth transistor; The MOS transistor T15 forms a fifth transistor; The MOS transistor T16 forms a sixth transistor; The MOS transistor T14 forms a seventh transistor.

In the MOS transistor T11 which is the third transistor, the gate electrode is connected to the signal input terminal (first signal input terminal) to which the input signal IN is supplied, and the drain electrode is provided as a high potential side operating voltage. It is connected to the power supply Vdd. The source electrode of the MOS transistor T11 is connected to the gate electrode of the MOS transistor T12 which is the fourth transistor.

The drain electrode of the MOS transistor T12 is connected to the second clock signal input terminal, and as shown in FIG. 2, the driving clock signal (second clock signal) having a predetermined timing relationship with the output clock signal (first clock signal). Clock signal) CK '. In addition, the source electrode of the MOS transistor T12 is connected to the gate electrode of the first MOS transistor T1.

In addition, a source electrode of such a MOS transistor T12 is diode-connected to a high potential power supply Vdd, a drain and a source electrode are connected to the MOS transistor T13, and the drain and the source electrode function as a load. It is connected to the gate electrode of the MOS transistor T14 which is a seventh transistor connected between the transistor T13 and the low potential power supply Vss provided as an operating voltage obtained at the low potential side. Thereafter, the drain electrode of the MOS transistor T14 is connected to the gate electrode of the second MOS transistor T2.

In the MOS transistor T15 which is the fifth transistor, a gate electrode is connected to a reset signal input terminal (second signal input terminal) to which the reset signal RST is supplied; A drain electrode is connected to the source electrode of the MOS transistor T11; The source electrode is connected to the low potential power supply Vss. In the MOS transistor T16 which is the sixth transistor, the gate electrode is connected to the second signal input terminal RST to which the reset signal RST is supplied; A drain electrode is connected to the source electrode of the MOS transistor T12; The source electrode is connected to the low potential power supply Vss.

)와 동일하다. The circuit configuration shown in Fig. 4A is the same as the block diagram of the signal holding section described above with reference to Fig. 1A. That is, the MOS transistors T11 to T12 each have the same function as the AND circuit 11 of FIG. 1A, and the MOS transistors T13 to T16 each have the set / reset flip flop FF'n of FIG. 1A. ) Has the same function. In addition, the source electrode of the MOS transistor T12 is the same as the output terminal Q of the flip flop FF'n of FIG. 1A, and the drain electrode of the MOS transistor T14 is the flip flop FF'n of FIG. 1A. Inverting output terminal ()

Same as).

Here, all the eight MOS transistors T1, T2, and T11 to T16 described above are composed of n-type amorphous silicon TFTs.

Now, with reference to the timing chart of FIG. 4B, the operation of the signal holding unit FFPn will be described.

First, the MOS transistor T11 is turned on in such a manner that the high level input signal IN is supplied to a signal input terminal (first signal input terminal) connected to the gate electrode of the MOS transistor T11. The high potential power supply Vss is supplied to the MOS transistor T11, and the MOS transistor T11 is turned on, so that the potential of the source electrode of the MOS transistor T11 is raised. In this manner, the potential of the gate electrode of the MOS transistor T12 connected to the source electrode of the MOS transistor T11 goes up, and this MOS transistor T12 is turned on.

The drain electrode of the MOS transistor T12 is connected to the second clock signal input terminal, and a driving clock signal (second clock signal) CK 'is supplied. As a result, the input signal IN becomes a high level. At the timing when the MOS transistor T11 is turned on, the driving clock signal CK 'is obtained at a low level, and the source electrode (same as the output terminal Q) of the MOS transistor T12 is also at a low level. In this manner, the gate electrode of the first MOS transistor T1 connected to the source electrode �� of the MOS transistor T12 becomes low level. In this way, the first MOS transistor T1 is turned off.

)와 동일한)이하이 레벨이 되며, MOS 트랜지스터(T14)의 드레인 전극에 접속되는 제 2 MOS 트랜지스터(T2)의 게이트 전극 또한 하이 레벨이 된다. 이러한 방식으로, 제 2 MOS 트랜지스터(T2)가 온으로 켜진다.In addition, the gate electrode of the MOS transistor T14 connected to the source electrode of the MOS transistor T12 also becomes low level, and in this manner, the MOS transistor T14 is turned off. Accordingly, the drain electrode (inverting output terminal () of the MOS transistor T14 is caused by the high potential power supply Vdd through the MOS transistor T13 functioning as a diode (rod).

), And the gate electrode of the second MOS transistor T2 connected to the drain electrode of the MOS transistor T14 also becomes a high level. In this way, the second MOS transistor T2 is turned on.

Accordingly, the output signal obtained from the output terminal OUT of the connection contact between the first and second MOS transistors T1 and T2 is the low potential power supply Vss supplied to the source electrode of the second MOS transistor T2. It is at the same low level as.

Thereafter, while the input signal IN is at the high level, the driving clock signal CK 'is raised to become the high level, and the high level driving clock signal CK' is supplied to the drain electrode of the MOS transistor T12. . At this time, the MOS transistor T12 is turned on, and the source electrode (output terminal Q) of the MOS transistor T12 is at a high level. In this manner, the gate electrode of the first MOS transistor T1 and the gate electrode of the MOS transistor T14 are obtained at high levels, respectively, and the MOS transistors T1 and T14 are turned on.

))이 낮아진다. 이후, 제 2 MOS 트랜지스터(T2)의 게이트 전극이 로우 레벨이 되며, 이러한 방식으로, 제 2 MOS 트랜지스터(T2)가 오프된다.When the MOS transistor T14 is turned on, a current path is formed from the high potential power source Vdd to the high potential power source Vdd through the MOS transistors T13 and T14, and the drain electrode (T14) of the MOS transistor T14 is formed. Invert output terminal

)) Becomes lower. Thereafter, the gate electrode of the second MOS transistor T2 is at a low level, and in this manner, the second MOS transistor T2 is turned off.

Accordingly, a signal having a level that reacts with an output clock signal (first clock signal) CK supplied to a second clock signal input terminal connected to the drain electrode of the first MOS transistor T1, and includes the first and second signals. The output signal OUT is output from the output terminal of the connection contact between the second MOS transistors T1 and T2. That is, when the output clock signal CK is at the low level, the output signal OUT is also at the low level.

In addition, when the output clock signal CK is at a high level, the output signal OUT is also at a high level. At this time, the low level input signal IN is supplied to the gate electrode of the MOS transistor T11. However, due to the parasitic capacitance of the gate electrode of the MOS transistor T11, the charge is maintained for a predetermined period of time. Thereafter, the off state is not set immediately, and after the on state is maintained for the predetermined period described above, the off state is turned off. Thus, the on state of the MOS transistors T11, T12, and T14 is maintained for a predetermined period of time. In this manner, the gate electrode of the first MOS transistor T1 is maintained at a high level, the gate electrode of the second MOS transistor T2 is maintained at a low level, and the output signal OUT is at a high level.

When the low level clock signal CK is supplied to the drain electrode of the MOS transistor T12, due to the parasitic capacitance of the gate electrodes of the MOS transistors T14 and T1, the charge is maintained for a predetermined period of time. Accordingly, these MOS transistors T14 and T1 are not immediately turned off; After being kept in the on state for the predetermined period described above, the state is turned off. Thus, for a predetermined period, the on state of these MOS transistors T14 and T1 is maintained, and in this manner, the output signal OUT is maintained at the high level.

When the high level reset signal RST is supplied to the second signal input terminal connected to the gate electrodes of the MOS transistors T15 and T16, these MOS transistors T15 and T16 are turned on. In this manner, the drain electrode of the MOS transistor T15 and the drain electrode of the MOS transistor T16 (output terminal Q) are brought to the low level, respectively, to the gate electrodes of the MOS transistors T12, T14, and T1. After the sustained charge is discharged immediately, these MOS transistors T12, T14, and T1 are turned off, so that the output signal OUT is at a low level.

While each MOS transistor is n-channel type in the above description, it may be p-channel type in a range in which the on / off operation of each MOS transistor is made in the same manner as described above. In addition, such MOS transistors may include both n-channel and p-channel types. In this case, the level of each signal can be appropriately set so that the on / off operation of each MOS transistor is made the same in the above-described manner.

As described above, the signal holding part FFPn of the present embodiment has two clock signals, that is, an output clock signal (first clock signal) CK and a driving clock, as in the configuration shown in Fig. 1A. By using the signal (second clock signal) CK ', the timing at which the driving clock signal CK' is obtained at the high level is significantly delayed than the timing at which the input signal IN is obtained at the high level. In this manner, the time for which the voltage is applied to the gate electrode of the first MOS transistor T1n constituting the push / pull circuit can be set at a time D2 shorter than the conventional configuration. Accordingly, the deterioration of the characteristics of the first MOS transistor T1n of the push / pull circuit can be suppressed.

Now, according to the present embodiment, a configuration of a shift register circuit constituted by connecting a plurality of signal holding portions in series will be described.

FIG. 5 is a circuit diagram showing an example of the configuration of the shift register using the signal holding section according to the present embodiment, and FIG. 6 is a timing chart illustrating the operation of the shift register circuit in FIG.

As shown in Fig. 5, the shift register circuit according to the present embodiment is constructed by connecting a plurality of signal holding portions shown in Figs. 1A, 3A, and 4A in series.

That is, the output signal OUTn of the signal holding unit FFPn of the nth stage is taken from the outside, and the signal input terminal of the signal holding unit FFPn + 1 of the n + 1st stage is used as the input signal IN. First signal input terminal). The reset signal input terminal of the n-th stage signal holding unit FFPn is used as the reset signal RST as an output signal OUTn + 1 from the nth + 1th stage holding unit FFPn + 1. The connection is formed to feed back to the (second signal input terminal). Here, the predetermined start signal ST is supplied to the signal input terminal of the signal holding unit FFP1 of the first stage. In addition, a reset signal is externally supplied to the reset signal input terminal of the flip-flop FFn of the signal holding portion of the final stage.

In addition, for example, when the "m" output stage is required for the shift register circuit, the signal holding portion for the m + 1 stage is used, and finally, without outputting the output signal OUT to the outside. The signal holding portion at the start stage is used as the dummy portion so that the output signal OUT of the stage is supplied to the reset signal input terminal of the signal holding portion of the mth stage as the reset signal RST.

In addition, for the odd-numbered signal holding units FFP1, FFP3, ..., the first output clock signal CK1 and the first driving clock signal (which satisfy the above-described conditions for the first output clock signal ( CK 'may be configured to be supplied as an output clock signal (first clock signal) CK and a driving clock signal (second clock signal) CK', respectively. On the other hand, for the even-numbered signal holding unit FFP2. FFP4, ..., the second output clock signal CK2 and the second output clock signal having the inverted waveform of the first output clock signal CK1 described above. The second output clock signal CK2 'satisfying the above-described condition may be configured to be supplied as the output clock signal CK and the driving clock signal CK', respectively.

According to the shift register circuit described above, in the case of the conventional shift register circuit and as shown in the timing chart shown in Fig. 6, after the start signal is supplied, the high level output signals OUT1, OUT2, OUT3, OUT4,. ..) is sequentially transmitted (shifted), and then output in synchronization with the high level application time of the pulse signals CK1 and CK2.

As described above, in the shift register of the present invention, in addition to the output clock signal CK, another driving clock signal CK 'is used as the clock signal, and the driving clock signal CK' is obtained at a high level. The timing at which the input signal IN is delayed much more than the timing at which the input signal IN is obtained at the high level. In this way, the period during which the voltage is applied to the gate electrode of the first MOS transistor T11 of the push / pull circuit can be considerably reduced as compared with the conventional one, and the deterioration in the characteristics of the MOS transistor T1 with time can be suppressed. This improves the reliability of the shift register circuit for a long time.

Now, with reference to the accompanying drawings, an application example of the shift register circuit according to the present invention will be described.

Fig. 7A is a simplified diagram showing the overall configuration of a liquid crystal display device to which a shift register circuit according to the present invention is applied.

Here, the liquid crystal display device using the active matrix liquid crystal display panel as the liquid crystal display device will be described.

As shown in Fig. 7A, the liquid crystal display device according to the present application includes: a liquid crystal display panel (display means) 10; A source driver (signal driver; display driver) 20; A gate driver (scan driver; display driver) 30; LCD controller 40; System control circuit 50; And digital-to-analog converters (hereinafter referred to as D / A converters).

Now, a detailed description of the members involved follows. As shown in FIG. 7B, the liquid crystal display panel 10 includes: a liquid crystal capacitor CL including a pixel electrode arranged in a matrix form and a common electrode (common voltage Vcom) disposed to face the pixel electrode; A liquid crystal charged between the pixel electrode and the common electrode; A TFT whose source is connected to the pixel electrode (hereinafter referred to as "pixel transistor (TFT)"); A scan line Lg extending in a row direction of the matrix and connected to gates of the plurality of pixel transistors TFT; And a signal line Ld extending in the column direction of the matrix and connected to the drains of the plurality of pixel transistors TFT.

By applying a signal voltage to the pixel electrode selected by the source driver 20 and the gate driver 30 described above, the arrangement of liquid crystals is controlled to display and output predetermined image information. Here, Cs is a charged capacitor, and the liquid crystal capacitor Clc, the charged capacitor Cs, and the pixel transistor TFT constitute the liquid crystal pixel (display pixel) 11.

The source driver 20 transmits a signal voltage corresponding to the image signals R, G, and B to the pixel electrode through the signal line Ld based on the horizontal control signal supplied from the LCD controller 40 described above. Supply.

Here, as shown in FIG. 7B, the source driver 20 includes: a sample storage circuit 22 input together with R, G, and B image signals; And a shift register 21 for controlling the sample holding operation of the sample holding circuit 22. As the sample holding control signal shifted and outputted in the predetermined direction by the shift register 21 is sequentially applied to the sample storage circuit 22, signal voltages corresponding to the applied R, G, and B image signals are applied to the liquid crystal display panel. It is transmitted to the signal line Ld of (10).

On the other hand, in the gate driver 30, based on the vertical control signal supplied from the LCD controller 40, the scan signal is sequentially applied to the scan line Lg and is in a selected state. Thereafter, the source driver 20 applies (writes) the signal voltage supplied to the signal line Ld to the pixel electrode (display pixel) disposed at the position crossing the signal line Ld, and sequentially drives the driving. Run

Gate driver 30 includes a shift register 31 and a buffer 32, as shown in FIG. 7B. As the control signal sequentially shifted and output in the predetermined direction by the shift register 31 is sequentially applied to the scan line Lg of the liquid crystal display panel 10 as a predetermined gate signal, the pixel transistor ITFT is driven and driven. The signal voltage applied to the signal line Ld by the source driver 20 is controlled and applied to the pixel electrode through the pixel transistor TFT.

The LCD controller 40 controls the horizontal control signal and the vertical control signal based on the horizontal control signal HD, the vertical sync signal VD, and the system clock SYSCK supplied from the system control circuit 50. Generate a control signal. Thereafter, as the generated control signal is supplied to the source driver 20 and the gate driver 30, control is performed to apply a signal voltage to the pixel electrode at a predetermined timing, and the desired image information is applied to the liquid crystal display panel 10. Will be displayed.

The system control circuit 50 supplies the system clock SYSCK to the source driver 20, the LCD controller 40, the D / A converter 60, and the like, and the horizontal sync signal HD synchronized with the system clock SYSCK. ) And the vertical sync signal VD are supplied to the LCD controller 40. In addition, a video image signal composed of digital RGB signals is output to the source driver 20 through the D / A converter 60 as analog RGB signals (video signals R, G, and B).

That is, each of the LCD controller 40 and the system control circuit 50 displays and generates desired image information on the liquid crystal display panel 10 based on a video image signal supplied from the outside through an interface (not shown). And a driving control signal generator for generating various control signals for outputting the control signals to the source driver 20 and the gate driver 30.

In the liquid crystal display device having the above-described configuration, the shift register circuit (Fig. 5) according to the present invention is provided with the shift register 21 provided in the source driver 20 and the shift register 31 provided in the gate driver 30. It can be suitably applied as. That is, based on the output clock signals CK1 and CK2 and the driving clock signals CK1 'and CK2' each having a predetermined cycle, the above-described signal holding and holding unit FFPn (Figs. 1A, 3A, 4A). The output signals OUTn sequentially output from the respective outputs can be used as sample holding control signals or control signals output to the buffer 32.

Here, the shift registers 21 and 31 include operation control signals (output clock signals CK1 and CK2, driving clock signals CK1 'and CK2') for performing operations similar to the shift register circuit according to the present invention. The start signal ST may be configured to be generated and output by the LCD controller 40. In addition, the start signal ST is generated and output by the LCD controller 40, and the source driver 20 and the gate driver 30 are omitted, and the output clock signals CK1 and CK2 and the driving clock signal are generated. (CK1 ', CK2') may be generated.

When the shift register circuit according to the present invention is applied to a liquid crystal display device, the shift registers 21 and 31 are operated in a shift manner, and the sequential line driving is executed, the push / pull circuits of the shift registers 21 and 31 are executed. The period during which the voltage is applied to the gate electrode of the first MOS transistor T1 constituting the P can be significantly reduced as compared with the prior art, and in this way, the deterioration of the characteristics of the MOS transistor T1 can be suppressed. In addition, it is possible to provide a liquid crystal display device capable of improving long-term reliability of the shift register circuit and reducing malfunction and deterioration of display characteristics for a long time.

In addition, driving circuits such as the source driver 20 and the gate driver 30 constituted by the shift registers 21 and 31 are integrally formed on the substrate (TFT substrate) of the display panel 10 by an amorphous silicon TFT. It is possible to achieve cost reduction and thinning of the liquid crystal display device.

Although the present invention has been described by way of one embodiment, it is not limited to only such an embodiment, and various modifications and improvements can be made without departing from the gist of the present invention.

For example, the circuit configuration shown in FIG. 4A may be provided as an example for achieving the function of the present invention. To the extent that similar functions can be obtained, the number of transistors or their connections may vary.

In addition, the transistors are not limited to n-channel amorphous silicon (TFT) and may be p-channel. In addition, poly-silicon (TFT) or ZnO-TFT with the same electronic conductivity may be used.

Claims (31)

Connected in series to store and hold a signal based on the supplied input signal, to output an output signal based on the stored and held signal based on the supplied input signal, and to output the output signal as the next input signal It includes a plurality of stages signal holding circuit for supplying, Each of the plurality of stages of signal holding circuits is provided with two types of clock signals including a first clock signal and a second clock signal having a timing delayed by a predetermined delay with respect to the timing of applying the input signal. And an output circuit for supplying a signal at a timing delayed by a delay time of the second clock signal from a timing of applying the input signal, and outputting the output signal at a timing responsive to the first clock signal. And a shift register circuit. The method of claim 1, And a reset signal for resetting the stored and held signal at a timing responsive to the timing of the output signal. The method of claim 2, Each signal holding circuit of the plurality of stages stores and holds the input signal at a timing delayed by the delay time in response to the second clock signal, and stores the held and held signal in response to the reset signal. Further comprising a latch circuit for resetting, and And the output circuit outputs a signal stored and held in the latch circuit as the output signal at a timing in response to the first clock signal. The method of claim 2, Each of the plurality of stages of signal holding circuits further includes a latch circuit for storing and holding the input signal and resetting the stored and held signal in response to the reset signal, and And the output circuit outputs a signal stored and held in the latch circuit as the output signal at a timing in response to the second clock signal. The method of claim 2, And the reset signal is a signal applied at a timing of obtaining an inverted phase of the first clock signal. The method of claim 2, And said reset signal is an output signal output from the signal holding circuit of the next stage. The method of claim 2, The output circuit comprises at least one transistor, and And the transistor is energized only between a timing delayed by the delay time of the second clock signal from a timing of applying the input signal and a timing at which the reset signal is applied. The method of claim 1, Of the signal holding circuits of the plurality of stages, two types of clock signals applied to the signal holding circuits of the even-numbered stages are obtained by inverting two types of clock signals applied to the signal holding circuits of the odd-numbered stages. A shift register circuit, characterized in that one signal. The method of claim 1, And the second clock signal is a signal obtained by shifting the phase of the first clock signal to delay rising timing. The method of claim 1, The rising timing of the second clock signal is within a period from the falling timing of the first clock signal to the rising timing. The method of claim 10, And the falling timing of the second clock signal is equal to or earlier than the falling timing of the first clock signal. The method of claim 1, The output circuit includes: an output terminal for outputting the output signal; A first transistor having a first clock signal applied to a drain electrode and a source electrode connected to the output terminal; A second transistor connected to the output terminal, the source electrode to a low potential power source, and Between the timing of applying the input signal and the timing delayed by the delay time of the second clock signal and the timing of applying the reset signal, a driving signal for energizing the first transistor is a gate electrode of the first transistor. And an inverted signal of the drive signal is supplied to a gate electrode of the second transistor. The method of claim 12, Each of the plurality of stages of signal holding circuits is: A first clock signal input terminal to which the first clock signal is supplied; A second clock signal input terminal to which the second clock signal is supplied; A first signal input terminal to which the input signal is supplied; A second signal input terminal to which the reset signal is supplied; A third transistor having a gate electrode connected to the first signal input terminal and a drain electrode connected to a high potential power supply; A fourth transistor having a gate electrode connected to the source electrode of the third transistor, a drain electrode connected to the second clock signal input terminal, and a source electrode connected to the gate electrode of the first transistor; A fifth transistor having a gate electrode connected to the second signal input terminal, a drain electrode connected to a gate electrode of the fourth transistor, and a source electrode connected to a low potential power supply; And And a gate electrode connected to the second signal input terminal, a drain electrode connected to the gate electrode of the first transistor, and a source electrode including a sixth transistor connected to a low potential power supply. The method of claim 1, And the signal holding circuit is formed of a plurality of field effect transistors having a single conductivity. The method of claim 14, And the field effect transistor is an amorphous silicon thin film transistor. An input signal is supplied, connected in series, and outputs an output signal based on the input signal, and includes a plurality of stages of signal holding circuits for supplying the output signal as an input signal to a next stage, Each of the plurality of stages of signal holding circuits includes a second clock signal including a first clock signal and a second clock signal having a timing delayed by a predetermined delay with respect to the timing of applying the input signal and the reset signal. A clock signal is supplied, and Each of the plurality of signal holding circuits includes: storing and holding the input signal at a timing delayed by the delay time in response to the second clock signal, and recovering the stored and held signal in response to the reset signal. And a latch circuit to be set, and an output circuit for outputting the stored and held input signal as the output signal at a timing responsive to the first clock signal. The method of claim 16, The output circuit comprises at least one transistor, and And the transistor is energized only between a timing delayed by the delay time of the second clock signal from a timing of applying the input signal and a timing at which the reset signal is applied. An input signal is supplied, connected in series, and outputs an output signal based on the input signal, and includes a plurality of stages of signal holding circuits for supplying the output signal as an input signal to a next stage, Each of the plurality of stages of signal holding circuits includes a second clock signal including a first clock signal and a second clock signal having a timing delayed by a predetermined delay with respect to the timing of applying the input signal and the reset signal. A clock signal is supplied, and Each of the plurality of stages of signal holding circuits may include: a latch circuit for storing and holding the input signal and resetting the stored and held signal in response to the reset signal, and in response to the second clock signal; And an output circuit for outputting the stored and held input signal as the output signal at a timing delayed by a delay time. The method of claim 18, The output circuit comprises at least one transistor, and And the transistor is energized only between a timing delayed by the delay time of the second clock signal from a timing of applying the input signal and a timing at which the reset signal is applied. A display driving device for outputting a signal for displaying a desired image on a display panel having a plurality of display pixels in a matrix form, The display driving apparatus includes a shift register circuit for sequentially outputting a control signal to output the signal, The shift register circuit is connected in series: stores and holds a signal based on the supplied input signal, outputs an output signal based on the stored and held signal based on the supplied input signal, and inputs the next stage. A signal holding circuit of a plurality of stages for supplying the output signal as a signal; Each of the plurality of stages of signal holding circuits is provided with two types of clock signals including a first clock signal and a second clock signal having a timing delayed by a predetermined delay with respect to the timing of applying the input signal. And an output circuit for supplying a signal at a timing delayed by the predetermined delay time from the timing of applying the input signal, and outputting the output signal at a timing responsive to the first clock signal. A display driving device for outputting a signal for displaying a desired image on a display panel having a plurality of display pixels in a matrix form. The method of claim 20, And a reset signal for resetting the stored and held signal at a timing responsive to the timing of the output signal. The method of claim 21, And the reset signal is an output signal output from a signal holding circuit of a next stage. The method of claim 20, The output circuit comprises at least one transistor, and And the transistor is energized only between a timing delayed by the delay time of the second clock signal from a timing of applying the input signal and a timing at which the reset signal is applied. The method of claim 20, Of the signal holding circuits of the plurality of stages, two types of clock signals applied to the signal holding circuits of the even-numbered stages are obtained by inverting two types of clock signals applied to the signal holding circuits of the odd-numbered stages. It is a signal, The display drive apparatus characterized by the above-mentioned. The method of claim 20, And the second clock signal is a signal obtained by shifting a phase of the first clock signal to delay a rising timing. The method of claim 20, The rising timing of the second clock signal is within a period from the falling timing of the first clock signal to the rising timing; and The falling timing of the second clock signal is equal to or earlier than the falling timing of the first clock signal. The method of claim 20, The output circuit includes: an output terminal for outputting the output signal; A first transistor having a first clock signal applied to a drain electrode and a source electrode connected to the output terminal; A second transistor connected to the output terminal, the source electrode to a low potential power source, and Between the timing of applying the input signal and the timing delayed by the delay time of the second clock signal and the timing of applying the reset signal, a driving signal for energizing the first transistor is a gate electrode of the first transistor. And an inverted signal of the driving signal is supplied to a gate electrode of the second transistor. The method of claim 27, Each of the plurality of stages of signal holding circuits is: A first clock signal input terminal to which the first clock signal is supplied; A second clock signal input terminal to which the second clock signal is supplied; A first signal input terminal to which the input signal is supplied; A second signal input terminal to which the reset signal is supplied; A third transistor having a gate electrode connected to the first signal input terminal and a drain electrode connected to a high potential power supply; A fourth transistor having a gate electrode connected to the source electrode of the third transistor, a drain electrode connected to the second clock signal input terminal, and a source electrode connected to the gate electrode of the first transistor; A fifth transistor having a gate electrode connected to the second signal input terminal, a drain electrode connected to a gate electrode of the fourth transistor, and a source electrode connected to a low potential power supply; And And a sixth transistor having a gate electrode connected to the second signal input terminal, a drain electrode connected to the gate electrode of the first transistor, and a source electrode connected to a low potential power supply. The method of claim 20, And the signal holding circuit is formed of a plurality of field effect transistors having a single conductivity. The method of claim 29, And the field effect transistor is an amorphous silicon thin film transistor. The method of claim 30, And the display driving element is formed on the same substrate as the display panel.

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