KR20080022497A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and a fabricating method thereof are provided to ensure a space between gate patterns according to reduced design rule, by forming triangular spacers at both sides of the gate patterns. Gate patterns(110) composed of a gate insulating layer(112) and a gate conduction layer(114) are formed on a semiconductor substrate(100). Impurity regions are formed at both sides of the gate patterns in the substrate, and then an insulating layer for a spacer is conformally formed along the gate patterns. The insulating layer is sputtered to form an insulating layer pattern having a flat inclined surface. The insulating layer is anisotropically etched to form triangular spacers at both sides of the gate patterns.

Description

Semiconductor device and method for manufacturing the same {Semiconductor device and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device capable of effectively gap-filling an insulating film and a method for manufacturing the same.

As the degree of integration of semiconductor devices increases rapidly, the distance between the devices is gradually narrowing. Therefore, the line width of the gate electrode of the MOS transistor, which is an important component of the semiconductor device, is also miniaturized, and the distance between the gate electrodes is shortened.

As such, when the distance between the gate electrodes decreases, a gap fill process for filling the space between the gate electrodes and insulating the devices becomes increasingly difficult.

Currently, a chemical vapor deposition (CVD) process is used as a method of gap filling an insulating material between gate electrodes. In such a method, it is difficult to completely gap fill the space between the gate electrodes. That is, a void phenomenon may occur in the center boundary region between the gate electrodes as a pore defect.

As such, when voids are generated in the insulating film, a crack phenomenon may occur in the insulating film around the void in a subsequent process. In addition, when a contact for electrical connection between devices is formed, a conductive material may be buried in a void to cause a bridge phenomenon between the contacts.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of effectively gap filling an insulating film.

In addition, another object of the present invention is to provide a method for manufacturing such a semiconductor device.

The technical problem to be achieved by the present invention is not limited to the above-mentioned problem, another task that is not mentioned is clearly to those skilled in the art from the following description

 It can be understood.

According to an embodiment of the present disclosure, a semiconductor device includes gate patterns formed by stacking a gate insulating film and a gate conductive layer on a semiconductor substrate, and both sides of the impurity regions and gate patterns formed in the semiconductor substrate on both sides of the gate patterns. Triangular spacers formed in the wall.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, in which gate patterns including a gate insulating film and a gate conductive film are stacked on a semiconductor substrate, and impurity regions are formed in the semiconductor substrate on both sides of the gate patterns. Depositing a spacer insulating film conformally along the gate patterns, sputtering the spacer insulating film to form an insulating film pattern having a flat inclined plane, and anisotropically etching the insulating film to form triangular spacers on both sides of the gate patterns. Include.

Specific details of other embodiments are included in the detailed description and the drawings.

According to the semiconductor device of the present invention and a method of manufacturing the same, by forming a spacer having a triangular shape on both sides of the gate pattern, the width between the facing spacers can be gradually increased as the upper surface from the surface of the semiconductor substrate. That is, the space between the gate patterns according to the reduction of the design rule of the semiconductor device may be secured.

Therefore, since the margin between the spacers facing each other increases, it is possible to prevent the formation of voids between the gate patterns when forming the interlayer insulating film that completely fills the transistor. Therefore, the insulating film due to the voids may be damaged, or a conductive material may be embedded in the voids when forming a contact for electrical connection between the devices, thereby preventing the bridge from occurring.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

For reference, a semiconductor device according to an embodiment of the present invention relates to a MOS transistor, and NMOS and PMOS transistors may be formed on a semiconductor substrate for each region.

Hereinafter, a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 1. 1 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

As illustrated in FIG. 1, the active region is defined by the device isolation layer 102, and the gate patterns 110 formed on the semiconductor substrate 100 at predetermined intervals are positioned. The gate patterns 110 have a structure in which the gate insulating layer 112 and the gate conductive layer 114 are stacked, and spacers 134 are positioned on both sides of the gate patterns 110.

The spacers 134 disposed on both sides of the gate patterns 110 are formed in a triangular shape, and have a flat inclined surface inclined from the upper portion of the gate pattern 110 to the semiconductor substrate 100. Accordingly, the width between the spacers 134 facing each other may gradually increase as the width of the spacers 134 rises upward from the surface of the semiconductor substrate 100. Thus, the margin between the facing spacers 134 may be increased. That is, the space between the gate patterns 110 may be secured according to the reduction of the design rule of the semiconductor device.

The buffer layer pattern 122 formed of an oxide layer may be disposed on the sidewall of the gate pattern 110 and the semiconductor substrate 100 in contact with the triangular spacer 134. In addition, impurity regions 104 are formed in the active regions on both sides of the gate patterns 110. The impurity regions 104 may have a double diffused drain (DDD) or a lightly doped drain (LDD) structure.

The silicide layer 142 is formed on the gate patterns 110 and the impurity regions 104 having spacers 134 formed at both sides thereof to reduce contact resistance during contact formation. The silicide layer 142 may be, for example, a titanium silicide layer (TiSi _x ), a tantalum silicide layer (TaSi _x ), a cobalt silicide layer (CoSi _x ), or a nickel silicide layer (NiSi _x ).

As described above, the thin film 150 that stresses the channel region under the gate patterns 110 is formed on the entire surface of the semiconductor substrate 100 on which the gate patterns 110, the spacers 134, and the silicide layer 142 are formed. Located. In detail, the thin film 150 is subject to compressive or tensile stress depending on the NMOS and PMOS transistors. Accordingly, the thin film 150 may increase the mobility of the carrier in the channel region to improve the operating speed of the MOS transistor.

Since the thin film 150 is conformally formed along the surface of the resultant formed on the semiconductor substrate 100, the thin film 150 may be positioned at a predetermined thickness along the inclined surface of the spacer 134 between the gate patterns 110. . The thin film 150 may be formed of, for example, a silicon nitride film or a silicon oxynitride film.

In addition, an interlayer insulating layer 160 is disposed on the thin film 150 to completely fill gaps between the gate patterns 110. Here, since the interlayer insulating layer 160 is formed on the triangular spacer 134 having a flat inclined surface, the interlayer insulating layer 160 may be a high quality interlayer insulating layer 160 in which void formation is suppressed.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 7.

2 to 7 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 2, a device isolation layer 102 is formed by performing a Local Oxidation of Silicon (LOCOS) process or a Shallow Trench Isolation (STI) process on a predetermined region of the semiconductor substrate 100. Accordingly, an active region is defined in the semiconductor substrate 100. Here, the semiconductor substrate 100 may be a silicon substrate or a silicon on insulator (SOI) substrate.

Thereafter, the semiconductor substrate 100 is doped with impurities to form a well. That is, n-well is formed by ion implantation of n-type impurities in the region where the PMOS transistor is to be formed, and p-well is formed by ion implantation of p-type impurities in the region where the NMOS transistor is to be formed.

Thereafter, the gate insulating layer 112 and the gate conductive layer 114 are deposited and patterned on the entire surface of the semiconductor substrate 100 to form the gate patterns 110. In this case, the gate insulating layer 112 may be formed of an oxide film, and the gate conductive layer 114 may be formed of a polysilicon layer doped with impurities.

Subsequently, the impurity region 104 is formed in the active regions on both sides of the gate patterns 110 using the gate patterns 110 as an ion implantation mask. In this case, the impurity region 104 may be formed of a double diffused drain (DDD) or lightly doped drain (LDD) structure. For example, in the case of forming the impurity region 104 of the LDD structure, a low concentration impurity region is formed in the active region between the gate patterns 110, and then a subsequent spacer (see 134 of FIG. 5) is formed, Again, a high concentration of impurity regions may be formed for each region to complete the impurity region 104 of the LDD structure.

Next, as shown in FIG. 3, a spacer insulating layer 130 is conformally formed along the gate patterns 110.

Before forming the spacer insulating layer 130, the buffer layer 120 may be conformally formed along the gate patterns 110. Here, the buffer layer 120 serves to recover damages on the surfaces of the gate patterns 110 during an etching process for forming the gate patterns 110. The buffer layer 120 may be formed by thermally oxidizing the semiconductor substrate 100 on which the gate patterns 110 are formed, and may be thinly formed to a thickness of about 50 μs or less. For example, the buffer film 120 may be formed of a silicon oxide film or a metal oxide film.

Thereafter, an insulating film 130 for spacers is formed on the buffer film 120. The spacer insulating layer 130 may be formed by depositing a silicon nitride film or a silicon oxynitride film. When forming the spacer insulating layer 130, for example, a deposition process such as a rapid thermal chemical vapor deposition (RTCVD) or an automatic layer deposition (ALD) process may be performed.

Next, as shown in FIG. 4, a sputtering process is performed on the spacer insulating film 130 conformally deposited on the gate patterns 110.

When the sputtering process is performed on the spacer insulating layer 130, etching occurs while the spacer insulating layer 130 is deposited. That is, since the sputtering speed is high on the gate patterns 110, the spacer insulating layer 13 is etched to form an insulating layer pattern 132 having a sharp shape. In addition, the spacer insulating layer 130 etched on the gate patterns 110 is redeposited between the gate patterns 110. Accordingly, the insulating layer pattern 132 having an inclined surface may be formed on the semiconductor substrate 100 between the gate patterns 110 while filling the gate patterns 110.

Subsequently, as shown in FIG. 5, the anisotropic etching process is performed on the insulating layer pattern 132 and the buffer layer 120 to incline the semiconductor substrate 100 on both sides of the gate patterns 110, and to form a flat inclined surface. A spacer 134 having the same shape. In this case, as an anisotropic etching process, for example, a reactive ion etching (RIE) process may be performed. That is, triangular spacers 134 may be formed on both sides of the gate patterns 110.

As described above, as the spacers 134 having a triangular shape are formed on both sides of the gate patterns 110, the width between the gate patterns 110 may gradually increase as the upper portion rises from the surface of the semiconductor substrate 100. Thus, the margin between the facing spacers 134 may be increased. That is, the space between the gate patterns 110 may be secured according to the reduction of the design rule of the semiconductor device.

Subsequently, when the impurity region 104 of the LDD structure is formed, a high concentration of impurities are implanted into the active region of the semiconductor substrate 100 using the gate patterns 110 having spacers 134 formed on both sides as a mask. do.

Accordingly, the PMOS transistor and the NMOS transistor are completed for each region of the semiconductor substrate 100.

Next, as shown in FIG. 6, the silicide layer 142 is formed on the gate patterns 110 and the impurity region 104. In more detail, a silicide metal film (not shown) is formed on the entire surface of the semiconductor substrate 100 on which the gate patterns 110 and the impurity region 104 are formed. Here, the silicide metal layer may be formed by depositing a material such as titanium (Ti), tantalum (Ta), cobalt (Co), or tungsten (W).

Thereafter, a high temperature heat treatment process is performed on the entire surface of the semiconductor substrate 100 to cause the silicide metal film and the silicon component to react. Here, the heat treatment process may be performed using a rapid thermal process (RTP) apparatus, a furnace or a sputter apparatus.

After the heat treatment process, a selective wet etch process is performed to remove the unreacted silicide metal film. In this case, a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) may be used as the wet etching solution.

As a result, the silicide layer 142 is completed on the surface of the impurity region 104 and the gate patterns 110. The silicide layer 142 formed as described above may reduce contact resistance during contact formation in a subsequent process, and minimize increase in resistance of the gate pattern due to miniaturization.

After the silicide layer 142 is formed, as shown in FIG. 7, a thin film 150 for implementing a high performance MOS transistor is conformally formed on the entire surface of the resultant. In this case, the thin film 150 is formed between the gate patterns 110 along the flat inclined surface of the spacer 134. That is, the thin film 150 may have a gentle slope between the gate patterns 110. For example, the thin film 150 may be formed by stacking a silicon nitride film, a silicon oxynitride film, or the like. Here, the thin film 150 may be formed to have tensile stress or compressive stress according to the NMOS or PMOS region. Accordingly, the thin film 150 exerts a predetermined stress on the channel region of the transistor, thereby increasing the mobility of the carrier. The thin film 150 may also serve as an etch stop layer when forming a contact in a subsequent process.

Next, as shown in FIG. 1, an insulating material is filled on the thin film 150 to form an interlayer insulating layer 160 having a sufficient thickness. In this case, the interlayer insulating layer 160 may be formed of Tetra Ethyl Ortho Silicate (TEOS), Undoped Silicate Glass (USG), Phospho Silicate Glass (PSG), Borosilicate Glass (BSG), BoroPhosphoSilicate Glass (BPSG), Fluoride Silicate Glass (FSG), and SOG. (Spin On Glass), TOSZ (Tonen SilaZene) or a combination thereof may be used. The interlayer insulating layer 160 may be formed using a chemical vapor deposition (CVD) method, a spin coating method, or the like.

In this case, since the spacer 134 having a triangular shape is formed on both sides of the gate patterns 110, the interlayer insulating layer 160 is formed on the thin film 150 along the inclination of the spacer 134. That is, since the gap-fill margin between the gate patterns 110 is increased by the spacer 160 having a triangular shape, a high quality interlayer insulating film filling the gap between the gate patterns 110 while suppressing void formation is provided. Can be formed.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

2 to 7 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols on main parts of the drawings>

100: semiconductor substrate 102: device isolation film

110: gate pattern 112: gate insulating film

114: gate conductive film 120: buffer film

122: buffer film pattern 130: insulating film for spacer

132: insulating film pattern 134: spacer

142: silicide film 150: thin film

160: interlayer insulating film

Claims (12)

Gate patterns formed by stacking a gate insulating film and a gate conductive film on a semiconductor substrate; An impurity region formed in the semiconductor substrate on both sides of the gate patterns; And And a triangular spacer formed on both sidewalls of the gate patterns. The method of claim 1, And an interlayer insulating layer in which the spacer completely fills the gate patterns formed on both sidewalls. The method of claim 2, And a buffer layer formed on the gate pattern and the semiconductor substrate in contact with the spacer. The method of claim 2, And a silicide film formed on a surface of the gate conductive film and the impurity region. The method of claim 2, And a thin film provided under the interlayer insulating layer and conformally formed along the surfaces of the semiconductor substrate, the spacer and the gate patterns. Forming gate patterns on which a gate insulating film and a gate conductive film are stacked on a semiconductor substrate, An impurity region is formed in the semiconductor substrate on both sides of the gate patterns, Depositing a spacer insulating film conformally along the gate patterns, Sputtering the insulating film for spacers to form an insulating film pattern having a flat inclined surface, And anisotropically etching the insulating layer to form triangular spacers on both sides of the gate patterns. The method of claim 6, A method of manufacturing a semiconductor device, the method comprising: forming an interlayer insulating film completely filling the gate patterns having spacers formed at both sides thereof. The method of claim 7, wherein And forming a buffer film conformally along the gate patterns under the spacer insulating film. The method of claim 7, wherein forming the insulating film pattern, And forming a sharp portion on the gate patterns. The method of claim 7, wherein forming the spacer, Reactive ion etching (RIE) of the insulating film manufacturing method. The method of claim 7, wherein And forming a silicide film on surfaces of the gate conductive film and the impurity region after forming the spacer. The method of claim 7, wherein And forming a conformally stressed thin film along surfaces of the semiconductor substrate, the spacer, and the gate patterns before forming the interlayer insulating film.

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