KR20080020308A - Thin film transistor substrate and method for manufacturing thin film transistor substrate - Google Patents

Abstract

A TFT substrate and a manufacturing method thereof are provided to increase the capacitance of a storage capacitor by reducing the thickness of an insulating film of an upper part of a storage electrode pattern and improve an open ratio by reducing the size of the storage electrode pattern. A method for manufacturing a TFT(Thin Film Transistor) substrate comprises the following steps of: forming an active pattern(1200) and a storage electrode pattern(1300) on a substrate(1100); forming a gate insulating film(1400) where a thickness of a storage electrode pattern upper side is thinner than a thickness of an active pattern upper side; and injecting impurity ion into the storage electrode pattern.

Description

Thin Film Transistor Substrate and Manufacturing Method Thereof {THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE}

1 to 4 are diagrams for explaining a method of manufacturing a thin film transistor substrate according to the first embodiment of the present invention.

5 to 9 are cross-sectional conceptual views illustrating a method of manufacturing an active pattern and a storage pattern according to the first embodiment.

10 to 13 are views for explaining a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention.

14 to 18 are cross-sectional conceptual views illustrating a method of manufacturing an active pattern and a storage pattern according to a second embodiment.

<Explanation of symbols for the main parts of the drawings>

1100: substrate 1200: active pattern

1300: storage electrode pattern 1400: gate insulating film

1510: gate electrode 1600: storage line

1700: interlayer insulating film 1810: source electrode

1900: drain electrode 2100: pixel electrode

The present invention relates to a thin film transistor substrate, a method for manufacturing the same, and a method for manufacturing a liquid crystal display panel including the same. A thin film transistor substrate capable of simplifying a manufacturing process of a thin film transistor substrate and increasing capacitance of a storage capacitor, and a method thereof It relates to a manufacturing method.

In general, a liquid crystal display (LCD) includes a thin film transistor substrate including a pixel electrode and a thin film transistor (TFT) for switching each pixel, and a common electrode substrate including a color filter and a common electrode. And liquid crystal sealed between the two substrates. The pixel electrode of the thin film transistor substrate forms a liquid crystal capacitor together with the common electrode of the common electrode substrate. The liquid crystal display adjusts the arrangement of liquid crystals by separately supplying data signals (gradation voltages) according to image information to each of the liquid crystal capacitors of each pixel, and adjusts the amount of light passing through the liquid crystals according to the adjusted arrangement of the liquid crystals to display an image. Display.

The gray voltage applied to one pixel is charged across the liquid crystal capacitor for a short time, and the charged voltage must be maintained until the next gray voltage is input. Therefore, in order to keep the voltage charged in the liquid crystal capacitor constant within each pixel, a storage capacitor is connected to the liquid crystal capacitor.

A liquid crystal display including a thin film transistor composed of polycrystalline silicon forms a polycrystalline silicon thin film on a substrate and patterns the active thin film to form an active pattern and a storage electrode pattern. In this case, impurity ions are implanted into the storage electrode pattern region through a separate ion implantation process after the patterning process in order to secure sufficient capacitance. In the ion implantation process, a photoresist film is coated on a substrate on which an active pattern and a storage electrode pattern are formed, and then developed and exposed to form a photoresist mask. Thereafter, ion implantation using the photoresist mask as an ion implantation mask is performed to implant impurity ions into the storage electrode pattern region.

As described above, there is a problem in that a separate photo mask for forming the ion implantation mask pattern on the substrate is additionally manufactured. In addition, the fabrication and removal of the ion implantation mask using the photoresist film in addition to the patterning process causes a surface damage of the active pattern to be used as the channel region of the thin film transistor, thereby adversely affecting device operation. In addition, there is a problem that the yield is reduced due to the increase of the process step, as well as the productivity is lowered.

In addition, the conventional storage electrode pattern should be manufactured to a certain size or more to secure the capacitance of the target storage capacitor. Since the storage electrode pattern is formed in the pixel area, there is a problem in that the aperture ratio decreases.

Accordingly, the present invention was derived to solve the above problems, and the manufacturing process is simplified by performing a patterning process for patterning an active pattern and a storage electrode pattern and an ion implantation process for implanting impurity ions into the storage electrode pattern with a single mask. It is an object of the present invention to provide a thin film transistor substrate and a method of manufacturing the same, which can increase the capacitance of a storage capacitor by reducing the distance between the storage electrode pattern and the storage line connected to the pixel electrode.

Forming an active pattern and a storage electrode pattern on a substrate according to the present invention, forming a gate insulating layer having a thickness higher on the storage electrode pattern than on the active pattern, and forming impurity ions on the storage electrode pattern. It provides a method for manufacturing a thin film transistor substrate comprising the step of implanting.

The forming of the gate insulating layer having a thickness higher than the thickness of the upper portion of the active electrode pattern above the active pattern may include forming the gate insulating layer on the substrate on which the active pattern and the storage electrode pattern are formed. And forming a photoresist mask pattern exposing the upper region of the storage electrode pattern and removing a portion of the gate insulating layer in the exposed region.

The implanting of impurity ions into the storage electrode pattern may include performing an ion implantation process using the photoresist mask pattern as an ion implantation mask and removing the photoresist mask pattern.

The method may further include forming a silicon thin film and a first gate insulating film on a substrate according to the present invention, and removing the first gate insulating film and the silicon thin film by using a photoresist mask pattern having a height difference to form an active pattern and a storage electrode pattern. Exposing the first gate insulating layer on the upper side of the storage electrode pattern by lowering the height of the photoresist mask pattern; and exposing the photoresist mask pattern having the lowered height as an etching mask and an ion implantation mask. Removing the first gate insulating film and implanting impurities into the storage electrode pattern; removing the remaining photoresist mask pattern; and forming a second gate insulating film over the entire structure. To provide.

Forming a gate electrode overlapping the active pattern with a portion of the active layer, a gate line connected to the gate electrode in one direction, and a storage line overlapping the storage electrode pattern with a portion of the storage layer; The method may further include forming a source region and a drain region by implanting impurity ions into the active patterns on both sides of the gate electrode, and forming an interlayer insulating layer on the entire surface of the substrate on which the gate electrode is formed.

In addition, a substrate according to the present invention, an active pattern and a storage electrode pattern formed on the substrate and having a source region, a drain region and a channel region, a gate insulating film formed on the active pattern and the storage electrode pattern, and A gate electrode disposed on a gate insulating layer, the gate electrode overlapping a portion of the channel region, a gate line connected to the gate electrode and extending in one direction, a storage line overlapping the storage electrode pattern, and a portion of the source region; A source electrode connected to the source electrode, a source line connected to the source electrode and extending in the other direction, and a drain electrode connected to the drain region and overlapping the storage line with a portion thereof; The thickness of the gate insulating layer is greater than that of the gate insulating layer It provides a thin film transistor substrate than to.

In this case, when the thickness of the gate insulating layer on the active pattern is set to 1, the thickness of the gate insulating layer on the storage electrode pattern is preferably 0.1 to 0.9.

At least two gate insulating layers are stacked on the active pattern, at least one gate insulating layer is stacked on the storage electrode pattern, and a gate insulating layer is stacked on the storage electrode pattern. It is preferable that it is thicker than the thickness of an insulating film.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you.

In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity, and like reference numerals designate like elements. In addition, when a part such as a layer, a film, an area, or a plate is expressed as being on or above another part, not only when each part is directly above or directly above the other part but also another part between each part and another part This includes cases.

1 to 4 illustrate a method of manufacturing a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIGS. 5 to 9 illustrate a method of manufacturing an active pattern and a storage pattern according to the first exemplary embodiment. These are cross-sectional conceptual diagrams.

Hereinafter, a method of manufacturing the thin film transistor substrate according to the present embodiment will be described with reference to FIGS. 1 to 9. FIG. 5 illustrates a unit pixel area having one pixel electrode and one thin film transistor.

As shown in FIG. 1, the active pattern 1200 and the storage electrode pattern 1300 for the storage capacitor are formed on the transparent insulating substrate 1100, the gate insulating layer 1400 is formed on the entire structure, and the storage electrode pattern ( 1300) dopant ions are doped into the region. In the present embodiment, the thickness T1 of the gate insulating film 1400 on the storage electrode pattern 1300 is preferably made thinner than the thickness T2 of the gate insulating film 1400 in another region.

This will be described in detail with reference to FIGS. 5 to 9.

First, referring to FIG. 5, the polycrystalline silicon thin film 1110 is formed on the transparent insulating substrate 1100. The polycrystalline silicon thin film 1110 is preferably formed by depositing an amorphous silicon thin film on the substrate 1100 and then performing a crystallization process. That is, an amorphous silicon thin film (a-Si: H) is deposited on the substrate 130 through a Low Pressure Chemical Vapor Deposition (LPCVD) method or a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. Deposit. Thereafter, a dehydrogenation process of removing hydrogen of the amorphous silicon thin film is performed, and then the amorphous silicon thin film is crystallized using heat to form a polycrystalline silicon thin film. At this time, it is effective to use the solid phase crystallization (SPC) method and the excimer laser annealing (ELA) method as the crystallization method using the heat. In addition, a buffer layer (not shown) including at least one of a silicon oxide film and a silicon nitride film may be formed on the substrate 1100, and a polycrystalline silicon thin film 1110 may be formed thereon.

The first photoresist mask pattern 1101 is formed by applying a photoresist film on the polycrystalline silicon thin film 1110 and then performing a photolithography process using a mask. The first photoresist mask pattern 1101 may open an area except for an area in which the active pattern 1200 and the storage electrode pattern 1300 are to be formed.

Referring to FIG. 6, an exposed polycrystalline silicon thin film 1110 is patterned by performing an etching process using the first photoresist mask pattern 1101 as an etching mask to form an active pattern 1200 and a storage electrode pattern 1300. do. Here, as shown in FIG. 1, the active pattern 1200 is formed in a substantially straight shape extending in the horizontal direction in the region where the thin film transistor is to be formed, and the storage electrode pattern 1300 is formed on one side of the active pattern 1200. It is preferred to be manufactured in a substantially plate shape extending from the end. In this case, the storage electrode pattern 1300 may vary in area, shape, and location of the storage electrode pattern 1300 according to the aperture ratio and the capacitance of the storage capacitor 130. The first photoresist mask pattern 1101 is removed, and a gate insulating film 1400 is formed on the substrate 1100 on which the active pattern 1200 and the storage electrode pattern 1300 are formed. The gate insulating film 1400 uses an insulating film including a silicon oxide film and / or a silicon nitride film.

Referring to FIG. 7, a photoresist film is coated on the gate insulating film 1400 and a photolithography process using a mask is performed to form a second photoresist mask pattern 1102 that opens the storage electrode pattern 1300.

Referring to FIG. 8, an etching process using the second photoresist mask pattern 1102 as an etch mask is performed to remove a portion of the gate insulating layer 1400 of the exposed region (ie, the upper portion of the storage electrode pattern 1300). . Subsequently, ion implantation is performed using the second photoresist mask pattern 1102 as an ion implantation mask to implant impurity ions into the storage electrode pattern 1300.

In this case, since the thickness of the gate insulating layer 1400 on the upper side of the storage electrode pattern 1300 is thin, the ion projection depth R _p may be easily set, and the acceleration energy for ion implantation may not be high. In the ion implantation process according to the present embodiment, N-type impurity ions such as phosphorus (P) or arsenic (As) are preferably ion implanted at a dose of 10 ¹⁴ to 10 ¹⁶ / cm 2 at an acceleration energy of 10 to 30 KeV. . In this case, impurity ions may not be implanted into the storage electrode pattern 1300 when an acceleration energy lower than the acceleration energy is used, and impurity ions implanted when the acceleration energy higher than the acceleration energy is used escape the substrate from the storage electrode pattern 1300. A problem that is injected into 1100 occurs.

Next, as shown in FIG. 9, when the second photoresist mask pattern 1102 is removed, an active pattern 1200 and a storage electrode pattern 1300 into which impurities are injected are formed, and an upper portion of the storage electrode pattern 1300 is formed. A gate insulating film having a thickness T1 of the gate insulating film 1400 that is thinner than another region is formed.

As described above, according to the present exemplary embodiment, the gate insulating film 1400 on the upper side of the storage electrode pattern 1300 is removed by using the second photoresist mask pattern 1102 in which impurity ions are implanted into the storage electrode pattern 1300. Can be. As a result, the thickness T1 of the gate insulating layer 1400 on the storage electrode pattern 1300 may be made thinner than the thickness T2 of the gate insulating layer 1400 of another region. In this case, when the thickness T2 of the gate insulating film 1400 of another region is 1, the thickness T1 of the gate insulating film 1400 on the storage electrode pattern 1300 may be 0.1 to 0.9. The storage electrode pattern 1300 is connected to the drain terminal 1230 and the pixel electrode 2100 of the thin film transistor 1200 which are manufactured through a subsequent process.

Accordingly, in the present embodiment, the opening ratio may be improved by reducing the size of the storage electrode pattern 1300. Here, the capacitance of the storage capacitor is inversely proportional to the distance between the storage electrode pattern 1300 and the storage line 1600 fabricated through a subsequent process and is proportional to the overlapping area of the two electrodes. The distance between the storage electrode pattern 1300 and the storage line is determined by the thickness of the gate insulating layer 1400 provided in the region between the storage electrode pattern 1300 and the storage line. Therefore, when the thickness of the gate insulating film 1400 is reduced as in the present exemplary embodiment, the capacitance of the storage capacitor may be increased in inverse proportion thereto. When the same capacitance is maintained, the overlap area size of the storage electrode pattern 1300 and the storage line 1600 may be reduced. As described above, since the size of the storage electrode pattern 1300 and the storage line 1600 can be reduced while maintaining the desired storage capacitance, the aperture ratio can be improved.

Next, as shown in FIG. 2, a first conductive film is formed on the entire surface of the substrate 1100 on which the active pattern 1200, the storage electrode pattern 1300, and the gate insulating film 1400 are formed, and the first conductive film is patterned. Therefore, it is preferable to form the gate line 1500, the gate electrode 1510, and the storage line 1600.

It is preferable to use at least any one of Mo, Cu, Al, Ti, Cr, and these alloys for the said 1st conductive film. At this time, the first conductive film may be formed in a single layer structure, or may be formed in a double or more multilayer structure. The first conductive layer is patterned to form the gate line 1500, the gate electrode 1510, and the storage line 1600. That is, a photoresist layer is coated on the first conductive layer, and then a photoresist mask pattern (not shown) is formed to shield the gate line 1500, the gate electrode 1510, and the storage line 1600 through the photolithography process. Thereafter, an etching process using the photoresist mask pattern as an etching mask is performed to etch the first conductive film in the exposed region, and the photoresist mask pattern is removed. As a result, the gate line 1500 extending in the horizontal direction, the gate electrode 1510 protruding from the active pattern 1200, and a portion of the gate line 1500 overlapping the gate line 1500 extend in the same direction as the gate line 1500. A storage line 1600 overlapping with the electrode pattern 1300 is formed. As illustrated in the drawing, the storage line 1600 includes an extension part connecting the adjacent pixel areas and an electrode part overlapping the storage electrode pattern 1300. The extension part may be manufactured in a linear shape, and the electrode part may be manufactured in a plate shape. The electrode portion may be manufactured to have the same size as the storage electrode pattern 1300. The capacitance of the storage capacitor may be increased by reducing the thickness of the gate insulating layer 1400 on the upper portion of the storage electrode pattern 1300 doped with impurity ions. As a result, the voltage applied to the liquid crystal capacitor may be kept constant until the next signal voltage is applied to the liquid crystal capacitor.

The gate electrode 1510 is positioned in the center region of the active pattern 1200, and the active pattern 1200 overlapping the gate electrode 1510 is defined as a channel region 1210.

After forming the gate electrode 1510, an ion implantation process is performed to form the source region 1220 and the drain region 1230 in the active pattern 1200 at both sides of the gate electrode 1510.

The ion implantation process is preferably performed by separating (i.e., using a different mask) a process of implanting N-type impurity ions and a process of implanting P-type impurity ions according to the characteristics (carrier characteristics) of the transistor to be formed. . That is, the region in which the N type impurity ions are to be implanted is opened by using a mask pattern (not shown), and then the N type impurity ions are implanted into the active patterns 1200 on both sides of the gate electrode 1510. Subsequently, a region in which P-type impurity ions are to be implanted is opened using another mask pattern (not shown), and then P-type impurity ions are implanted into the active patterns 1200 on both sides of the gate electrode 1510. Through this, N-type transistors and P-type transistors may be manufactured on the single substrate 1100, respectively. Of course, the present invention is not limited thereto, and an ion barrier layer (not shown) may be formed on the gate electrode 1510 to perform ion implantation using the ion implantation mask, and a plurality of ion implants, that is, high concentration ion implantation and low concentration ion implantation, may be used. Injection may also be performed.

Next, as shown in FIG. 3, an interlayer insulating layer 1700 is formed on the entire surface of the substrate 1100 on which the gate electrode 1510 is formed, and passes through the interlayer insulating layer 1700 to drain the source region 1220 and the drain. The source electrode 1810, the source line 1800, and the drain electrode 1900 are respectively connected to the region 1230.

As the interlayer insulating film 1700, it is preferable to use an inorganic insulating material including a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN _x ). Of course, an organic insulating material may be used as the interlayer insulating film 1700. The interlayer insulating film 1700 may be formed of a single layer or may be formed of a multilayer film. After the interlayer insulating film 1700 is formed on the entire structure, a photosensitive film is coated on the interlayer insulating film 1700. A photolithography process using a mask is performed to form a photoresist mask pattern that opens the source region 1220 and the drain region 1230. An etching process using the photoresist mask pattern as an etching mask is performed to form a source contact hole 1820 to open a portion of the source region 1220 and a drain contact hole 1910 to open a portion of the drain region 1230. do.

A second conductive film is formed on the entire surface of the substrate 1100 on which the interlayer insulating film 1700 is formed, and then patterned to form a linear source line 1800 orthogonal to the gate line 1500, and at the source line 1800. Protruding to form a source electrode 1810 to be connected to the source region 1220 through the source contact hole 1820, and is connected to the drain region 1230 through the drain contact hole 1910 and the storage line 1600 And a portion of the drain electrode 1900 overlapping each other are formed. The second conductive film uses at least one of Mo, Cu, Al, Ti, Cr, and alloys thereof. As shown in the drawing, the drain electrode 1900 includes a connection part connected to the drain region 1230 of the active pattern 1200 and an extension part having the same shape as the storage electrode pattern 1300. An extension of the drain electrode 1900 may increase the capacitance of the storage capacitor. In addition, the capacitance value can be freely changed by changing the shape of the extension without limiting the above description. An extension of the drain electrode 1900 is connected to the pixel electrode through a subsequent process. The drain electrode 1900 may be used as one electrode plate of the storage capacitor, and the storage electrode line 1600 may be used as another electrode plate of the storage capacitor.

Next, as shown in FIG. 4, the passivation layer 2000 is formed on the entire surface of the substrate 1100 on which the source electrode 1810 and the drain electrode 1900 are formed, and the drain electrode 1900 is formed on the passivation layer 2000. The pixel electrode 2100 to be connected is formed.

That is, after forming the passivation layer 2000, a pixel contact hole 2110 exposing a part of the drain electrode 1900 is formed. The passivation layer 2000 uses an inorganic insulating material or an organic insulating material. Thereafter, a light-transmissive conductive film including indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire structure. The transmissive conductive layer is patterned to form a pixel electrode 2100 connected to the drain electrode 1900 through the pixel contact hole 2110.

In addition, the present invention is not limited to the above description, and a gate insulating film may be formed on a polycrystalline silicon thin film, and then an active pattern and a storage electrode pattern may be formed, and impurity ions may be implanted into the storage pattern. You can also prevent light leakage. The thickness of the gate insulating layer on the storage electrode pattern may be reduced by using a slit or a semi-transmissive mask. Hereinafter, a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention will be described. The description overlapping with the above description will be omitted. In addition, the technology of the embodiments to be described later may be applied to the embodiments described above.

10 to 13 illustrate a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIGS. 14 to 18 illustrate a method of manufacturing an active pattern and a storage pattern according to a second exemplary embodiment. These are cross-sectional conceptual diagrams.

Hereinafter, a method of manufacturing the thin film transistor substrate according to the present embodiment will be described with reference to FIGS. 10 to 18.

As shown in FIG. 10, the active pattern 1200 and the impurity ion-doped storage electrode pattern 1300 are formed on the transparent insulating substrate 1100, and the gate insulating layer 1410 is formed on the patterns 1200 and 1300. 1420. The thickness of the gate insulating layer 142 on the upper side of the storage electrode pattern 1300 may be thinner than the thickness of the gate insulating layers 1410 and 1420 on the upper side of the active pattern 1200. That is, in the present exemplary embodiment, first and second gate insulating layers 1410 and 1420 are formed on the active pattern 1200, and a second gate insulating layer 1420 is formed on the storage electrode pattern 1300.

This will be described in detail with reference to FIGS. 14 to 18.

First, referring to FIG. 14, a polycrystalline silicon thin film 1110 and a first gate insulating film 1410 are formed on a light-transmissive insulating substrate 1100, and a photosensitive film 1120 is coated on the transmissive insulating substrate 1100.

Referring to FIG. 15, a photolithography process using a halftone photo mask 3000 is performed to form a first photoresist mask pattern 1130. In this case, the first photoresist mask pattern 1130 is manufactured to have a height lower than that of the photoresist layer 1120 in the region where the active pattern 1200 is to be formed.

When the exposure process is performed using the halftone photo mask 3000 described above, the photoresist film 1120 under the light-transmitting region J is completely exposed, and the photoresist film 1120 under the light-shielding region K is not exposed. Instead, only a portion of the photoresist film 1120 under the semi-transmissive region L is exposed above the photoresist film 1120. Subsequently, when the development process is performed, as illustrated in FIG. 15, the photoresist film 1120 under the light transmissive region J is completely removed, and the photoresist film under the transflective region L is removed with only a portion of the exposed upper side. The photosensitive film 1120 under the light blocking region K is not removed and remains. As a result, as described above, the height of the photoresist layer 1120 remaining on the polycrystalline silicon thin film 1110 on which the storage electrode pattern 1300 is to be formed remains on the polycrystalline silicon thin film 1110 on which the active pattern 1200 is to be formed. The first photoresist mask pattern 1130 lower than the height of the photoresist 1120 may be formed. The height difference may vary depending on the light transmittance of the halftone film 3200 formed in the transflective region L of the halftone photo mask 3000 described above.

In addition, the present exemplary embodiment is not limited thereto, and instead of the halftone photo mask 3000, a slit mask in which a slit pattern is formed in the transflective region L may be used.

Referring to FIG. 16, an etch process using the first photoresist mask pattern 1130 as an etch mask may be performed to sequentially expose the first gate insulating layer 1410 and the polycrystalline silicon thin film 1110 exposed on the substrate 1100. The active pattern 1200 and the storage electrode pattern 1300 are formed by removing the active pattern 1200. In this case, the first gate insulating layer 1410 remains only in the upper region of the active pattern 1200 and the storage electrode pattern 1300.

Here, as shown in FIG. 10, the active pattern 1200 is formed in a substantially linear shape extending in the horizontal direction in the region where the thin film transistor is to be formed, and at both ends thereof, an extended region for connecting the source electrode and the drain electrode. It is preferable that this be provided. The storage electrode pattern 1300 is preferably manufactured in a substantially plate shape extending from one end of the active pattern 1200.

Referring to FIG. 17, a portion of the first photoresist mask pattern 1130 is removed through a first ashing process to open an upper region of the storage electrode pattern 1300, and a photoresist layer remains in an upper region of the active pattern 1200. 2 Photosensitive film mask pattern is formed. Thereafter, an etching process using the second photoresist mask pattern 1140 as an etching mask is performed to remove the first gate insulating layer 1410 of the exposed region. That is, the first gate insulating layer 1410 on the storage electrode pattern 1300 is removed. An impurity ion is implanted into the exposed storage electrode pattern 1300 by performing an ion implantation process using the second photoresist mask pattern 114 as an ion implantation mask.

Referring to FIG. 18, a second ashing process is performed to remove the second photoresist mask pattern 1140, and a second gate insulating layer 1420 is formed over the entire pattern.

As described above, the present exemplary embodiment includes a process of forming the active pattern 1200 and the storage electrode pattern 1300, a process of implanting impurity ions into the storage electrode pattern 1300, and a first gate insulating layer on the storage electrode pattern 1300. 1410) The removal process can be performed through a single photolithography process using a single mask to simplify the process. In addition, the first gate insulating layer 1410 may act as a protective layer on the active pattern 1200 to prevent damage to the surface of the active pattern 1200 due to the plasma used in the ashing process.

After removing the second photoresist mask pattern 1140, the second gate insulating film 1420 is coated on the entire structure, and only the second gate insulating film 1420 is disposed on the storage electrode pattern 1300, except for the storage electrode pattern 1300. First and second gate insulating layers 1410 and 1420 are disposed on an area (eg, an active pattern). In this case, the same material film may be used for the first and second gate insulating films 1410 and 1420, or another material film may be used. For example, a silicon oxide film may be used as the first and second gate insulating films 1410 and 1420, a silicon oxide film may be used as the first gate insulating film 1410, and a silicon nitride film may be used as the second gate insulating film 1420. .

In this case, when the thickness of the target gate insulating layers 1410 and 1420 (region thickness between the gate electrode and the channel) is 1, the thickness of the first gate insulating layer 1410 may be 0.1 to 0.9, and the second gate insulating layer The thickness of 1420 may be 0.1 to 0.9. As a result, it is possible to prevent the thickness of the insulating film for the gate electrode used in the thin film transistor from increasing. Here, the first gate insulating layer 1410 prevents damage to the active pattern 1200, and the second gate insulating layer 1420 insulates the gate electrode 1510 from the active pattern 1200. . The second gate insulating layer 1420 serves as a dielectric between the storage electrode pattern 1300 and the storage line 1600. Therefore, the first and second gate insulating layers 1410 and 1420 are not limited to the above descriptions for performing their respective roles, and may have various thickness ranges.

Next, as illustrated in FIG. 11, first and second gate insulating layers 1410 and 1420 are provided on the active pattern 1200, and a second gate insulating layer 1420 is provided on the storage line 1600. The first conductive film is formed on the entire surface of the substrate 110, and the first conductive film is patterned to form the gate line 1500, the gate electrode 1510, and the storage line 1600. In this case, in order to prevent light leakage, the dummy pattern 1520 may be formed together in the boundary region between the pixels.

After the photoresist is coated on the first conductive layer on the second gate insulating layer 1420, the gate line 1500, the gate electrode 1510, the dummy pattern 1520, and the storage line 1600 may be formed through a photolithography process. A photosensitive film mask pattern (not shown) for shielding is formed. Thereafter, an etching process using the photoresist mask pattern as an etching mask is performed to etch the first conductive film in the exposed region, and the photoresist mask pattern is removed.

As a result, the gate line 1500 extending in the horizontal direction, the gate electrode 1510 protruding from the active pattern 1200, and a portion of the gate line 1500 overlapping the gate line 1500 extend in the same direction as the gate line 1500. A storage line 1600 in which the electrode pattern 1300 and a portion thereof overlap, and a dummy pattern spaced apart from the gate line 1500 and the storage line 1600 at a boundary area of the pixel and extending in a direction perpendicular thereto 1520). The width of the dummy pattern 1520 may be variously changed according to the aperture ratio of the pixel. Preferably, the width of the dummy wiring 1520 is 1 to 3 times larger than the line width of the gate line 1500 or the source line 1800. As described above, the light leakage phenomenon in the boundary region of the pixel may be prevented through the dummy pattern 1520. Therefore, a film that serves to prevent light leakage may not be formed on the common electrode substrate corresponding to the thin film transistor substrate.

The gate electrode 1510 includes first and second protrusions protruding from the gate line 1500 as shown in the figure. The first and second protrusions are positioned in the central region of the active pattern 1200, and the first and second gate insulating layers 1410 and 1420 are provided between the first and second protrusions and the active pattern 1200. As illustrated in the drawing, the storage line 1600 includes an extension part connecting the adjacent pixel regions and an electrode part protruding from the extension part and overlapping the storage electrode pattern 1300.

As described above, the gate electrode 1510 is formed and an ion implantation process is performed to form the source region 1220 and the drain region 1230 in the active patterns 1200 at both sides of the gate electrode 1510. The source region 1220 and the drain region 1230 may be formed by implanting N-type or P-type impurity ions into a region extending in a rectangular shape at the end of the active pattern 1200.

After the ion implantation process of the present embodiment, a heat treatment process for activating impurity ions may be further performed.

Next, as shown in FIG. 12, an interlayer insulating film 1700 is formed on the entire surface of the substrate 1100 on which the gate electrode 1510 and the dummy pattern 1520 are formed, and a portion of the interlayer insulating film 1700 is etched. A source contact hole 1820 and a drain contact hole 1910 exposing portions of the source region 1220 and the drain region 1230 are formed. A second conductive film is formed on the entire surface of the interlayer insulating film 1700 having the contact holes 1820 and 1910, and then patterned to form a linear source line 1800 orthogonal to the gate line 1500. A source electrode 1810 protruding from the line 1800 to be connected to the source region 1220 through the source contact hole 1820, and connected to the drain region 1230 through the drain contact hole 1910. A drain electrode 1900 overlapping the storage line 1600 and a portion thereof is formed. Through this, a thin film transistor is manufactured. In the case of the source line 1800, it is effective to overlap the dummy pattern 1520 and a portion thereof. Preferably, the source line 1800 extends inside the dummy pattern 1520 that serves to prevent light leakage.

Next, as shown in FIG. 13, a passivation film 2010 and a passivation film 2000 are formed on the entire surface of the substrate 1100 on which the source electrode 1810 and the drain electrode 1900 are formed, and the passivation film 2010 and the passivation film are formed. A portion of the 2000 is removed to form the pixel contact hole 2110. The pixel electrode 2100 is formed by depositing and patterning a transparent conductive film on the passivation layer 2000 where the pixel contact hole 2110 is formed.

Here, the passivation film 2010 is formed on the entire upper surface of the interlayer insulating film 1700 on which the source line 1800, the source electrode 1810, and the drain electrode 1900 are formed, but it is preferably deposited at a temperature of 300 to 500 degrees Celsius or more. Do. The passivation layer 2010 and the passivation layer 2000 serve to protect the thin film transistor formed under the passivation layer.

The present embodiment is not limited to the above description, and a transflective pattern may be formed on a portion of the pixel electrode. That is, the transflective pattern may be formed in the thin film transistor region and the storage wiring region for the storage capacitor, and a light reflecting film may be formed on the transflective pattern. As a result, the thin film transistor substrate may be used in a transflective liquid crystal display panel.

The thin film transistor and the pixel electrode may be formed on the substrate through the method of the above-described embodiment, and the thin film transistor substrate for the liquid crystal display device may be manufactured using the thin film transistor and the pixel electrode. In the above descriptions, a thin film transistor formed on a thin film transistor substrate used in a liquid crystal display has been described as an example, but the present invention is not limited thereto, and a driving circuit and a pixel of various types of flat panel display devices such as LTPS and OLED may be used. It can be applied to a driving transistor.

In addition, the liquid crystal display panel may be manufactured by bonding and sealing the common electrode substrate to the thin film transistor substrate having the above-described structure and then injecting liquid crystal into the region between the two substrates. In this case, the common electrode substrate is fabricated by forming red, green, and blue color filters on the transparent insulating substrate, and forming a common electrode thereon. In this case, the color filters preferably correspond to pixels of the thin film transistor substrate. In addition, a predetermined spacer may be further formed to maintain a cell gap between the two substrates when the two substrates are bonded to each other. In addition, it is preferable to use sealing members, such as a sealant, for the bonding sealing of two board | substrates.

Of course, the present invention is not limited thereto, and a liquid crystal display may be prepared by preparing a thin film transistor substrate and a common electrode substrate, and then dropping liquid crystal on one substrate, applying a sealing member to the edges of the other substrate, and then sealing the two substrates. .

As described above, the present invention can increase the capacitance of the storage capacitor by reducing the thickness of the upper insulating layer of the storage electrode pattern, and can improve the aperture ratio by reducing the size of the storage electrode pattern.

In addition, the present invention can simplify the manufacturing process by performing the patterning process of the active pattern and the storage electrode pattern and the process of implanting impurity ions into the storage electrode pattern with a single mask.

Although described with reference to the embodiments, it will be understood by those skilled in the art that the present invention may be modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. .

Claims (8)

Forming an active pattern and a storage electrode pattern on the substrate; Forming a gate insulating layer having a thickness thinner on the storage electrode pattern than on the active pattern; And And implanting impurity ions into the storage electrode pattern. The method of claim 1, wherein the forming of the gate insulating layer having a lower thickness above the storage electrode pattern than the thickness above the active pattern is performed. Forming the gate insulating layer on the substrate on which the active pattern and the storage electrode pattern are formed; Forming a photoresist mask pattern exposing an upper region of the storage electrode pattern; And Removing a portion of the gate insulating film in an exposed region. The method of claim 2, wherein implanting impurity ions into the storage electrode pattern is performed. Performing an ion implantation process using the photoresist mask pattern as an ion implantation mask; And Removing the photoresist mask pattern. Forming a silicon thin film and a first gate insulating film on the substrate; Forming an active pattern and a storage electrode pattern by removing the first gate insulating layer and the silicon thin film using a photoresist mask pattern having a height difference; Lowering a height of the photoresist mask pattern to expose a first gate insulating layer on the storage electrode pattern; Removing the exposed first gate insulating layer by using the lowered photoresist mask pattern as an etching mask and an ion implantation mask, and implanting impurities into the storage electrode pattern; Removing the remaining photoresist mask pattern; And Forming a second gate insulating film over the entire structure. The method according to claim 1 or 4, Forming a gate electrode overlapping the active pattern with a portion of the active layer, a gate line connected to the gate electrode in one direction, and a storage line overlapping the storage electrode pattern with a portion of the storage layer; Implanting impurity ions into the active patterns on both sides of the gate electrode to form a source region and a drain region; And And forming an interlayer insulating film on the entire surface of the substrate on which the gate electrode is formed. Board; An active pattern and a storage electrode pattern formed on the substrate and having a source region, a drain region, and a channel region; A gate insulating layer formed on the active pattern and the storage electrode pattern; A gate electrode disposed on the gate insulating layer and overlapping the channel region with a portion thereof; A gate line connected to the gate electrode and extending in one direction; A storage line overlapping the storage electrode pattern; A source electrode connected to the source region; A source line connected to the source electrode and extending in another direction; And A drain electrode connected to the drain region and overlapping the storage line with a portion thereof; The thin film transistor substrate of claim 1, wherein a thickness of the gate insulating layer on the storage electrode pattern is smaller than a thickness of the gate insulating layer on the active pattern. The method according to claim 6, The thickness of the gate insulating layer on the storage electrode pattern when the gate insulating film thickness of the upper portion of the active pattern is set to 1 is 0.1 to 0.9 thin film transistor substrate. The method according to claim 6, At least two or more gate insulating layers are stacked on the active pattern, at least one or more gate insulating layers are stacked on the storage electrode pattern, and a gate insulating layer is stacked on the storage electrode pattern. Thin film transistor substrate thicker than the thickness of the insulating film.

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