KR20080017635A - Fuse in semiconductor device and method for forming the fuse - Google Patents

Abstract

A fuse of a semiconductor device and a forming method of the same are provided to perform a repair process after a package process by using an electrical fuse operated by a high voltage. A plurality of concave parts are formed on a substrate(10). A protrusive part is formed between the concave parts. A field concentration induction layer(17) is buried into the concave parts. An insulating layer(18) is formed on the substrate corresponding to the protrusive part in order to be overlapped with the adjacent concave parts. An electrode(19) is formed on the insulating layer. Edges of both top ends of the adjacent field concentration induction layers come in contact with each other. The insulating layer is broken to disconnect the substrate and the electrode from each other when a high voltage difference is formed between the substrate and the electrode.

Description

Fuse of Semiconductor Device and Formation Method {FUSE IN SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE FUSE}

1 is a cross-sectional view for explaining a fuse and a repair method using the same of another semiconductor device according to an embodiment of the present invention.

2A through 2H are cross-sectional views illustrating a method of forming a fuse according to an exemplary embodiment of the present invention shown in FIG.

<Explanation of symbols for main parts of drawing>

10: substrate

11: pad oxide film

12: pad nitride film

13: antioxidant film

13A: Antioxidation Pattern

15: sacrificial oxide film

16: concave

17: field concentration induction film

18: insulating film

19: electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a repair fuse for a semiconductor device that compensates for defects in the semiconductor device, a repair method for a semiconductor device using the fuse, and a method for forming the fuse.

In the manufacture of semiconductor devices, if any one of a number of fine cells is defective, the semiconductor device does not function as a memory and thus is treated as a defective product. However, even though only some cells in the memory have failed, discarding the entire device as a defective product is an inefficient process in terms of yield. Therefore, a repair operation is performed to replace defective cells by using spare memory cells (hereinafter, referred to as redundancy cells) previously installed in the memory, thereby improving the yield by restoring the entire memory.

In the repair operation using the redundancy cell, a spare low and a spare column are pre-installed for each cell array, so that defective memory cells having defects are replaced with spare memory cells in row / column units. It proceeds in a relaxed manner, which is described in detail as follows.

In other words, when a defective memory cell is selected through a test after wafer processing is completed, a program for changing an address corresponding to the address signal of the spare cell is executed in the internal circuit. Therefore, when an address signal corresponding to a bad line is input in actual use, the selection is switched to a spare line instead. One of the programming methods is a method of burning a fuse with a laser beam and breaking it. The wiring broken by the laser irradiation is called a fuse, and the broken portion and the area surrounding the fuse are called a fuse box. As a result, as the laser is irradiated through the fuse box, the lower fuse is blown.

However, when the repair is performed according to the conventional technology, a problem occurs that the semiconductor device cannot be repaired after the package process is completed. In particular, in the highly integrated semiconductor device that requires a high speed operation, the failure of the semiconductor device is increased after the package process is completed. Thus, a problem that cannot be repaired after the package is completed is a problem to be solved as soon as possible.

Accordingly, an object of the present invention is to provide a fuse and a method of forming the semiconductor device, which can be repaired before and after the packaging process.

According to an aspect of the present invention, a plurality of recesses are formed on a surface thereof, a substrate having protrusions formed between adjacent recesses, and an electric field concentration induction film embedded in the recesses. And an insulating film formed on the substrate of the protruding portion so as to overlap each of the neighboring recesses, and a fuse of the semiconductor device having an electrode formed on the insulating film.

According to another aspect of the present invention, there is provided a substrate having a plurality of recesses formed on a surface thereof, and having a protrusion formed between the adjacent recesses, and buried in the recesses. And forming an insulating film on the substrate so as to overlap each of the neighboring field concentrating films, and forming an electrode on the insulating film. Provided is a method of forming a fuse.

In general, after a FAB (fabrication) process is completed to detect a defect of a semiconductor device, a probe test (probe test1) is performed, and when a defect is detected, a repair test is performed, and after the completion of the package process, a probe test ( Probe test 2) is performed to test the chip defect. However, in the current technology, if a failure occurs in the probe test1, the main cell may be treated using a redundancy cell by cutting the fuse. However, if a failure occurs after the package, there is no way to repair the failure.

Accordingly, the present invention includes an electric fuse in which a repair is performed using a high electric field generated between the substrate and the electrode, so that the repair can be performed not only before the package process but also after the package process.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

1 is a cross-sectional view illustrating a fuse of a semiconductor device and a repairing method using the same according to an embodiment of the present invention.

Referring to FIG. 1, a fuse of a semiconductor device according to an embodiment of the present invention has a structure of an electrode 19 electrically separated from the substrate 10 through an insulating film 11, with the center of the electrode 19 as a starting point. It is provided with a field concentration induction film 17 separated in contact with each other formed in the substrate 10. In particular, the substrate 10 has a protrusion ('E') portion protruding in the form of a peak between neighboring field concentration induction films 17 in order to concentrate the electric field as much as possible at a portion where the area concentration induction films 17 contact each other. ). Preferably, the field concentration induction film 17 abuts on a portion corresponding to the central portion of the electrode 19 so that the electric field is concentrated as much as possible in the substrate 10 corresponding to the central portion of the electrode 19.

Hereinafter, a repair operation using a fuse having such a structure will be briefly described. When a high voltage, for example, a power supply voltage V _DD is applied to the electrode 19 serving as the upper electrode and a ground voltage V _SS is applied to the substrate 10 serving as the lower electrode, the electrode 19 and the substrate 10 are applied. ), A high voltage difference (high electric field) occurs. At this time, a high electric field is concentrated at a portion where the field concentration induction film 17 abuts each other ('E' portion), and the insulating layer 11 at the portion corresponding to the portion is destroyed. As a result, the repair operation is performed while the substrate 10 and the electrode 19 are electrically shorted to each other.

For reference, in order to apply a high voltage to the electrode 19, although not shown in the drawing, a pad for connecting the electrode 19 and the external pins to each other is required. In addition, the pad is again connected with a metal wire electrically connected to the electrode 19. In this case, the pad may add a new pad at a different position from the existing pad or share an existing pad instead of a voltage applying pad required for the operation of the chip. In addition, the high voltage applied through the pad is applied to a specific address through a metal wiring irrespective of driving of the chip to perform repair. Therefore, since the fuse according to the embodiment of the present invention is an electrically operated electrical fuse, the repair operation may be performed not only before the package process but also after the package process.

Hereinafter, a method of forming a fuse according to an exemplary embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS. 2A to 2H.

First, as shown in FIG. 2A, the pad oxide film 11 and the pad nitride film 12 are sequentially deposited on the substrate 10 with the antioxidant film 13.

Subsequently, as shown in FIG. 2B, after the photoresist (not shown) is applied on the pad nitride film 12, an exposure and development process using a photomask is performed to form the photoresist pattern 14. Thereafter, an etching process using the photoresist pattern 14 as a mask is performed to etch the pad nitride film 12 and the pad oxide film 11. As a result, an anti-oxidation film pattern 13A is formed on the substrate 10.

Subsequently, as shown in FIG. 2C, a strip process is performed to remove the photoresist pattern 14 (see FIG. 2B). Thereafter, a sacrificial oxide film 15 is formed on the surface of the substrate 10 exposed by the antioxidant pattern 13A by performing a thermal oxidation process, for example, a LOCOS (LOCal Oxidation of Silicon) process. During the LOCOS process, pattern deformation occurs along the sacrificial oxide film 15 in the anti-oxidation film pattern 13A adjacent to the sacrificial oxide film 15.

Subsequently, as shown in FIG. 2D, an etching process is performed to remove the antioxidant pattern 13A (see FIG. 2C). For example, first, a wet etching process using a phosphoric acid solution (H ₃ PO ₄ ) is performed to remove the pad nitride film 12 (see FIG. 2C), and a wet etching process using a buffered oxide etchant (BOE) is performed to perform a pad oxide film 11. , See FIG. 2C).

Subsequently, as shown in FIG. 2E, the substrate 10 exposed between the sacrificial oxide layers 15 is etched to a predetermined depth (H). Preferably, the substrate 10 is etched to the bottom of the sacrificial oxide film 15 to have the same depth as that of the sacrificial oxide film 15.

Subsequently, as illustrated in FIG. 2F, an etching process is performed to remove the sacrificial oxide film 15 (see FIG. 2E). As a result, a plurality of recesses 16 are formed in the substrate 10. Preferably, the recess 16 has a semicircular shape and both top edges abut each other.

Subsequently, as shown in FIG. 2G, the field concentration induction film 17 is deposited so that the recessed portion 16 is embedded. For example, an oxide film is deposited on the field concentration induction film 17. Then, a planarization process such as chemical mechanical polishing (CMP) and etch-back is performed to perform the field concentration induction film 17. ) Is flattened. As a result, a plurality of electric field concentration induction films 17 are formed in the recesses 16, respectively.

Subsequently, as illustrated in FIG. 2H, a stacked structure of an insulating film 18 and an electrode 19 is formed on the field concentration induction film 17 so that the point where the neighboring field concentration induction film 17 abuts on the center is formed. do. For example, after the insulating film 18 and the electrode 19 are sequentially deposited on the field concentration induction film 17, an etching process using a predetermined photoresist pattern (not shown) is performed to perform the electrode 19 and the insulating film 18. Etch). In this case, the photoresist pattern is used to define the electrode 19 so that the point where the adjacent field concentration induction film 17 abuts each other is the center of the pattern. As a result, a fuse of a type using the substrate 10 as the lower electrode and the electrode 19 as the upper electrode is completed.

For reference, the insulating film 18 may be formed in an ONO (Oxide / Nitride / Oxide) structure or any one film selected from a group of Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ , BaTiO _3, and SrTiO ₃ . . In addition, the electrode 19 may be formed of polysilicon or a metal material.

As such, in the embodiment of the present invention, since the substrate 10 has a sharp pointed protrusion (see 'E' portion) at the portion where the field concentration induction film 17 abuts each other, the field concentration induction film 17 adjacent to each other is formed. Where the electric field is most concentrated. When a high voltage is applied to a fuse having such a structure, for example, a power supply voltage is applied to the electrode 19 and a ground voltage is applied to the substrate 10, a high electric field is generated between the electrode 19 and the substrate 10. In the area where the electric field is concentrated the most, the insulation layer 18 is broken without enduring such a high electric field, and an electrical short between the substrate 10 and the electrode 19 occurs. Through this, the repair of the semiconductor device proceeds.

That is, since the fuse according to the embodiment of the present invention is an electrical fuse electrically operated by a high voltage applied separately, the fuse can be sufficiently repaired not only before the package process but also after the package process.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, by providing an electric fuse that is electrically operated by a high voltage applied separately, it is possible to sufficiently repair after the package process as well as before the package process. Through this, the yield of the semiconductor device may be improved.

Claims (13)

A substrate having a plurality of recesses formed on a surface thereof and a protrusion formed between the adjacent recesses; An electric field concentration induction film embedded in the concave portion; An insulating film formed on the substrate of the protruding portion so as to overlap each of the neighboring concave portions; And An electrode formed on the insulating film A fuse of the semiconductor device having a. The method of claim 1, The field concentration induction film of the fuse of the semiconductor device, characterized in that the neighboring edges of the both sides abut each other. The method according to claim 1 or 2, And the insulating layer breaks down when a high voltage difference is formed between the substrate and the electrode to electrically short the substrate and the electrode. The method according to claim 1 or 2, The insulating film is a fuse of the semiconductor device, characterized in that formed of any one selected from the group of ONO, Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ , BaTiO ₃ and SrTiO ₃ . The method according to claim 1 or 2, The electrode is a fuse of a semiconductor device, characterized in that formed of polysilicon or metal material. Providing a substrate having a plurality of recesses formed on a surface thereof and having protrusions formed between adjacent recesses; Forming a field concentration inducing film embedded in the recess; Forming an insulating film on the substrate of the protrusion so as to overlap each of the neighboring field concentration induction films; And Forming an electrode on the insulating film A fuse forming method of a semiconductor device comprising a. The method of claim 6, The concave portion, Forming an anti-oxidation film pattern on the substrate; Forming a sacrificial oxide film on the substrate exposed due to the antioxidant pattern; Etching the substrate exposed between the sacrificial oxide layers to a predetermined depth; Removing the sacrificial oxide film Method for forming a fuse of the semiconductor device including a. The method of claim 7, wherein Forming the antioxidant pattern is, Sequentially forming a pad oxide film and a pad nitride film on the substrate; And Etching the pad nitride layer and the pad oxide layer A fuse forming method of a semiconductor device comprising a. The method of claim 7, wherein And forming the sacrificial oxide film using a thermal oxidation process. The method according to any one of claims 6 to 9, Etching the substrate to a predetermined depth, And etching the substrate to a lowermost portion of the sacrificial oxide film so as to have the same depth as the sacrificial oxide film. The method according to any one of claims 6 to 9, And the concave portion is formed such that neighboring edges of the concave portion abut each other. The method according to any one of claims 6 to 9, And the insulating film is formed of any one selected from the group of ONO, Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ , BaTiO _3, and SrTiO ₃ . The method according to any one of claims 6 to 9, And the electrode is formed of polysilicon or a metal material.

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