KR20080017594A - Method of fabricating a non-volatile memory cell having a buried n+region and a tunnel insulating layer self-aligned with each other - Google Patents

Abstract

A method for fabricating a non-volatile memory cell having a buried n+ region and a tunnel insulating layer self-aligned with each other are provided to overlap the tunnel insulating layer on a normal position of a burial impurity region by using a spacer. A gate insulating layer(120) is formed on a semiconductor substrate(110). A mask pattern(10) having an opening(12) is formed on the gate insulating layer. A spacer(20) is formed on a sidewall of the opening. A burial impurity region(130) is formed at a lower part of the opening is formed by implanting impurities into the semiconductor substrate by using the mask pattern as an ion implantation mask. A tunnel window(40) for exposing the burial impurity region is formed by etching the gate insulating layer. The mask pattern and the spacer are removed. A tunnel insulating layer is formed on the burial impurity region exposed by the tunnel window. A floating gate layer, a gate interlayer dielectric, and a control gate layer are sequentially formed on the semiconductor substrate having the tunnel insulating layer.

Description

Method of fabricating a non-volatile memory cell having a buried n + region and a tunnel insulating layer self-aligned with each other}

1 to 6 are cross-sectional views sequentially illustrating a method of manufacturing a nonvolatile memory cell according to an exemplary embodiment of the present invention.

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a nonvolatile memory cell having a buried n-type impurity region and a tunnel insulating film self-aligned with each other.

Semiconductor memory devices used to store data may be classified into volatile memory devices or nonvolatile memory cells. The volatile memory devices lose their stored data when the power supplied to them is interrupted. In contrast, the nonvolatile memory cells retain their stored data even if the power supplied to them is interrupted. Therefore, the nonvolatile memory cells, for example, EEPROM (Electrically Erasable and Programmable Read Only Memory) devices are widely used in a memory card or a mobile telecommunication system.

The EEPROM device includes a plurality of memory cells, each of the EEPROM cells having one memory transistor and one selection transistor connected in series. The memory transistor may include an n-type source region n-type buried impurity region formed in a semiconductor substrate. The buried impurity region has a higher impurity concentration than the source region. Furthermore, the memory transistor may include a floating gate, a gate interlayer insulating layer, and a control gate electrode sequentially stacked on a channel region between the source region and the buried impurity region. The floating gate may extend to cover the buried impurity region. Further, a tunnel oxide film thinner than the gate insulating film may be interposed between the floating gate and the buried impurity region.

To program the memory transistor, a ground voltage and a positive program voltage are applied to the buried impurity region and the control gate electrode, respectively. As a result, electrons in the buried impurity region are injected into the floating gate through the tunnel insulating layer to increase the threshold voltage of the memory transistor. On the contrary, in order to erase the memory transistor, a ground voltage and a positive erase voltage are applied to the control gate electrode and the buried impurity region, respectively. In this case, electrons in the floating gate are extracted into the buried impurity region through the tunnel oxide film to reduce the threshold voltage of the memory transistor.

A conventional method of forming an EEPROM cell includes forming the buried impurity region in a predetermined region of the semiconductor substrate, forming the gate insulating film on a semiconductor substrate having the buried impurity region, and patterning the gate insulating film. Forming a tunnel window exposing the buried impurity region, and forming the tunnel oxide film on the exposed buried impurity region. In this case, the tunnel window may be misaligned with the buried impurity region. That is, only a portion of the tunnel window may overlap the buried impurity region. In this case, the program efficiency and / or erase efficiency of the memory transistor may decrease. In particular, as the degree of integration of the EEPROM device increases, the misalignment probability between the tunnel window and the buried impurity region may increase.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a nonvolatile memory cell, in which a tunnel window is self-aligned with a buried impurity region to improve program efficiency and erase efficiency.

According to an aspect of the present invention for achieving the above technical problem, a method of manufacturing a nonvolatile memory cell is provided. The method for manufacturing the nonvolatile memory cell includes forming a gate insulating film on a semiconductor substrate. A mask pattern having an opening is formed on the gate insulating film. Impurities are implanted into the semiconductor substrate using the mask pattern as an ion implantation mask to form a buried impurity region under the opening. The gate insulating layer is etched using the mask pattern and the spacer as etching masks to form a tunnel window exposing the buried impurity region. The mask pattern and the spacer are removed. A tunnel insulating film is formed on the buried impurity region exposed by the tunnel window. A floating gate film, a gate interlayer insulating film, and a control gate film are sequentially formed on the semiconductor substrate having the tunnel insulating film.

The spacer may be formed before or after the buried impurity region is formed.

The spacer may be formed of a material film having an etch selectivity with respect to the mask pattern. The mask pattern may be formed of a silicon nitride film, and the spacer may be formed of a silicon film.

The tunnel insulating layer may be formed of a thermal oxide layer, and the thermal oxide layer of the buried impurity region may be formed to have a thickness thinner than that of the gate insulating layer.

The method may further include forming a memory gate pattern covering the tunnel insulating layer and the gate insulating layer adjacent to the tunnel insulating layer by successively patterning the control gate layer, the gate interlayer insulating layer, and the floating gate layer. Impurities are implanted into the semiconductor substrate using the memory gate pattern as an ion implantation mask so as to contact the buried impurity region and the first impurity region spaced from the buried impurity region and a second opposite to the first impurity region Impurity regions can be formed.

And continuously patterning the control gate layer, the gate interlayer insulating layer, and the floating gate layer to form a memory gate pattern covering the tunnel insulating layer and the gate insulating layer adjacent thereto, and a selection gate pattern adjacent to the memory gate pattern. have. Impurities are implanted into the semiconductor substrate by using the memory gate pattern and the selection gate pattern as ion implantation masks, the first impurity region spaced apart from the buried impurity region, the memory gate pattern and the contact with the buried impurity region A second impurity region positioned between the selection gate patterns and a third impurity region adjacent to the selection gate pattern and spaced apart from the second impurity region may be formed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. Also, an element or layer is referred to as "on" or "on" of another element or layer by interposing another layer or other element in the middle as well as directly above the other element or layer. Include all cases.

1 to 6 are cross-sectional views sequentially illustrating a method of manufacturing a nonvolatile memory cell according to an exemplary embodiment of the present invention.

Referring to FIG. 1, an isolation layer (not shown) defining an active region (not shown) in the semiconductor substrate 110 may be formed, and a gate insulating layer 120 is formed on the semiconductor substrate 110. The gate insulating layer 120 may be formed of a silicon oxide film or a silicon oxynitride film having a thickness of about 250 kV to about 350 kPa. The gate insulating layer 120 may be formed by a process such as Plasma Enhanced Chemical Vapor Deposition (PECVD), High Density Plasma-Chemical Vapor Deposition (HDP-CVD), Atomosphere Pressure Chemical Vapor Deposition (APCVD), or the like.

Subsequently, a mask pattern 10 having an opening 12 exposing a portion of the gate insulating layer 120 is formed on the gate insulating layer 120. The mask pattern 10 may be formed of a silicon nitride film as a hard mask pattern.

Referring to FIG. 2, a spacer layer (not shown) is conformally formed on the mask pattern 10, and the spacer layer (not shown) is anisotropically etched on sidewalls of the opening 12. Spacers 20 are formed. The spacers 20 may be formed of a material different from that of the mask pattern 10 and have an etching selectivity with respect to the gate insulating layer 120. For example, the spacers 20 may be formed of a polysilicon layer.

Next, impurities are implanted into the semiconductor substrate 110 defined by the opening 12, using the mask pattern 10 as an ion implantation mask. As a result, buried impurity regions 130 are formed in the semiconductor substrate 110 corresponding to the openings 12. The buried impurity region 130 may be made of n + type impurities. In addition, the impurities may partially pass through the spacers 20 during the ion implantation 30, so that the buried impurity region 130 may be symmetrically narrowed downward from the surface of the semiconductor substrate 110. Can be.

2, the impurity is implanted into the semiconductor substrate 30 after the spacers 20 are formed. However, the mask pattern 10 is formed in the semiconductor substrate 110. Impurity ion implantation 30 may be used as an ion implantation mask, and then the spacers 20 may be formed. In the latter case, the buried impurity region 130 may have a constant width from the surface to the bottom in the semiconductor substrate 110.

3, the tunnel window 40 exposing the buried impurity region 130 by etching the gate insulating layer 120 using the mask pattern 10 and the spacers 20 as an etch mask. To form. In this case, the etching of the gate insulating layer 120 may be performed by wet etching using an etchant containing hydrofluoric acid.

Referring to FIG. 4, the mask pattern 10 and the spacers 20 are removed. Thereafter, a tunnel insulating layer 140 is formed on the buried impurity region 130 exposed by the tunnel window 40. The tunnel insulating layer 140 may be a thermal oxide film formed by thermally oxidizing the semiconductor substrate 110 in an oxygen atmosphere. In this case, the tunnel insulating layer 140 may further include a step of thermally oxidizing in a nitrogen oxide atmosphere after the above-described thermal oxidation in order to reduce the interface trap density between the semiconductor substrate 110. The thermal oxide film on the buried impurity region 130, that is, the tunnel insulating film 140, may be formed to have a thickness thinner than that of the gate insulating film 120. According to the exemplary embodiment of the present invention, the tunnel insulation layer 140 is formed on the buried impurity region 130 by defining the region where the tunnel insulation layer 140 is to be defined by the spacers (see 20 in FIG. 3). Can be aligned. That is, the tunnel insulating layer 140 may be formed on the buried impurity region 130 without being biased to one side.

Next, referring to FIG. 5, a floating gate film 151, a gate interlayer insulating film 152, and a control gate film 153 are sequentially formed on the semiconductor substrate 110 having the tunnel insulating film 140. The floating gate layer 151 may be a conductive layer, for example, a doped polysilicon layer. The doped polysilicon may be formed by doping in-situ simultaneously with deposition. Alternatively, undoped polysilicon may be formed first and then doped by implanting impurities. The gate interlayer insulating layer 152 may be formed of an silicon oxide / silicon nitride / silicon oxide layer (ONO layer) or a high dielectric layer. In this case, the high-k dielectric film may include aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), lanthanum oxide (LaO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), and titanium oxide (TiO). ), A tantalum oxide film (TaO), or a combination thereof. The control gate layer 153 may be formed of the same conductive layer as the floating gate layer 151 or a different conductive layer. In addition, the control gate film 153 may be formed of a laminated film made of a polysilicon film, a polyside, or a combination thereof.

Referring to FIG. 6, the tunnel insulating layer 140 and the gate insulating layer 120 adjacent thereto are formed by successively patterning the control gate layer 153, the gate interlayer insulating layer 152, and the floating gate layer 151. A covering memory gate pattern 150 and a selection gate pattern 160 adjacent to the memory gate pattern 150 may be formed. The memory gate pattern 150 may sequentially include a control gate pattern 156, a gate interlayer insulating layer pattern 155, and a floating gate pattern 154. The selection gate pattern 160 may include an upper selection gate pattern 166, a gate interlayer insulating layer pattern 164, and a lower selection gate pattern 162 in order from above. In addition, the control gate pattern 156 and the lower selection gate pattern 162 extend across the device isolation layer (not shown) to form sense lines (not shown) and word lines (not shown) in the form of lines, respectively. can do.

Subsequently, first, second and third impurity regions 172, 174, and 176 may be formed in the semiconductor substrate 110. The impurity regions 172, 174, and 176 may be formed by ion implanting n-type impurities using the memory gate pattern 150 and the selection gate pattern 160 as an ion etching mask. As a result, the first impurity region 172 may be formed to be spaced apart from the buried impurity region 130. That is, the first impurity region 172 may be a source region of the memory transistor. The second impurity region 174 may be formed in the semiconductor substrate 110 between the memory gate pattern 150 and the selection gate pattern 160 while contacting the buried impurity region 130. The second impurity region 174 may be electrically connected to the buried impurity region 130. The second impurity region 174 may serve as a drain region of the memory transistor and a source region of the selection transistor. The third impurity region 176 is formed adjacent to the selection gate pattern 160 and spaced apart from the second impurity region 174, and may be a drain region of the selection transistor.

Next, sidewall spacers 180 may be formed on both sides of the memory gate pattern 150 and the selection gate pattern 160.

As described above, according to the present invention, in forming the tunnel insulating film, the tunnel insulating film may be superimposed on the buried impurity region by defining a portion where the tunnel insulating film is to be formed using the spacer. As a result, in the operation of the nonvolatile memory cell, a threshold voltage is applied to the cell at the time of program / erase of the cell, thereby improving program efficiency and erase efficiency.

Claims (7)

Forming a gate insulating film on the semiconductor substrate, Forming a mask pattern having an opening on the gate insulating film, Forming a spacer on the sidewall of the opening, Impurities are implanted into the semiconductor substrate using the mask pattern as an ion implantation mask to form a buried impurity region under the opening; Forming a tunnel window through which the gate insulating layer is etched by using the mask pattern and the spacer as etching masks to expose the buried impurity region; Removing the mask pattern and the spacer, Forming a tunnel insulating film on the buried impurity region exposed by the tunnel window, And sequentially forming a floating gate film, a gate interlayer insulating film, and a control gate film on the semiconductor substrate having the tunnel insulating film. The method of claim 1, And the spacers are formed before or after the buried impurity region is formed. The method of claim 1, And the spacer is formed of a material film having an etch selectivity with respect to the mask pattern. The method of claim 3, wherein And the mask pattern is formed of a silicon nitride film, and the spacer is formed of a silicon film. The method of claim 1, And the tunnel insulating film is formed of a thermal oxide film, and wherein the thermal oxide film of the buried impurity region is formed to have a thickness thinner than that of the gate insulating film. The method of claim 1, Continuously patterning the control gate layer, the gate interlayer insulating layer, and the floating gate layer to form a memory gate pattern covering the tunnel insulating layer and the gate insulating layer adjacent thereto; Implanting impurities into the semiconductor substrate using the memory gate pattern as an ion implantation mask, the first impurity region spaced from the buried impurity region and the first impurity region which is in contact with the buried impurity region and positioned opposite to the first impurity region 2. A method of manufacturing a nonvolatile memory cell, characterized by further comprising forming an impurity region. The method of claim 1, Successively patterning the control gate layer, the gate interlayer insulating layer, and the floating gate layer to form a memory gate pattern covering the tunnel insulating layer and the gate insulating layer adjacent thereto, and a selection gate pattern adjacent to the memory gate pattern, Impurities are implanted into the semiconductor substrate by using the memory gate pattern and the selection gate pattern as ion implantation masks, the first impurity region spaced apart from the buried impurity region, the memory gate pattern and the contact with the buried impurity region And forming a second impurity region located between the select gate patterns and a third impurity region adjacent to the select gate pattern and spaced apart from the second impurity region.

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