KR20080013495A - Image sensor for sharing a read out circuit and method for sharing the read out circuit - Google Patents

Abstract

An image sensor for sharing a read out circuit and a method for sharing the read out circuit are provided to set the operation timing differently to each column by the read out circuit shared by plural columns. A pixel array(100) includes plural unit pixels arrayed as a matrix. A row driver(200) selects a row line of the pixel array. Plural read out circuits(300) are driven by different timing, shared to plural column lines, remove the fixing pattern noise of the unit pixel, and change an analog image signal into a digital image signal. Plural line memories store the image information of at least two or more lines of column lines of the pixel array outputted from the read out circuits. A column decoder(700) decodes the column direction address signal and outputs the image information stored in the line memories corresponding to the column line in response to the decoded address signal. Each unit pixel includes a photo diode for generating optical charges in response to the optical image of an object.

Description

Image sensor for sharing a read out circuit and method for sharing the read out circuit}

1 is a block diagram illustrating a general image sensor.

2 is a block diagram illustrating an image sensor according to the present invention.

FIG. 3 is a detailed circuit diagram showing two unit pixels 110 (n) and 110 (n + 1) respectively connected to two columns sharing one CDS circuit 310 and an ADC 410 shown in FIG. to be.

FIG. 4 is a timing diagram illustrating an operation of two unit pixels 110 (n) and 110 (n + 1) shown in FIG. 3.

5 is another embodiment of two unit pixels 110 (n) and 110 (n + 1), each connected to two columns sharing one CDS circuit 310 and ADC 320 shown in FIG. A detailed circuit diagram is shown.

FIG. 6 is a timing diagram illustrating an operation of two unit pixels 110 (n) and 110 (n + 1) shown in FIG. 5.

7 is a block diagram illustrating another embodiment of an image sensor according to the present invention.

8A and 8B are detailed circuit diagrams illustrating the shared unit pixel 130 illustrated in FIG. 7.

FIG. 9 is a timing diagram illustrating an operation of the sharing unit pixel 130 illustrated in FIG. 8A.

10 is a block diagram showing another embodiment of an image sensor according to the present invention.

<Explanation of symbols for main parts of the drawings>

100, 101, 102: pixel array

110 (n), 110 (n + 1): unit pixels

111 (n), 111 (n + 1), 131 (n), 131 (n + 1), 141 (n), 141 (n + 1), 141 (n1), 141 (n1 + 1): photodiode

112 (n), 112 (n + 1), 132 (n), 132 (n + 1), 142 (n), 142 (n + 1), 142 (n1), 142 (n1 + 1): transfer transistor

113 (n), 113 (n + 1), 133, 143: reset transistor

114 (n), 114 (n + 1), 134, 144: driving transistor

115 (n), 115 (n + 1), 135, 145: select transistor

130: shared unit pixels

137 (n), 137 (n + 1): fractional pixel

200, 201, 202: Low Driver

300, 301, 302 (n), 302 (n + 1): lead out circuit

310, 311: CDS circuit

320, 321: ADC

500, 501, 502 (n), 502 (n + 1): analog control block

600, 601, 602 (n), 602 (n + 1): line memory block

610 (n), 610 (n + 1), 630 (n), 630 (n + 1): line memory

700, 701, 702 (n), 702 (n + 1): column decoder

800: the first switch block

810: first switch means

900, 901, 902 (n), 902 (n + 1): second switch block

910, 930: second switch means

The present invention relates to an image sensor, and more particularly to a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

An image sensor is a device that converts external optical information into an electrical signal. The unit pixel of the image sensor generates an electrical value corresponding to the light energy generated by the subject. In particular, the CMOS image sensor is a device for converting an optical image into an electrical signal using a CMOS manufacturing technology, and uses a method of outputting the charge accumulated in each unit pixel as a voltage.

1 is a block diagram illustrating a general image sensor.

Typical image sensors include a pixel array 10, a row driver 20, a read out circuit 30, an analog control block 50, a line memory 60, and a column decoder 70. Here, the readout circuit 30 includes a plurality of CDS circuits (Correlated Double Sampling) 31 and a plurality of Analog to Digital Converters (ADCs) 32.

The pixel array 10 includes a plurality of unit pixels 11 arranged in a matrix.

The row driver 20 selects a row line of the pixel array 10.

The CDS circuit 31 removes fixed pattern noise of the unit pixel 11, and the ADC 32 converts the analog video signal output from the corresponding CDS circuit 31 into a digital video signal. .

The analog control block 50 controls the operation of the readout circuit 30.

The line memory block 60 includes a plurality of line memories 61, and each line memory 61 stores image information of a corresponding column line of the pixel array 10. Here, each line memory 61 may be composed of two latches for sequentially storing pixel information of two row lines.

The column decoder 70 decodes the address signal in the column direction and outputs pixel information stored in the line memory 61.

Referring to FIG. 1, in the general image sensor, one CDS circuit 31, one ADC 32, and one line memory 61 are connected through one column bus per one unit pixel 11.

Therefore, when the pitch of the unit pixels 11 decreases, the area where the corresponding CDS circuit 31, the ADC 32, and the line memory 60 should be formed is also reduced. To solve this problem, designing circuits arranged in a column direction increases the overall chip size by forming chips long in the column direction.

If the pitch of the unit pixel 11 becomes smaller, in the worst case, it becomes impossible to implement capacitors and amplifiers constituting the CDS circuit 31 and the ADC 32 in a given pitch.

The present invention has been made to solve the above problems, and an object thereof is to reduce a chip area by sharing a readout circuit with a certain number of columns.

The present inventors have found that the readout circuit can be shared by multiple columns to effectively solve the above problem and completed the present invention.

First, an image sensor according to the present invention includes a pixel array including a plurality of unit pixels arranged in a matrix;

A row driver to select a row line of the pixel array;

A plurality of read-out circuits driven at different timings and shared by a plurality of column lines, removing fixed pattern noise of the unit pixel, and converting an analog image signal into a digital image signal;

A plurality of line memories for storing image information of at least two or more row lines of the column lines of the pixel array output from the readout circuit;

And a column decoder for decoding the address signal in the column direction and outputting image information stored in the line memory corresponding to the column line corresponding to the decoded address signal.

In addition, the image sensor according to the invention is a matrix array, the pixel array comprising a plurality of unit shared pixels, wherein the unit pixels including the photodiode and the transfer transistor comprises a reset transistor, a driving transistor and a selection transistor;

A row driver to select a row line of the pixel array;

A plurality of read-out circuits for removing fixed pattern noise of the unit pixel and converting an analog image signal into a digital image signal;

A plurality of line memories for storing image information of at least two row lines of the column lines of the pixel array output from the readout circuit at different timings;

And a column decoder for decoding the address signal in the column direction and outputting image information stored in the line memory of the column line corresponding to the decoded address signal.

Meanwhile, in the method of sharing the readout circuit of the image sensor according to the present invention, a plurality of column lines are connected to one readout circuit at different timings so that the plurality of column lines share one readout circuit. In the out-circuit sharing method,

Driving the readout circuit at different timings;

Storing image data processed by the readout circuit in a plurality of memories at different timings; And

And outputting the stored image data.

In addition, the method of sharing the readout circuit of the image sensor according to the present invention is a method of sharing a readout circuit of an image sensor in which a plurality of column lines share one readout circuit,

Driving the readout circuit at different timings;

Storing image data processed by the readout circuit in a plurality of memories at different timings; And

And outputting the stored image data.

Meanwhile, the present invention is applicable to both shared pixel structures and non-shared pixel structures.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in various forms by those skilled in the art within the scope of the claims. Like numbers refer to like elements throughout the specification.

2 is a block diagram illustrating an image sensor according to the present invention. Here, the case where two columns share one read out circuit (CDS circuit and ADC) will be described as an example. However, a plurality of columns may share one read out circuit as needed.

The image sensor according to the present invention includes a pixel array 100, a row driver 200, a first selection switch block 800, a readout circuit 300, a second selection switch block 900, and an analog control block 500. , A line memory block 600 and a column decoder 700. Here, the readout circuit 300 includes a plurality of correlated double sampling (CDS) circuits 310 and a plurality of analog to digital converters (ADCs) 320.

The pixel array 100 includes a plurality of unit pixels 110 (n) and 110 (n + 1) arranged in a matrix.

The row driver 200 selects a row line of the pixel array 100.

The CDS circuit 310 of the readout block 300 removes fixed pattern noise of the unit pixel 110, and the ADC 320 outputs an analog image signal output from the corresponding CDS circuit 310. To convert the digital video signal.

The analog control block 500 controls the operation of the readout circuit 300.

The line memory block 600 includes a plurality of line memories 610 (n) and 610 (n + 1), and each line memory 610 (n) and 610 (n + 1) includes a pixel array 100. First and second latches 611 (n), 612 (n), 611 (n + 1), and 612 (n + 1) respectively storing image information of two row lines of a column of Include.

The column decoder 700 decodes the address signal in the column direction, and the second latch 612 (n) of the line memories 610 (n) and 610 (n + 1) corresponding to the column line corresponding to the decoded address signal. ), And outputs image information stored in 612 (n + 1).

The first selection switch block 800 includes a plurality of switch means 810, each switch means 810 sharing a corresponding column line in response to an even switching signal ES or an odd switching signal OS. 300).

The second switch block 900 includes a plurality of switch means 910, each switch means 910 outputs the output of the corresponding ADC 410 in response to the even switching signal ES and the odd switching signal OS. To 600.

FIG. 3 shows two unit pixels 110 (n) and 110 (n + 1) respectively connected to two column lines sharing one CDS circuit 310 and ADC 410 shown in FIG. Detailed circuit diagram. Here, an example in which two column lines share one read out circuit (CDS circuit 310 and ADC 410) will be described as an example. However, as required, a plurality of column lines may use one read out circuit (CDS circuit). A structure that shares 310 and ADC 410 may be used.

The even unit pixel 110 (n) includes a photodiode 111 (n), a transfer transistor 112 (n), a reset transistor 113 (n), a driving transistor 114 (n) and a selection transistor 115 (n)). The photodiodes 111 (n) generate photocharges corresponding to the optical image of the subject.

The transfer transistor 112 (n) floats the photocharge generated by the corresponding photodiode 111 (n) in response to the even transmission signal TX (n), respectively, 116 (n). Transmit each).

The reset transistor 113 (n) discharges the electric charge stored in the floating diffusion node 116 (n), respectively, in response to the even reset signal RT (n) for the detection of the next image information.

The driving transistor 114 (n) serves as a source follower.

The select transistor 115 (n) may perform addressing by switching in response to the select signal LS.

The odd unit pixel 110 (n + 1) includes a photodiode 111 (n + 1), a transfer transistor 112 (n + 1), a reset transistor 113 (n + 1), and a driving transistor 114 ( n + 1) and a select transistor 115 (n + 1).

The photodiode 111 (n + 1) generates photocharges corresponding to the optical image of the subject.

The transfer transistor 112 (n + 1) floats the photocharge generated by the corresponding photodiode 111 (n + 1) in response to the odd transfer signal TX (n + 1). Send to (116 (n + 1)).

The reset transistor 113 (n + 1) discharges the charge stored in the floating diffusion node 116 (n + 1) in response to the odd reset signal RT (n + 1) for the detection of the next image information. .

The driving transistor 114 (n + 1) serves as a source follower.

The selection transistor 115 (n + 1) may perform addressing by switching in response to the selection signal LS.

Here, the same select signal LS is applied to the two select transistors 115 (n) and 115 (n + 1).

To apply the same exposure time to each of the two unit pixels 110 (n) and 110 (n + 1), odd / even reset signals RT (n), RT (n + 1) and odd / even The signal TX (n) and TX (n + 1) are respectively applied to the two unit pixels 110 (n) and 110 (n + 1) at different timings so that the two unit pixels 110 (n), 110 (n + 1) is reset at different timings and transmits image information at different timings. On the other hand, the selection signal LS is shared by two unit pixels 110 (n) and 110 (n + 1).

FIG. 4 is a timing diagram illustrating an operation of two unit pixels 110 (n) and 110 (n + 1) shown in FIG. 3.

When the even transmission signal TX (n) becomes high level while the even reset signal RT (n) is high level, the even unit pixel 110 (n) connected to the even column line CL (n) is reset. (T11), and after a certain time, when the odd transmission signal TX (n + 1) becomes high level with the odd reset signal RT (n + 1) being high level, the odd column line CL (n + 1 The odd unit pixel 110 (n + 1) connected to the &lt; RTI ID = 0.0 &gt;) is reset (t12).

In addition, the two photodiodes 111 (n) and 111 (n + 1) perform exposure operations until the even / odd transmission signals TX (n) and TX (n + 1) go from low level to high level again. Do this. Here, an integration time ET (n) and an odd column line CL (n + 1) of the even unit pixel 110 (n) connected to the even column line CL (n) are connected. The exposure time ET (n + 1) of the unit pixel 110 (n + 1) is set the same.

When the selection signal LS and the even switching signal ES are at the high level and the even reset signal RT (n) is at the low level, the reference of the even unit pixel 110 (n) connected to the even column line CL (n) is satisfied. A reference signal is read (t13).

When the even transmission signal TX (n) becomes high again, the photocharge stored in the photodiode 111 (n) is transmitted to the floating diffusion node 116 (n). Then, when the even transmission signal TX (n) becomes low level, the data stored in the floating diffusion node 116 (n) is output to the even column line CL (n) (t14). Subsequently, the CDS circuit 310 performs correlated double sampling (CDS) on the image signal on the even column line CL (n), and the ADC 320 converts the analog image signal subjected to CDS into a digital image signal. The first latch 611 (n) of the even-line memory 610 (n) stores a digital video signal. Thereafter, when the next low line digital image signal is input, the digital image signal stored in the first latch 611 (n) of the even-line memory 610 (n) is transmitted to the second latch 612 (n). The input digital video signal is stored in the first latch 611 (n).

On the other hand, when the odd switching signal OS becomes high level and the odd reset signal RT (n + 1) becomes low level while the selection signal LS maintains the high level, the unit pixel 110 corresponding to the odd column 110 (n A reference signal of +1)) is read (t15).

When the odd transmission signal TX (n + 1) becomes high again, the photocharge stored in the photodiode 111 (n + 1) is transmitted to the floating diffusion node 116 (n + 1). Subsequently, when the odd transmission signal TX (n + 1) becomes low level, data stored in the floating diffusion node 116 (n + 1) is output to the odd column line CL (n + 1) (t16). .

Subsequently, the CDS circuit 310 performs correlated double sampling (CDS) on the image signal carried on the odd column line CL (n + 1), and the ADC 320 converts the analog image signal subjected to CDS into a digital image signal. The first latch 611 (n + 1) of the odd line memory 610 (n + 1) stores a digital video signal. Subsequently, when the next low line digital image signal is input, the digital image signal stored in the first latch 611 (n + 1) of the odd line memory 610 (n + 1) is converted to the second latch 612 (n). +1)), and the input digital video signal is stored in the first latch 611 (n + 1).

5 is another of two unit pixels 120 (n) and 120 (n + 1) respectively connected to two column lines sharing one CDS circuit 310 and ADC 320 shown in FIG. Detailed circuit diagram showing an embodiment. Here, an example in which two column lines share one read out circuit (CDS circuit 310 and ADC 410) will be described as an example. However, as required, a plurality of column lines may use one read out circuit (CDS circuit). A structure that shares 310 and ADC 320 may be used.

The even-numbered pixel 120 (n) includes a photodiode 121 (n), a transfer transistor 122 (n), a reset transistor 123 (n), a driving transistor 124 (n) and a selection transistor 125 (n)).

The photodiode 121 (n) generates photocharges corresponding to the optical image of the subject.

The transfer transistor 122 (n) transfers the photocharge generated at the photodiode 121 (n) to the floating diffusion node 126 (n) in response to the even transmission signal TX (n). send.

The reset transistor 123 (n) discharges the charge stored in the floating diffusion node 126 (n) in response to the same reset signal RT to detect the next image information.

The driving transistor 124 (n) serves as a source follower.

The odd pixel 120 (n + 1) includes a photodiode 121 (n + 1), a transfer transistor 122 (n + 1), a reset transistor 123 (n + 1), and a driving transistor 124 ( n + 1) and a select transistor 125 (n + 1).

The photodiode 121 (n + 1) generates photocharges corresponding to the optical image of the subject.

The transfer transistor 122 (n + 1) floats the photocharge generated in the corresponding photodiode 121 (n + 1) in response to the odd transfer signal TX (n + 1). Send to (126 (n + 1)).

The reset transistor 123 (n + 1) discharges the electric charge stored in the floating diffusion node 126 (n + 1) in response to the reset signal RT to detect the next image information.

The driving transistor 124 (n + 1) serves as a source follower.

The select transistor 125 (n + 1) may perform addressing by switching in response to the select signal LS.

Here, the same selection signal LS is applied to the two selection transistors 125 (n) and 125 (n + 1).

In order to apply the same exposure time to each of the two unit pixels 120 (n) and 120 (n + 1), the odd / even transmission signals TX (n) and TX (n + 1) have different timings. Applied to each of the two unit pixels 120 (n) and 120 (n + 1), the two unit pixels n and 120 (n + 1) are sequentially reset and sequentially transmit image information. . On the other hand, the selection signal LS is shared by two unit pixels 120 (n) and 120 (n + 1).

FIG. 6 is a timing diagram illustrating an operation of two unit pixels 120 (n) and 120 (n + 1) shown in FIG. 5.

When the reset signal RT is at the high level, when the even transmission signal TX (n) is at the high level, the unit pixel 120 (n) connected to the even column line CL (n) is reset (t21), and for a predetermined time. Later, when the odd transmission signal TX (n + 1) becomes high level, the unit pixel 120 (n + 1) connected to the odd column line CL (n + 1) is reset (t22).

Further, the two photodiodes 121 (n) and 121 (n + 1) are exposed to operation until the even / odd transmission signals TX (n) and TX (n + 1) go from low level to high level again. Do this. Here, the exposure time ET (n) of the unit pixel 120 (n) connected to the even column line CL (n) and the unit pixel 120 (n + 1) corresponding to the odd column line CL (n + 1) The integration time ET (n + 1) is set equally.

When the selection signal LS and the even switching signal ES become high level and the reset signal RT becomes low level, the reference signal of the unit pixel 120 (n) connected to the even column line CL (n) becomes Lead (t23).

When the even transmission signal TX (n) becomes high again, the photocharge stored in the photodiode 121 (n) is transmitted to the floating diffusion node 126 (n). Then, when the even transmission signal TX (n) becomes low level, the data stored in the floating diffusion node 126 (n) is output to the even column line CL (n) (t24).

Subsequently, the CDS circuit 310 performs correlated double sampling (CDS) on the image signal on the even column line CL (n), and the ADC 320 converts the analog image signal subjected to CDS into a digital image signal. The first latch 611 (n) of the even line memory 610 (n) stores a digital image signal. Thereafter, when the next low line digital image signal is input, the digital image signal stored in the first latch 611 (n) of the even-numbered line memory 610 (n) is transmitted to the second latch 612 (n). The input digital video signal is stored in the first latch 61 (n).

On the other hand, when the odd switching signal OS becomes high level and the reset signal RT becomes low level while the selection signal LS maintains the high level, the reference of the unit pixel 120 (n + 1) corresponding to the odd column A reference signal is read (t25).

When the odd transmission signal TX (n + 1) becomes high again, the photocharge stored in the photodiode 121 (n + 1) is transmitted to the floating diffusion node 126 (n + 1). Then, when the odd transmission signal TX (n + 1) becomes low level, the data stored in the floating diffusion node 126 (n + 1) is output to the odd column line CL (n + 1) (t26).

Subsequently, the CDS circuit 310 performs correlated double sampling (CDS) on the image signal on the odd column line CL (n + 1), and the ADC 320 converts the analog image signal subjected to CDS into a digital image signal. The first latch 611 (n + 1) of the odd line memory 610 (n + 1) stores the digital video signal. Subsequently, when the next low line digital image signal is input, the digital image signal stored in the first latch 611 (n + 1) of the odd line memory 610 (n + 1) is transferred to the second latch 612 (n). +1)), and the input digital video signal is stored in the first latch 611 (n + 1).

7 is a block diagram illustrating another embodiment of an image sensor according to the present invention.

The image sensor according to the present invention includes a pixel array 101, a readout circuit 301, a row driver 201, a second selection switch block 901, an analog control block 501, a line memory block 601 and a column. Decoder 701 is included. Here, the readout circuit 301 includes a correlated double sampling (CDS) circuit 311 and an analog to digital converter (ADC) 321.

The pixel array 101 includes a plurality of shared unit pixels 130 arranged in a matrix.

The row driver 201 selects a row line of the pixel array 101.

The CDS circuit 311 removes fixed pattern noise of the shared unit pixel 130.

The ADC block 321 converts the analog video signal output from the corresponding CDS circuit 311 into a digital video signal.

The analog control block 501 controls the operation of the read out circuit 301.

The line memory block 601 includes a plurality of line memories 630 (n) and 630 (n + 1), and each line memory 630 (n) and 630 (n + 1) includes a pixel array 101. First and second latches 631 (n), 632 (n), 631 (n + 1), and 632 (n + 1), respectively, for storing image information of two row lines of a column line It includes.

The column decoder 701 decodes the address signal in the column direction, and the second latch 632 (n) of the line memory 630 (n) or 630 (n + 1) corresponding to the column line corresponding to the decoded address signal. ), And outputs the video information stored in 632 (n + 1).

The second switch block 901 includes a plurality of switch means 930, and each switch means 930 supplies the output of the corresponding ADC 321 in response to the even / odd switching signal ES / OS. 601).

8A and 8B are detailed circuit diagrams illustrating the shared unit pixel 130 illustrated in FIG. 7. FIG. 8A shows a structure in which two unit pixels 137 (n) and 137 (n + 1) share the reset transistor 133, the driving transistor 134, and the selection transistor 135, and FIG. 8B shows four structures. The unit pixel 147 (n), 147 (n + 1), 147 (n1), and 147 (n1 + 1) share a structure in which the reset transistor 143, the driving transistor 144, and the selection transistor 145 share a common structure. Indicates.

First, referring to FIG. 8A, in the shared unit pixel 130, two unit pixels 137 (n) and 137 (n + 1) may include a reset transistor 133, a driving transistor 134, and a selection transistor 135. It is a shared structure. Here, each of the unit pixels 137 (n) and 137 (n + 1) includes photodiodes 131 (n) and 131 (n + 1) and transfer transistors 132 (n) and 132 (n + 1). It includes.

The photodiodes 131 (n) and 131 (n + 1) generate photocharges corresponding to the optical image of the subject.

The transfer transistors 132 (n) and 132 (n + 1) are photodiodes 131 (n) and 131 (n +) in response to the even / odd transmission signals TX (n) and TX (n + 1), respectively. The photocharge generated in 1)) is transmitted to the floating diffusion node 136.

The reset transistor 133 discharges the charge stored in the floating diffusion node 136 in response to the reset signal RT to detect the next image information.

The driving transistor 134 may serve as a source follower, and the selection transistor 135 may perform addressing by switching in response to the selection signal LS.

In order to apply the same exposure time to each of the two unit pixels 137 (n) and 137 (n + 1), the reset signal RT and the odd / even transmission signal TX (n), TX (n + 1) It is applied to each of the two unit pixels 137 (n) and 137 (n + 1) at different timings so that the two unit pixels 137 (n) and 137 (n + 1) are sequentially reset and sequentially Transmits video information.

Referring to FIG. 8B, four unit pixels 147 (n), 147 (n + 1), 147 (n1), and 147 (n1 + 1) are driven by the reset transistor 143. The transistor 144 and the selection transistor 145 are shared. Here, each of the unit pixels 147 (n), 147 (n + 1), 147 (n1), and 147 (n1 + 1) is a photodiode 141 (n), 141 (n + 1), and 141 (n1), respectively. , 141 (n1 + 1) and transfer transistors 142 (n), 142 (n + 1), 142 (n1), and 142 (n1 + 1). The operation of the sharing unit pixel 140 illustrated in FIG. 8B is similar to that of the sharing unit pixel 130 illustrated in FIG. 8A, and thus a detailed description thereof will be omitted.

FIG. 9 is a timing diagram illustrating an operation of the sharing unit pixel 130 illustrated in FIG. 8A.

With the reset signal RT at the high level, when the even transmission signal TX (n) is at the high level, the even unit pixel 137 (n) is reset (t31), and after a certain time, the reset signal RT is at the high level. When the odd transmission signal TX (n + 1) becomes a high level, the odd unit pixel 120 (n + 1) is reset (t32).

In addition, the two photodiodes 131 (n) and 131 (n + 1) are exposed to operation until the even / odd transmission signals TX (n) and TX (n + 1) go from low level to high level again. Do this. Here, the integration time of the even unit pixel 137 (n) and the odd unit pixel 137 (n + 1) is set to be the same.

When the selection signal LS and the even switching signal ES become high level and the reset signal RT becomes low level, a reference signal of the even unit pixel 137 (n) is read (t33).

When the even transmission signal TX (n) becomes high again, the photocharge stored in the photodiode 131 (n) is transmitted to the floating diffusion node 136 (n). Then, when the even transmission signal TX (n) becomes low level, the data stored in the floating diffusion node 136 (n) is output to the column line CL.

Subsequently, the CDS circuit 311 performs correlated double sampling (CDS) on the image signal loaded on the column line CL, and the ADC 321 converts the analog image signal subjected to CDS into a digital image signal, and the even line memory ( The first latch 631 (n) of 630 (n) stores a digital video signal. Subsequently, when the next low line digital image signal is input, the digital image signal stored in the first latch 631 (n) of the even-numbered line memory 630 (n) is transmitted to the second latch 632 (n). The input digital video signal is stored in the first latch 631 (n). On the other hand, the odd switching signal OS is at the high level while the selection signal LS is at the high level, and the reset signal RT is at the low level. In this case, a reference signal of the odd unit pixel 137 (n + 1) is read.

When the odd transmission signal TX (n + 1) becomes high again, the photocharge stored in the photodiode 131 (n + 1) is transmitted to the floating diffusion node 136 (n + 1). Then, when the odd transmission signal TX (n + 1) becomes low level, the data stored in the floating diffusion node 136 (n + 1) c is output to the column line CL.

Subsequently, the CDS circuit 311 performs correlated double sampling (CDS) on the image signal loaded on the column line CL, and the ADC 321 converts the analog image signal performed on the CDS into a digital image signal and uses an odd line memory ( The first latch 631 (n + 1) of 630 (n + 1) stores a digital video signal. Subsequently, when the digital image signal of the next low line is input, the digital image signal stored in the first latch 631 (n + 1) of the odd line memory 631 (n + 1) is transferred to the second latch 632 (n). +1)), and the input digital video signal is stored in the first latch 631 (n + 1).

10 is a block diagram showing another embodiment of an image sensor according to the present invention.

The image sensor according to the present invention includes a readout circuit 302 (n) and 302 (n + 1) corresponding to even / odd columns at the top and bottom of the pixel array 102, and the second selection switch block 902. (n), 902 (n + 1), line memory blocks 602 (n), 602 (n + 1), and column decoders 702 (n), 702 (n + 1) are disposed and a row driver The 202 and the analog control block 502 are disposed on the left or the right side with respect to the pixel array 102. Here, the readout circuits 30 (n) and 302 (n + 1) include a plurality of correlated double sampling (CDS) circuits 312 and a plurality of analog to digital converters (ADCs) 322. In FIG. Since the illustrated image sensor operates similarly to the image sensor illustrated in FIG. 7, detailed description thereof will be omitted herein.

In the present invention, a plurality of columns share a readout circuit (CDS circuit, ADC, etc.) using a large hold capacitor and a sampling capacitor, and the readout circuit operates timing for each column. By setting differently, the chip area can be reduced.

As described above, the image sensor according to the present invention has an effect of reducing the chip area by sharing a readout circuit with a certain number of columns.

Claims (21)

A pixel array including a plurality of unit pixels arranged in a matrix; A row driver to select a row line of the pixel array; A plurality of read-out circuits driven at different timings and shared by a plurality of column lines, removing fixed pattern noise of the unit pixel, and converting an analog image signal into a digital image signal; A plurality of line memories for storing image information of at least two or more row lines of the column lines of the pixel array output from the readout circuit; And a column decoder for decoding the address signal in the column direction and outputting image information stored in the line memory corresponding to the column line corresponding to the decoded address signal. The method of claim 1, wherein each unit pixel is A photodiode for generating a photocharge corresponding to the optical image of the subject; A transfer transistor for transmitting the photocharge generated by the photodiode to a floating diffusion node in response to a transmission signal; A reset transistor for discharging charge stored in the floating diffusion node in response to a reset signal for detecting next image information; A driving transistor serving as a source follower; And And a selection transistor for performing addressing with switching in response to the selection signal. The method of claim 2, A unit pixel connected to each column is applied with a reset signal and a transmission signal at different timings, respectively, and resets at a different timing for each of the plurality of column lines, and transmits image information at different timings. An image sensor characterized by applying the same exposure time. The method of claim 2, And the selection signal is shared to the plurality of unit pixels. The method of claim 2, The reset signal is shared with the plurality of unit pixels. The circuit of claim 1, wherein the readout circuit A plurality of CDS circuits for removing fixed pattern noise of the unit pixels; And And a plurality of ADCs for converting the analog video signal output from the corresponding CDS circuit into a digital video signal. The method of claim 1, And an analog control block for controlling the operation of the readout circuit to drive at different timings for the respective columns. The method of claim 1, And said line memory comprises a plurality of latch means for sequentially storing image information of at least two row lines. The method of claim 1, A plurality of first selection switch means for connecting a column line selected from a shared column line to the readout circuit in response to a switching signal; And And a plurality of second switch means for transmitting the output of the readout circuit to the line memory in response to the switching signal. A method of sharing a readout circuit of an image sensor in which a plurality of column lines are connected to one read out circuit, so that the plurality of column lines share one read out circuit, Converting an optical image of the subject into image information; Driving the readout circuit at different timings; Storing image data processed by the readout circuit in a plurality of line memories at different timings; And Outputting the stored image data; and sharing the readout circuit of the image sensor. 11. The method of claim 10, wherein converting Resetting unit pixels connected to the plurality of column lines at different timings for each of the plurality of column lines; Reading a reference signal at different timings for each of the plurality of columns of the unit pixels connected to the plurality of columns; Transmitting the photocharge stored in the photodiode to the floating diffusion node; And And outputting image data stored in the floating diffusion node. The method of claim 11, And applying the same exposure time to the unit pixels connected to the plurality of column lines. A pixel array arranged in a matrix, the plurality of unit pixels including a photo diode and a transfer transistor comprising a plurality of unit shared pixels sharing a reset transistor, a driving transistor, and a selection transistor; A row driver to select a row line of the pixel array; A plurality of read-out circuits for removing fixed pattern noise of the unit pixel and converting an analog image signal into a digital image signal; A plurality of line memories for storing image information of at least two row lines output from the readout circuit at different timings; And a column decoder for decoding the address signal in the column direction and outputting image information stored in the line memory corresponding to the column line corresponding to the decoded address signal. The method of claim 13, In order to apply the same exposure time to each of the unit pixels, a reset signal and a transmission signal are respectively applied at different timings, reset at different timings, and transmit image information at different timings. The method of claim 13, And an analog control block for controlling the operation of the readout circuit to drive at different timings for the respective columns. The method of claim 13, And said plurality of read out circuits, said plurality of second switch means, said plurality of memory and column decoders are alternately arranged above and below said pixel array. The method of claim 13, And said line memory comprises a plurality of latch means for sequentially storing image information of at least two row lines. The method of claim 13, And a plurality of switch means for transmitting the output of said read out circuit to a corresponding said line memory in response to a switching signal. A method of sharing a readout circuit of an image sensor in which a plurality of column lines share one readout circuit, Converting an optical image of a subject into image information; driving the readout circuit at different timings; Storing image data processed by the readout circuit in a plurality of line memories at different timings; And Outputting the stored image data; and sharing the readout circuit of the image sensor. 20. The method of claim 19, wherein converting Resetting the shared unit pixels connected to the plurality of column lines at different timings for the plurality of column lines; Reading a reference signal at different timings for each of the plurality of column lines of a shared unit pixel connected to the plurality of column lines; Transmitting photocharges stored in the plurality of photodiodes to the floating diffusion node at different timings; And And outputting image data stored in the floating diffusion node. The method of claim 19, And applying the same exposure time to the plurality of shared unit pixels.

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