KR20040105454A - Image sensor and method for controlling data readout - Google Patents

Abstract

PURPOSE: A CMOS image sensor is provided to simplify its logic and reduce path offset due to a data readout path by reducing the number of analog-to-digital converter blocks or latch circuits. CONSTITUTION: A CMOS image sensor(200) includes a pixel array(210) provided with a plurality pixels, a plurality of switching means(232,234) respectively connected to odd numbered rows and even numbered rows of the pixel array, performing their switching function, a plurality of analog-to-digital converter blocks(222,224,226) connected to a pair of the switching means corresponding to the odd and even numbered rows, and latch blocks(240) outputting digital data corresponding to a video signal of the pixels after storing the digital data received from the analog-to-digital converter blocks of the odd numbered rows or the even numbered rows. The switching means are synchronized by an externally input clock signal and are activated to select the odd numbered rows or the even numbered rows. The analog-to-digital converter blocks include a correlated double sampling block sampling the video signal sensed from the pixels, an amplifier amplifying the sampled video signal, and an analog-to-digital converter converting the amplified signal into digital data.

Description

IMAGE SENSOR AND METHOD FOR CONTROLLING DATA READOUT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS image sensor (CIS), and more particularly, to a CMOS image element and its data for minimizing a data readout path to improve an offset generated when data is read. A control method for reading.

Referring to FIG. 1, the CMOS image element 10 according to an exemplary embodiment of the present disclosure may include pixel arrays 34 including a plurality of pixels 18 to 24, and rows for driving pixels in units of rows. Data read block 6, 38 or 36 for reading data of odd or even columns of pixel arrays on two sides (e.g. up, down or left and right) facing each other with driver 2 and pixel array 34 in the center 40).

Each data read block 6, 38, or 36, 40 may include an analog-to-digital converter (ADC) block 6, 36 and a latch block 38, 40 between each pixel array 34 and the data output terminal OUTx. Equipped. It also has a buffer 4 which receives a select signal COUNTER from an external (e.g., data selector: not shown) to activate the corresponding de-flip flop 16 or 32 of the latch block 38 or 40.

The analog-to-digital converter blocks 6 and 36 are correlated double sample blocks (CDSs) 26 corresponding to respective pixel columns, an amplifier 28 for amplifying the sampled signals, and the amplified signals for digital data. Analog-to-digital converter (ADC: 30) to convert to.

The CMOS image element 10 may be configured such that the respective electrical signals provided from the red pixels R: 18, the green pixels G _R , G _B : 22, and 20, and the blue pixels B: 24 are converted into ADC blocks 6. , 36). The signals provided by each of the pixels in the odd rows of pixels are processed in the lower ADC block 36 below the pixel array. The signals provided at each pixel in even rows of pixels are processed in the upper ADC block 6 located above the pixel array. After the digital signal provided from the ADC block 6 or 36 is stored in the latch block 38 or 40, it outputs a selection signal for causing the data selector (not shown) to output the latched data, and in response, the latch block ( 38 or 40 are output to an external image signal processor (not shown).

However, the CMOS image element 10 may include a path offset generated due to a spatial position difference between the upper and lower ADC blocks 6 and 36, for example, fixed pattern noise (FPN), and the like. Is generated.

Therefore, the CMOS image element 10 outputs the signals sensed by the plurality of pixels to the ADC blocks 6 and 36 through the data read line, which is the data corresponding to the time that is sampled by the CDS and converted by the ADC. The digital code values are stored in the de-flip flops 16 and 32 and processed. This approach results in path offsets due to different read paths between the respective data read lines for odd and even columns, which cause noise to degrade the performance of the CMOS imager. In addition, the chip area of the CMOS image element is increased by data read lines and peripheral circuits provided at both ends of the pixel array (up, down, left, and right), thereby increasing production costs.

As one of the prior arts for solving the above-described problems, a CMOS image device including a unidirectional data read line is disclosed in FIG. 2. Here, the detailed description of the components shown in FIG. 1 will be omitted.

Referring to FIG. 2, the CMOS image device 80 is provided on the semiconductor substrate in the same direction as the data read lines of the odd columns and the data read lines of the even columns shown in FIG. 1. This is to improve the path offset caused by bidirectional data read lines.

However, since the CMOS image device 80 having a unidirectional data read line occupies an area of the semiconductor substrate by the logic 48 and 76 shown in the drawing, the chip size of the CMOS image device may increase. .

In addition, since the CMOS image elements 80 have odd-numbered and even-numbered columns of ADC blocks 46 and 48 on the same side of the pixel array, the width of the CDS or ADC may be the interval of unit pixels, that is, the pitch ( pitch), it is very difficult to lay out a high performance CDS or ADC in one column pitch.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problem, and to provide a CMOS image device for preventing a path offset due to a data read path.

Another object of the present invention is to solve the above-mentioned problems, to provide a CMOS image element that can be reduced in size and production costs.

1 is a block diagram showing the configuration of a CMOS image element according to a first embodiment of the prior art;

2 is a block diagram showing the configuration of a CMOS image element according to a second embodiment of the prior art;

3 is a block diagram showing the configuration of a CMOS image element according to a first embodiment of the present invention; And

4 is a block diagram showing the configuration of a CMOS image element according to a second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100, 200: CMOS image element (CIS) 102, 202: row driver

104, 204, 106, 206: buffer 110, 210: pixel array

120, 220: ADC block 130, 230: Switching block

132, 134, 232, 234: switching circuit 140, 240: latch block

According to an aspect of the present invention for achieving the above object, the imaging device, a pixel array having a plurality of pixels, and a plurality of switching means connected to each of the odd and even columns of the pixel array connected to each other switching; And a plurality of analog-digital converter blocks connected to the pair of the switching means corresponding to the odd-numbered and even-numbered columns, and the video signals of the pixels from the analog-digital converter blocks of the odd-numbered or even-numbered columns. And a latch block for receiving and storing digital data.

In this aspect, the switching means is activated to select the odd-numbered or even-numbered columns in synchronization with a clock signal input from the outside, and the analog-to-digital converter block samples the image signal sensed from the pixels. It is preferable to include a correlated redundant sampling block, an amplifier for amplifying the sampled signal, and an analog-to-digital converter for converting the amplified signal into digital data.

According to another aspect of the present invention for achieving the above object, the image device comprises a pixel array having a plurality of pixels, a plurality of analog-to-digital converter blocks connected to the columns of the pixel array, and the analog-to-digital converter blocks Respectively connected to switching means for switching to output image signals of odd or even columns of the pixel array, and to the switching means for pairing odd and even columns of the pixel array, respectively. And a latch block receiving and storing digital data corresponding to an image signal of the pixels from the analog-digital converter blocks in the second or even-numbered columns and outputting the digital data to the outside.

Preferably, the switching means is activated to select the odd-numbered or even-numbered columns in synchronization with a clock signal input from the outside, and the analog-to-digital converter block is used to sample the image signal sensed from the pixels. And a sampling block, an amplifier for amplifying the sampled signal, and an analog-to-digital converter for converting the amplified signal into digital data.

Therefore, according to the present invention, by switching and outputting an image signal corresponding to an odd or even column of a pixel array, the number of analog-to-digital converter blocks or latch circuits corresponding to the switching circuits can be reduced, thereby simplifying the logic of the image elements. Can reduce the offset caused by the data read path.

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a configuration of a CMOS image sensor according to an embodiment of the present invention.

Referring to the drawings, the CMOS image device 100 includes a novel switching block 130.

In addition, the CMOS image device 100 includes a color pixel array 110, a row driver 102, two buffers 104 and 106, an analog-to-digital converter (ADC) block 120, and a latch block 140. ).

The color pixel array 110 includes three types of pixels, that is, a red pixel (R: 112), a blue pixel (B: 118), and a green pixel (G _R , G _B : 116, 114). It is provided. The green pixel G _R is located in the same row as the red pixel R, and the green pixel G _B is located in the same row as the blue pixel B.

The row driver 102 selects row lines in series, for example sequentially from top to bottom, in response to signals generated by a timing generator or address generator not shown. For example, the first line when the line is selected, the first red pixel in the row (R: 112), green _pixels: The (G _R 116) is activated. When the second row line is selected, the green pixels G _B 114 and blue pixels B 118 of the second row are activated.

The ADC block 120 may include a plurality of correlated double sampling (CDS) blocks 122 connected to odd or even columns of the pixel array 110, amplifiers 124, and ADCs 126. Include. The ADC block 120 receives the signals sensed by the plurality of pixels, is sampled by the CDS 122, amplified by the amplifier 124, and converted into digital data by the ADC 126.

The latch block 140 includes a plurality of de-flip flops 142, receives a selection signal COUNTER from the second buffer 106, and displays each digital data output from the ADCs 126. Output to a signal device (not shown). In this embodiment, the number of the flip-flops 142 is 1/2 times the number of columns of the pixel array 110.

The first buffer 104 selects the switching block 130 in synchronization with a clock signal CLK output from a timing generator (not shown), for example. The second buffer 106 receives a selection signal COUNTER from a data selector (not shown) and outputs it to the latch block 140.

In addition, the switching block 130 includes a plurality of switching circuits 132 and 134 corresponding to the columns of the pixel array 110. That is, the switching circuits 132 and 134 are respectively connected to the ADC block 120 corresponding to the odd-numbered and even-numbered pixel arrays, and the odd-numbered and even-numbered pairs of the switching circuits 132, 134 are each de-flipped. It is connected to the flop 142. The switching block 130 receives the clock signal CLK from the first buffer 104, and the odd-numbered switching circuits 132 are activated in the logic low level period of the clock signal CLK, and the switching signal 130 of the click signal CLK is activated. In the logic high level period, even-numbered switching circuits 134 are activated. Accordingly, the switching block 130 outputs the odd-numbered columns of data to the latch block 140 in the logic low level section of the click signal CLK, and latches the data of the even-numbered columns in the logic high level section of the click signal CLK. Output to block 140. In addition, the switching block 130 doubles the period of the clock signal CLK to output odd-numbered columns of data in the clock signal of the first period, and even-numbered columns of data in the clock signal of the second period. It may be output to 140.

Accordingly, one of the flip-flops 142 receives the odd or even columns of data in synchronization with the clock signal CLK, and outputs data to the outside in response to the selection signal COUNTER, thereby providing logic for the latch block 140. The number can be reduced.

4 is a block diagram showing the configuration of a CMOS image device according to another embodiment of the present invention. In this embodiment, detailed description of the same components shown in FIG. 3 will be omitted.

Referring to the drawings, the CMOS image device 200 includes a novel switching block 230. Here, as compared with the CMOS image device 100 shown in FIG. 3, the CMOS image device 200 of this embodiment shows that the switching block 230 is provided between the pixel array 210 and the ADC block 220. Can be.

The switching block 230 is provided with a plurality of switching circuits 232 and 234 corresponding to the columns of the pixel array 210. That is, the pair of switching circuits 232 and 234 are connected to one ADC block 222, 224 and 226 respectively corresponding to the odd and even pixel arrays, and one ADC block 222, 224 and 226. ) Is connected to one de flip flop 242, respectively. The switching block 230 receives the clock signal CLK from the third buffer 204 and activates the odd-numbered switching circuits 232 in the logic low level section of the clock signal CLK, and the logic of the click signal CLK. In the high level period, even-numbered switching circuits 234 are activated. Accordingly, the switching block 230 outputs odd-numbered columns of data to the ADC blocks 222, 224, and 226 in the logic low level section of the click signal CLK, and even-numbered data in the logic high level section of the click signal CLK. Output column data to ADC block. In addition, the switching block 230 doubles the period of the clock signal CLK so that the odd-numbered columns of data in the clock signal of the first period and the even-numbered columns of data in the clock signal of the second period are latch circuit 240. You can also output

The CMOS image element 200 may include a switching circuit corresponding to an odd-numbered or even-numbered column in response to a logic level of the clock signal CLK outputted from the third buffer 204 by the image signal output from the pixel array 210. Fields 230: 232 or 234, and output the signals of the activated switching circuits 232 or 234 to the corresponding ADC block 220.

Therefore, the CMOS image element 200 of this embodiment can reduce the number of CDS blocks 222 and ADCs 224 of the ADC block 220 by 1/2 times than the embodiment of FIG. 3.

As described above, the CMOS image elements 100 and 200 of the present invention include switching blocks 130 and 230 to select respective color image signals generated from respective pixels before or after the ADC block. As a result, the CMOS image device 100 or 200 may reduce the number of logics of the ADC block 220 or the latch blocks 140 and 240. In addition, unlike in the embodiment of the present invention, it is obvious that an image signal of a column is selected and output by using an encoder, a multiplexer, etc. without using a switching circuit.

As described above, by reducing the number of analog-to-digital converter blocks or latch circuits corresponding to the switching circuit, the logic of the image device can be simplified and the offset by the data read path can be reduced.

Claims (6)

In the imaging device: A pixel array having a plurality of pixels; A plurality of switching means connected to and connected to odd and even columns of the pixel array, respectively; A plurality of analog to digital converter blocks connected to a pair of said switching means corresponding to said odd-numbered and even-numbered columns; And a latch block receiving and storing digital data corresponding to the image signals of the pixels from the analog-digital converter blocks in the odd-numbered or even-numbered columns and outputting the digital data to the outside. The method of claim 1, And the switching means is activated to select the odd or even columns in synchronization with a clock signal input from the outside. The method of claim 1, The analog to digital converter block is; A correlated redundant sampling block for sampling the image signal detected from the pixels; An amplifier for amplifying the sampled signal; And an analog-to-digital converter for converting the amplified signal into digital data. In the imaging device: A pixel array having a plurality of pixels; A plurality of analog to digital converter blocks coupled to the columns of the pixel array; Switching means connected to the analog to digital converter blocks, respectively, and switching to output an image signal of odd or even columns of the pixel array; Connected to the switching means for pairing odd-numbered and even-numbered columns of the pixel array, respectively, and receiving digital data corresponding to an image signal of the pixels from the analog-digital converter blocks of the odd-numbered or even-numbered columns; And a latch block for storing and outputting the result to the outside. The method of claim 4, wherein And the switching means is activated to select the odd or even columns in synchronization with a clock signal input from the outside. The method of claim 4, wherein The analog to digital converter block is; A correlated redundant sampling block for sampling the image signal sensed from the pixels; An amplifier for amplifying the sampled signal; And an analog-to-digital converter for converting the amplified signal into digital data.