KR20080011853A - Display apparatus - Google Patents

Abstract

A display apparatus is provided to improve flicker caused by the swing of voltage in storage lines by executing a double driving. A display apparatus includes a display panel(100), gate and storage drivers(400,200), a gray scale divider(300), and a data driver(500). The display panel includes plural pixels, which are defined by gate, data, and storage lines, and displays images. The gate driver supplies sequentially gate signals to the gate lines. The storage driver applies a storage voltage, which is inverted for every half frame period, to the storage lines. The gray scale divider divides a gray scale signal, which is supplied from a gray scale source, into two signals. The data driver outputs data voltage corresponding to the divided signals to the data lines during first and second sub-frame periods.

Description

Display device {DISPLAY APPARATUS}

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a view illustrating the storage driver shown in FIG. 1.

3 is a driving waveform diagram of the storage driver illustrated in FIG. 2.

FIG. 4A is a block diagram illustrating a first embodiment of the gray division unit shown in FIG. 1.

FIG. 4B is a signal waveform diagram for describing an operation of the gray division unit according to the first embodiment shown in FIG. 4A.

FIG. 5A is a block diagram illustrating a second embodiment of the gray division unit shown in FIG. 1.

FIG. 5B is a signal waveform diagram for describing an operation of a gray scale division unit according to the second exemplary embodiment shown in FIG. 5A.

<Description of the symbols for the main parts of the drawings>

100: display panel 200: storage drive unit

300: gradation dispenser 400: gate driver

500: data driver 600: controller

GL: gate wiring DL: data wiring

SL: Storage wiring TFT: Thin film transistor

CLC: liquid crystal capacitor CST: storage capacitor

Vcom: Common Voltage DATA: Image Signal

CONT: sync signals

The present invention relates to a display device, and more particularly, to a display device for reducing power consumption and improving a response speed.

In general, a liquid crystal display device includes an array substrate on which pixel electrodes are formed, an opposing substrate on which a common electrode is formed, and a liquid crystal layer having an anisotropic dielectric constant interposed between two substrates. Such a liquid crystal display is a flat panel display that artificially forms an electric field between two substrates, and displays a desired image by adjusting the light transmittance of the liquid crystal, which varies according to the intensity of the electric field.

Such liquid crystal displays are widely used in various applications such as notebook computers, monitors, and the like based on the advantages of slim design, low power consumption, and high resolution. In recent years, mobile devices have been attracting attention, and liquid crystal display devices used in these portable devices are required not only to display information but also to be able to faithfully display photos, videos, broadcasts, and the like.

However, as the liquid crystal display device becomes higher resolution, an increase in power consumption becomes a problem, and a fast response speed required for displaying a moving image becomes a problem.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display device for reducing power consumption and improving a response speed.

A display device according to an exemplary embodiment for realizing the object of the present invention includes a display panel, a gate driver, a storage driver, a gray division unit, and a data driver. The display panel includes a plurality of pixel portions formed by gate lines and data lines crossing the gate lines, and storage lines are formed in parallel with the gate lines to display an image. The gate driver sequentially supplies a gate signal for activating the gate lines. The storage driver applies a storage voltage that is inverted every 1/2 frame period between adjacent storage lines. The gray division unit divides the gray level signal provided from the gray level source into two. The data driver converts the divided second gray level signal into a corresponding data voltage and outputs the data lines in the first sub frame period and the second sub frame period.

According to such a display device, power consumption can be reduced and response speed can be improved. In addition, the range of the gray scale voltage is extended to improve brightness, and the video visibility may be improved by driving the gray scale signal by dividing the gray signal.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel 100, a gate driver 400, a data driver 500, a storage driver 200, a gray division unit 300, and a controller 600. ).

Here, the gate driver 400, the data driver 500, the storage driver 200, the gray division unit 300, and the controller 600 convert the image signal provided from an external device to the display panel 100. Is defined as a driving device of a display device.

The display panel 100 crosses the data lines DL1 to DLm to which a divided data voltage (for example, a data signal) is supplied, and the gate lines GL1 that cross the data lines DL1 to DLm and are activated by a gate signal. A plurality of pixel portions defined by? GLn). The semiconductor device further includes storage lines SL1 to SLn formed to be parallel to the gate lines GL1 to GLn and intersect the data lines DL1 to DLm. Although not shown, the display panel 100 includes an array substrate on which gate lines GL1 to GLn, data lines DL1 to DLm, and storage lines SL1 to SLn are formed, and an opposing substrate facing the array substrate. (For example, a color filter substrate) and a liquid crystal layer interposed between the two substrates.

Each pixel portion includes a thin film transistor TFT in which a gate electrode and a source electrode are connected to the gate line GL and the data line DL, and a liquid crystal capacitor CLC and a storage capacitor CST electrically connected to the thin film transistor TFT. ) Is formed. The liquid crystal capacitor CLC functions as a dielectric using a pixel electrode connected to the drain electrode of the thin film transistor TFT and a common electrode provided with a common voltage as two electrodes, and a liquid crystal layer between the two electrodes. The common voltage Vcom provided to the common electrode is a direct current (DC) voltage maintaining a constant level of voltage. The pixel electrode and the common electrode may be formed on the same substrate or may be formed on different substrates. The storage capacitor CST functions as a dielectric, a first electrode connected to the drain electrode of the thin film transistor TFT, a second electrode connected to the storage line SL, and an insulator between the two electrodes. Here, the first storage voltage V1 or the second storage voltage V2 is applied to the storage line SL. For example, the storage capacitor CST may be formed by overlapping a portion of the pixel electrode and the storage line SL with an insulator interposed therebetween.

The controller 600 receives the synchronization signals CONT and the image signal DATA from the outside, and controls the signals for driving the gate driver 400 and the data driver 500 based on the synchronization signals CONT. Create The synchronization signals CONT input to the controller 600 include a main clock signal MCLK, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, and a data enable signal DE.

The gate control signals for controlling the gate driver 400 may include a vertical start signal STV indicating the start of output of the gate on signal Von and at least one gate clock signal controlling the period of the gate on signal Von. GATE CLK). The data control signals for controlling the data driver 500 include a horizontal start signal STH that indicates the start of the transmission of the data signal for one horizontal pixel column and a load that indicates the application of the data signal to the data lines DL1 to DLm. Signal TP and data clock signal DCLK. The data control signals may further include a polarity inversion signal RVS for inverting the voltage polarity (hereinafter, referred to as data polarity) of the data signal with respect to the common voltage Vcom. In addition, the controller 600 properly processes the image signal DATA received from the outside according to the operating conditions of the display panel 100, and then provides the image signal DATA to the data driver 500 through the gray division unit 300.

The gate driver 400 sequentially drives the gate lines GL1 to GLn formed on the display panel 100 based on the gate control signals provided from the controller 600. That is, by sequentially supplying a gate signal (eg, a gate on signal) for activating the gate line GL, the thin film transistors TFTs are turned on by being connected to the gate line GL to which the gate signal is applied. Drive. Here, the gate driver 400 divides one frame period into a first sub frame period and a second sub frame period, and sequentially supplies a gate signal twice. That is, the gate lines GL1 to GLn are sequentially activated once in the first sub frame period and sequentially activated once in the second sub frame period.

The data driver 500 supplies a data signal to the data lines DL1 to DLm based on the data control signals provided from the controller 600. That is, the time-divided gradation signal provided from the gradation divider 300 is converted into a corresponding data voltage (gradation voltage) and supplied to the data lines DL1 to DLm in the first and second sub frame periods. Here, the data voltages output to the data lines DL1 to DLm are driven in a line inversion scheme in which polarities are inverted in units of one horizontal pixel column and inverted for each subframe (for example, 1/2 frames). For example, a negative data voltage is applied to odd-numbered horizontal pixel columns with data lines, a positive data voltage is applied to even-numbered horizontal pixel columns, and a reverse polarity is applied to a next subframe. Apply the data voltage.

The storage driver 200 may invert the first and second storage voltages V1 and V2 between the storage lines SL1 to SLn adjacent to the storage lines SL1 to SLn of the display panel 100 at a half frame period. Is applied. That is, the first storage voltage and the second storage voltage of different levels are applied between the adjacent storage lines SL1 to SLn, and are inverted and applied to a section where the gate on signal Von is changed to the gate off signal Voff. do.

For example, when the first storage voltage V1 is higher than the second storage voltage V2 and the gate-on signal Von is provided, the odd-numbered storage wires SL1, SL3. The first storage voltage V1 is applied to 1) and the second storage voltage V2 is applied to even-numbered storage lines SL2 and SL4... Sn. When the gate-on signal Von is changed to the gate-off signal Voff, the gate-on signal Von is inverted to apply the second storage voltage V2 to the odd-numbered storage wires SL1, SL3... The first storage voltage V1 is applied to the wirings SL2 and SL4... Sn. As described above, the storage driver 200 inverts and applies the storage voltage after the charging period of the data voltage, which is the section in which the gate-on signal Von of the horizontal pixel column is applied, is completed.

The gray division unit 300 divides the gray level signal provided from the controller 600 in time and provides the data driver 500 to the data driver 500. That is, the gray scale signal having a driving frequency of 60 Hz (or 50 Hz) is received from the control unit 600, and divided into a gray scale signal having a driving frequency of 120 Hz (or 100 Hz) to provide to the data driver 500.

Meanwhile, although the gradation divider 300 is illustrated as being configured as an independent unit, the gradation divider 300 may be configured to be integrated into a graphic device, a liquid crystal display module, a controller 600, and a data driver 500. have.

FIG. 2 is an embodiment of the storage driver shown in FIG. 1, and FIG. 3 is a driving waveform diagram of the storage driver shown in FIG. 2.

Here, although the storage driver 200 illustrated in FIG. 2 is directly formed on the display panel 100, the storage driver 200 is not limited thereto and may be variously applied.

As described above, in the display device according to the present invention, the data voltage is inverted every horizontal pixel column with respect to the common voltage and inverted every subframe (1/2 frames). For example, the range of the data voltage applied to the data lines DL1 to DLm from the data driver 500 may be 0V to AVDD = 5V. Further, the common voltage (Vcom) is fixed to 1 / 2AVDD-V _kb (at this time, V is the kickback voltage _kb).

 Referring to FIG. 2, the storage driver 200 includes a plurality of stages SRV connected to the storage lines SL1 to SLn. Each stage includes a first switching element T1 and a second switching element T2, and further includes wiring for providing a storage driving voltage to the plurality of stages. Since the structures and operations of the first and second switching elements T1 and T2 included in each stage are the same, only the kth stage SRVk will be described.

The first switching element T1 of the k-th stage SRVk is connected to an input terminal VSL (hereinafter referred to as a storage driving wiring) to which a storage driving voltage is applied, and an output terminal is connected to the k-th storage wire SLk. The control terminal is connected to the k-th gate line GLk. The second switching element T2 has an input terminal connected to the storage drive wiring VSL, an output terminal connected to the k-th storage wiring SLk, and a control terminal connected to the k + 1 gate wiring GLk + 1. do. That is, the first and second switching elements T1 and T2 receive the storage driving voltage through one storage driving line VSL and output the same to the same storage line SL.

The operation of the storage driver 200 will be briefly described with reference to the driving waveform diagram of FIG. 3, and a positive data voltage is applied to the k-th horizontal pixel column provided with the k-th storage line SLk. Explain the case.

The first storage voltage V1 and the second storage voltage V2 are inverted and applied every 1 / 2H (H is a horizontal section) of the storage driving voltage applied to the storage driving wiring VSL. Here, the first storage voltage V1 is at a level higher than the second storage voltage V2.

The first switching element of the k-th stage SRVk in the section where the gate-on signal Von is applied to the k-th gate line GLk and the data voltage is charged in the pixel portion connected to the k-th gate line GLk. T1) is turned on. Accordingly, the second storage voltage V2 having the low level applied to the storage driving wiring VSL is applied to the kth storage wiring SLK through the first switching device in this section.

After 1 / 2H, the gate-off signal Voff is applied to the k-th gate line GLk, the gate-on signal Von is applied to the k + 1th gate line GLk + 1, and the storage driving wiring ( The high level first storage voltage V1 is applied to VSL. Accordingly, the first switching element T1 is turned off and the second switching element T2 is turned on so that the first storage voltage V1 of the storage driving wiring VSL is the second switching element T2. Through the k th storage line SLk.

That is, the second storage voltage V2 is applied to the k-th storage line SLk during the period in which the charging operation is performed on the pixel portion by the gate-on signal Von of the k-th gate line GLk, and the charging operation is performed. After completion, the first storage voltage V1 is applied to the kth storage line SLk.

After 1/2 frame, a negative data voltage is applied to the k-th horizontal pixel column provided with the k-th storage line SLk, and the voltage of the k-th storage line SLk is completed after the charging operation is completed. The first storage voltage V1 is changed from the second storage voltage V2. That is, the voltage of the k-th storage line SLk swings the first and second storage voltages V1 and V2 in a period of subframes (1/2 frames).

As such, when the positive data voltage is applied, the second storage voltage V2 is applied during the charging operation period, and the first storage voltage V1 is applied after the charging operation is completed. On the contrary, when a negative data voltage is applied, the first storage voltage V1 is applied during the charging operation period, and the second storage voltage V2 is applied after the charging operation is completed.

As described above, since the range of the pixel voltage (for example, the gray voltage) is increased by the amount of the voltage change of the pixel electrode increased due to the voltage change of the storage line SL, the voltage range for expressing the gray scale is increased, thereby improving luminance. In addition, because the common voltage is fixed, the power dissipated in the storage capacitors is reduced, reducing the total power consumption. When the data voltage changes due to the voltage change of the storage line SL, an overshooted data voltage is applied to the pixel electrode in the direction of accelerating the operation of the liquid crystal. Converge to data voltage values. This characteristic has the advantage of improving the response speed.

4A is a block diagram illustrating a gradation divider according to the first embodiment of FIG. 1, and FIG. 4B is a signal waveform diagram illustrating an operation of the gradation divider according to the first embodiment of FIG. 4A. .

4A and 4B, the gradation divider 300 according to the first embodiment of the present invention includes a frame memory 310.

The frame memory 310 receives and stores the gradation signal Gn + 1 of the n + 1 th frame from the gradation signal source, and stores the gradation signal Gn of the n th frame previously stored in the first sub gradation signal 1Gn and The second sub gray level signal 2Gn is divided and output. At this time, the first sub gray level signal 1Gn and the second sub gray level signal 2Gn output from the frame memory 310 are signals of the same gray level. In detail, the frame memory 310 outputs the gray level signal Gn of the nth frame, which is pre-stored in the first subframe period in which the nth frame is divided and the second subframe period, two times, respectively, to thereby provide the nth frame. The gray level signal Gn is divided by two. For example, if the driving frequency of the gray level signal provided to the frame memory 310 is 60 Hz (or 50 Hz), the driving frequency of the divided gray level signal may be defined as 120 Hz (or 100 Hz).

5A is a block diagram illustrating a configuration of the gray division unit shown in FIG. 1, and FIG. 5B is a signal waveform diagram illustrating an operation of the gray division unit according to the second embodiment illustrated in FIG. 5A. .

5A and 5B, the gray dividing unit 300 according to the second embodiment of the present invention includes a frame memory 310, a gray signal converting unit 320, and a separator 330. Since the frame memory 310 performs the same operation as the frame memory 310 according to the first embodiment described above, the frame memory 310 will be briefly described.

The frame memory 310 receives and stores the gray level signal Gn + 1 of the n + 1th frame from the gray level signal source, and stores the gray level signal Gn of the nth frame previously stored in the first sub gray level signal of the same gray level ( 1Gn) and the second sub gray level signal 2Gn are divided and output.

The gray level signal converter 320 converts each of the first sub gray level signal 1Gn and the second sub gray level signal 2Gn into a first corrected gray level signal HGn and a second corrected gray level signal LGn having different gray levels. Convert. Here, the first correction gray level signal HGn is a signal having a higher gray level than the input gray level signal (for example, the first sub gray level signal and the second sub gray level signal), and the second correction gray level signal LG n is smaller than the input gray level signal. It is a low gray level signal, and the sum of the two gray levels is the same gray level as the input gray level signal. For example, the gray level signal converter 320 may generate a first look-up table that generates the first corrected gray level signal HGn and a second corrected gray level signal LGn based on the input gray level signal Gn. It may be defined as a second lookup table.

The separator 330 receives the first corrected gray level signal HGn and the second corrected gray level signal LGn from the gray level signal changing unit 320, and responds to the output control signal FCS in response to the first corrected gray level signal HGn. ) And the output of the second correction gray level signal LGn. That is, in response to the output control signal FCS, the first correction gray level signal HGn generated based on the first sub gray level signal 1Gn is output in the first sub frame period, and the second sub frame period is output in the second sub frame period. The second correction gray level signal LGn generated based on the two sub gray level signals 2Gn is output.

In contrast to the above, the separator 330 outputs the second correction gray level signal LGn generated based on the first sub gray level signal 1Gn in the first sub frame section and the second in the second sub frame section. The first correction gray level signal HGn generated based on the sub gray level signal 2Gn may be output.

As described above, the gray level dividing unit 300 divides the input gray level signal into two different gray level signals, thereby improving video visibility. In addition, it is possible to improve flicker by driving two divisions of the gray level signal.

As described above, according to the present invention, the common voltage is maintained at a fixed voltage, and the voltage of the storage wiring is swing driven to widen the range of the gray scale voltage and improve the response speed. In addition, by dividing the gray level signal by two divisions, the response time is reduced by half, thereby improving video visibility and improving flicker due to the swing of the storage wiring voltage through double speed driving.

 Although described above with reference to the embodiments, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the invention described in the claims below. You will understand.

Claims (8)

A display panel in which a plurality of pixel portions are formed by gate lines and data lines crossing the gate lines, and storage lines are formed in parallel with the gate lines to display an image; A gate driver sequentially supplying a gate signal for activating the gate lines; A storage driver for applying a storage voltage inverted at a half frame period between the adjacent storage lines; A gradation divider dividing the gradation signal provided from the gradation source into two; And And a data driver converting the divided gray level signal into a corresponding data voltage and outputting the data voltages to the data lines in a first sub frame period and a second sub frame period. The method of claim 1, wherein the gradation dispenser and a frame memory which stores the gray level signal of the n + 1 th frame and divides the stored gray level signal of the nth frame into first and second sub gray level signals of the same gray level. The method of claim 2, wherein the gradation dispenser A gradation signal converter for converting each of the first and second sub gradation signals into a first correction gradation signal and a second correction gradation signal of different gradations; And And a separator configured to output a first correction gray level signal in the first sub frame period, and output a second correction gray level signal in the second sub frame period. The gray level signal converter of claim 3, wherein And first and second lookup tables for generating the first and second correction gray level signals, respectively. The method of claim 1, wherein each pixel unit A thin film transistor having a gate electrode and a source electrode connected to the gate line and the data line, respectively; A liquid crystal capacitor connected to the drain electrode of the thin film transistor; And And a storage capacitor connected to the drain electrode and the first electrode of the thin film transistor and to the storage wire and the second electrode. The display device of claim 1, wherein a driving frequency of the output gray level signal of the gray level divider is 120 Hz or 100 Hz. The voltage of the k-th storage line is a negative voltage when the k-th horizontal pixel column is charged, and when the k-th horizontal pixel column is charged with the negative data voltage. The voltage of the k-th storage wiring is a negative voltage, And the voltage of the k-th storage line is inverted after data charging is completed in the k-th horizontal pixel column. The display device of claim 7, wherein the polarity of the data voltage is inverted every horizontal pixel column and inverted every 1/2 frame.

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