KR20080010580A - Histogram based adc bist for hardware overhead optimization - Google Patents

Abstract

A histogram based ADC(Analog-Digital Converter) BIST(Built-In Self-Test) for hardware overhead optimization is provided to perform a test with an operation speed by applying the BIST to an ADC test. A histogram based ADC(Analog-Digital Converter) BIST(Built-In Self-Test) for hardware overhead optimization includes a signal generator(20), a comparator(40), and a result analyzer(30). The signal generator generates a test signal applied to the input of an ADC(10). The comparator outputs a test end signal when the signal generated from the signal generator reaches maximum voltage. The result analyzer outputs an offset, a gain, and an NL(Differential/Integral non-linearity) value by analyzing the output of the ADC. The result analyzer has a transition detector to detect the generation of transition through the LSB(Least Significant Bit) of the output of the ADC, and a counter device to count transition signals outputted from the transition detector.

Description

Built-in self test device and method of analog-to-digital converter to reduce hardware overhead {Histogram based ADC BIST for hardware overhead optimization}

1 is a conceptual diagram of a BIST technique using a histogram method.

2 is a block diagram of an ADC BIST device in accordance with the present invention.

3 is a diagram illustrating an internal configuration of the result analyzer of FIG. 2.

4 is a waveform diagram of a test signal used in the apparatus of the present invention.

5 is an output distribution diagram of a trouble-free ADC when the test signal of FIG. 4 is used.

8 is a graph showing an offset error.

9 is a graph showing gain error

FIG. 10 is a graph showing non-linearity errors. FIG.

The present invention relates to a built-in self-test (BIST) for testing faults on static parameters of analog-to-digital converters (ADCs). More specifically, the present invention relates to a BIST device and method of an ADC which shortens test time and reduces hardware overhead compared to the conventional method.

Hybrid signal circuits (ADCs), which are applied to most systems, include analog digital converters (ADCs), and a built-in self test method (BIST) has been actively studied. Built-in self-test methods for ADCs include static methods that determine the presence of failures by calculating parameters such as gain, offset, differential non-linearity (DNL), and integral non-linearity (INL), There is a dynamic method of calculating parameters such as Signal-to-Noise Ratio (SNR), Signal-to-Noise and Distortion (SINAD), and Effective Number of Bits (ENOB).

The most commonly used method is the histogram method. The configuration of the BIST using the histogram method is shown in FIG. 1. The BIST using the histogram method is a method of applying a predetermined test signal 12 generated by the signal generator to the input of the ADC 10 and storing the frequency for each code coming from the output in the memory 14. With the frequency of each code stored, DSP 16 calculates the characteristics of the ADC and outputs the offset, gain, and NL signals.

This histogram method requires many samples to obtain statistically satisfactory results. This results in a long test time and a large storage space. Several methods have been published to address these shortcomings, but there is a need for a way to reduce hardware overhead and test time simultaneously. In the conventional method, hardware overhead is reduced compared to the conventional method by sharing the hardware for calculating the offset, gain, INL, and DNL of the ADC. However, because the parameters are calculated sequentially rather than at one time, the test time is increased by four times compared to the conventional method.

In addition, other conventional methods have separate modules for calculating each parameter, which greatly reduces test time, but in this case, hardware overhead is increased.

In summary, the histogram method for testing the ADC is widely used to calculate static parameters such as offset, gain, differential non-linearity (DNL), and integral non-linearity (INL) of the ADC. The histogram method calculates a static parameter with the frequency of occurrence of the ADC's output, so the more samples the output has, the more accurate the result. However, a high capacity register is needed to store the frequency of occurrence of the ADC output value, and four high capacity registers are needed to calculate the four static parameters. This hardware overhead problem is difficult to apply to the BIST. In order to solve this problem, a method of reducing hardware overhead is to reuse BIST resources and calculate each parameter in turn. However, this method has the disadvantage that the test time is increased by four times.

The present inventors propose a BIST structure that reduces hardware overhead without reducing test time. By calculating the correlation of static parameters, we propose a structure that calculates offset, gain, DNL, and INL using one down counter and one up down counter. By calculating each parameter in parallel, the test time is reduced, and the hardware overhead can be reduced compared to conventional methods by simply calculating static parameters through two counters.

It is an object of the present invention to provide a BIST method and apparatus that can reduce hardware overhead and reduce test time compared to existing BIST methods that can calculate static parameters of an ADC.

In order to achieve the above object, two counters were used to analyze the static parameters of the ADC and to detect the static parameters for the development of the BIST apparatus and method of the present invention. Specifically, we analyzed the static parameters of the ADC and proposed hardware to detect errors for each parameter without setting a detector for each parameter, thereby reducing hardware overhead while reducing test time. To reduce. First, the concept of the BIST apparatus and method according to the present invention will be described.

According to the invention, a BIST device for testing an analog-to-digital converter (ADC)

A signal generator for generating a test signal to be applied to the input of the ADC

A comparator for outputting a test end signal when the signal generated by the signal generator reaches a maximum voltage;

It consists of a result analyzer that analyzes the output of the ADC and outputs the offset, gain, and NL values.

The result analyzer includes a transition detector for detecting the occurrence of a transition (transition) through the LSB of the ADC 10 output, and a counter means for counting the transition signal output from the transition detector.

The transition detector may include a first flip-flop to which an LSB signal of an ADC output is input, an XOR gate to which a signal diverged from an output signal of the first flip-flop and an input signal of the first flip-flop is input, and the XOR And a second flip flop to which an output signal of the gate is input. The transition detector compares the LSB of the ADC one clock with the current LSB and outputs a signal of '1' if the value is different.

In addition, the counter means counts up to the output value of the ADC until a transition (transition) occurs, the counter for storing the frequency H (i) of the i-th code, and H stored in the counter every time a transition occurs Comparing (i) with reference value H _ideal , the first comparator for detecting offset and DNL errors, and down counting by setting only the most significant bit each time the output code of the ADC 10 changes, The down counter which subtracts H (i) from the value stored in the counter and the second comparator which detects gain and INL error by comparing the value stored in the counter with the reference value whenever the LSB transition of the ADC occurs. It may include.

Meanwhile, according to another aspect of the present invention, a BIST method for testing an analog-to-digital converter (ADC)

Generating a test signal,

Checking whether the test signal reaches the maximum voltage and applying the test signal to the input of the ADC if the maximum voltage has not been reached yet;

Analyzing the signal output from the ADC, and outputting the offset, gain, and NL (DNL and INL) values.

Here, the step of analyzing the ADC output signal

1) a transition detection step of detecting the occurrence of a transition (transition) through the LSB of the ADC output,

2) storing the frequency H (i) of the i-th code by performing up counting until a transition (transition) occurs in the output value of the ADC 10;

3) detecting an offset and a DNL error by comparing the stored H (i) with a reference value H _ideal whenever a transition occurs;

4) In parallel with the steps 2) and 3), whenever the output code of the ADC 10 changes, only the most significant bit is set and down counted, and H (i) is subtracted from the currently stored value. Steps,

5) The stored value (H _ideal + α) -H (i) may include detecting a gain and an INL error in comparison with a reference value whenever the LSB transition of the ADC 10 occurs.

Here, step 2) includes comparing the LSB of the ADC one clock ago with the current LSB and outputting a signal of '1' if the value is different.

The above method of the present invention can be embodied as a computer program in practice, in which case the computer recording medium on which the program is recorded is also included in the technical scope of the present invention.

In the present invention, the signal generated as the test signal is preferably a ramp signal, but is not necessarily limited thereto.

Hereinafter, a specific embodiment of an ADC BIST apparatus and method according to the present invention will be described with reference to the drawings.

2 is a block diagram of an ADC BIST device according to the present invention. One embodiment of the BIST device according to the present invention is a result signal analyzer 30 for analyzing the output of the ramp signal generator 20 and analog-to-digital converter (ADC) 10 for generating a test signal, and the ramp signal Comparator 40 is configured to send a test end signal (Test end) when the generator 20 reaches a maximum voltage of A.

와

을 계산하여 저장하도록 두 개의 카운터를 사용하였다. 결과분석기의 구조(30)는 도 3에 나타내었다. 결과분석기(30)는 ADC(10) 출력의 LSB를 통해 트랜지션(천이) 발생을 검출하는 트랜지션 검출기(310)와 카운터(320) 그리고 다운카운터(330)로 구성된다. 트랜지션 검출기(310)는 두 개의 플립플롭(F/F)과 하나의 XOR 게이트로 구성되며, 한 클록 이전의 ADC의 LSB와 현재의 LSB를 비교하여 그 값이 다르면 '1'의 신호를 카운터(320)와 비교기(325)에 보낸다. 카운터(320)는 ADC(10)의 출력값에 트랜지션(천 이)이 발생할 때까지 업카운팅을 하여, i번째 코드의 빈도수 H(i)를 저장한다. 트랜지션이 발생할 때마다 카운터(320)에 저장되어 있는 H(i)와 레프런스값 H_ideal를 비교하여 옵셋 및 DNL 에러를 검출한다. 다운카운터(330)는 ADC(10)의 출력 코드가 바뀔 때마다 최상위 비트만을 셋(set)시키며, 다운카운팅을 통해 카운터(320)에 저장되어 있는 값에서 H(i)를 뺀다. 최상위 비트만을 set할 때 카운터에 H_ideal+α만큼의 값이 증가한다고 하면, 다운카운터(330)는 (H_ideal+α)-H(i)를 누적하여 저장할 수 있다. 다운카운터(330)에 저장된 값은 ADC(10)의 LSB의 트랜지션이 발생할 때마다 비교기(335)에서 레프런스값과 비교되어 이득 및 INL 에러를 검출할 수 있다. 이렇게 함으로써 옵셋, 이득, DNL 및 INL 에러 검출부를 뺄셈기 없이 구현함으로써 하드웨어 오버헤드를 줄일 수 있다.Result analyzer 30

Wow

We used two counters to calculate and store. The structure of the result analyzer 30 is shown in FIG. 3. The result analyzer 30 includes a transition detector 310, a counter 320, and a down counter 330 that detect a transition (transition) generation through the LSB of the ADC 10 output. The transition detector 310 is composed of two flip-flops (F / F) and one XOR gate, and compares the LSB of the ADC one clock before the current LSB. 320 and the comparator 325. The counter 320 counts up to the output value of the ADC 10 until a transition (transition) occurs, and stores the frequency H (i) of the i-th code. Whenever a transition occurs, the offset and DNL error are detected by comparing the reference value H (i) stored in the counter 320 with the reference value H _ideal . The down counter 330 only sets the most significant bit each time the output code of the ADC 10 changes, and subtracts H (i) from the value stored in the counter 320 through down counting. If the value of H _ideal + α is increased in the counter when only the most significant bit is set, the down counter 330 may accumulate and store (H _ideal + α) -H (i). The value stored in the down counter 330 may be compared with the reference value in the comparator 335 whenever the LSB transition of the ADC 10 occurs to detect a gain and an INL error. This reduces hardware overhead by implementing offset, gain, DNL, and INL error detectors without subtractors.

The test signal applied to the ADC may be any signal such as a ramp signal, a triangular wave signal, a sine / cosine signal, etc., if the distribution of the magnitude is known. In one embodiment of the present invention, the ramp signal shown in FIG. In FIG. 4, A denotes a magnitude (voltage) of a ramp signal, and FS denotes a range of input signals that the ADC can convert. According to the BIST of the present invention, since the test is performed for one test signal period, the test time is short. By equalizing A and FS, a uniform output distribution of the ADC as shown in FIG. 5 can be obtained. In FIG. 5, the horizontal axis represents the output code of the ADC, and the vertical axis represents the code count of the code.

The advantage of using a ramp signal is that it can reduce the hardware overhead of the reference value by making one reference value to determine whether it is faulty or faultless. The conventional methods using the histogram have a disadvantage in that hardware overhead occurs because parameters such as offset, gain, INL, and DNL are calculated separately. However, according to the present invention, since the offset and the DNL, the gain and the INL are related, the hardware of the built-in self test method can be reduced through the association.

6 is a flow chart showing the schematic configuration of the method according to the invention. The process will be described with reference to the hardware configuration of FIG.

First, a ramp signal for generating a test signal is generated 102. Check if the ramp signal reaches the maximum voltage (104), and if so, terminate the process, and if it has not reached the maximum voltage, apply the ramp signal to the input of the ADC under test (106) (see Figure 2). ). The digital signal output from the ADC is analyzed (108), and the offset, gain, and NL (DNL and INL) values are output (110).

7 shows a detailed process of the ADC output analysis step 108 of FIG. Referring to the process flow with reference to the hardware configuration of Figure 3, first, the occurrence of the transition (transition) is detected through the LSB of the ADC output (202). This step is performed by the transition detector 310, as shown in FIG. 3, and compares the LSB of the ADC one clock ago with the current LSB. To the comparator 325. Next, up counting is performed until a transition (transition) occurs in the output value of the ADC 10, and the frequency H (i) of the i-th code is stored (204). Whenever a transition occurs, the stored H (i) is compared with the reference value H _ideal (206) to detect an offset and a DNL error (208).

On the other hand, as a separate route from step 204, after detecting a transition (transition) occurrence through the LSB of the ADC output (202), only the most significant bit is set every time the output code of the ADC 10 is changed. Down counting is performed to subtract and store H (i) from the value stored in the counter 320 (210). That is, if the value of H _ideal + α increases in the down counter when only the most significant bit is set, the down counter 330 may accumulate and store (H _ideal + α) -H (i). The stored value (H _ideal + α) -H (i) is compared with the reference value in the comparator 335 whenever the LSB transition of the ADC 10 occurs (212) to detect a gain and an INL error. (214).

The above method can be actually performed by a computer program, and the computer recording medium which records the program is also included in the protection scope of the present invention. Computer record carriers include any type of recording device that stores data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet). Include.

Offset error is defined as the difference between the actual ADC transfer curve and the ideal case transfer curve. 8 shows the offset error. 8 shows the transfer curve of the ADC. The horizontal axis represents the analog input and the vertical axis represents the digital output. The lower figure of FIG. 8 shows a histogram for the digital output in real and ideal cases where there is an offset error. If there is an offset error, you can see that more frequency comes out from the first code.

The offset error can be calculated by the definition of the offset with the frequency of the output code for the input. The calculation of the offset can be done as follows.

N _T is the total number of samples, and H (i) means the number of samples of the i-th code. H _ideal is the number of samples per code in the ideal case. It can be seen from the above equation that the offset error can be obtained by calculating (H (0) -H _ideal ).

On the other hand, gain error means that the gain, that is, the slope appears differently from the ideal case in the transfer curve. 9 shows the frequency of the transfer curve and the output when the ADC has a gain error.

The gain error can be calculated using the equation below.

In the case of a faultless ADC, the gain is 1, so the cumulative value of (H (i)-H _ideal ) is 0. If the cumulative value is not zero, you know that there is a gain error in the circuit under test.

Non-linearity errors are based on the fact that, for an ideal ADC, the interval over which code changes occur is constant at 1 Least Significant Bit (LSB). DNL is defined as the difference between the length of the ideal section where the i-th code occurs and the length of the actual section. INL is defined as the sum of DNL because all DNL errors before the i th affect the change of the i th code. The frequency of the transfer curve and output for nonlinearity errors is shown in FIG. 10. The formula according to the definition of nonlinearity error is

Looking at the formulas of offset, gain, INL, and DNL so far, we can see that each equation is proportional to H (i) -H _ideal .

와

을 계산하여 저장하는 구조를 제안하였다. 따라서 본 발명에 따른 내장된 자체 테스트 장치는 도 2에 나타낸 것과 같이 구성하였다.Therefore, the offset, gain, INL, and DNL can be calculated by using a module that calculates H (i) -H _ideal without having a unit to calculate each parameter according to the conventional method. In this application, for a more accurate calculation

Wow

We proposed a structure to calculate and store. Therefore, the built-in self test apparatus according to the present invention is configured as shown in FIG.

First, according to the present invention, since the BIST is applied to the ADC test, it can be tested at the operation speed. In this case, the ADC BIST based on the histogram was difficult to apply due to its hardware overhead. However, the ADC BIST can be applied by reducing the hardware overhead of the ADC BIST. In addition, the total cost of the circuit can be reduced with a reduction in test cost.

The built-in self test method of the present invention was applied to an 8-bit flash ADC. Six circuits with arbitrary short and open faults inserted into the transistor inside the ADC and eight circuits with offset error, gain error, INL and DNL error by changing the resistance value of the flash ADC by 10%. The experiment was conducted for. In the case of a fault-free circuit, a ramp signal was applied so that the frequency of each code was 255. As a result, it was confirmed that the failure of all the circuits was efficiently detected.

Since the method of the present invention improves the hardware overhead of existing methods for calculating static parameters, the comparison of hardware overhead and test time is more important than the performance evaluation. A comparison of the existing method and the proposed method is shown in Table 1 below.

In the paper entitled "Hardware Resource Minimization for Histogram-Based ADC BIST," there are four phases that sequentially compute four static parameters. Because of this, there is a control block that controls each phase, and the test time is long. The method presented in the paper "Optimal Schemes for ADC BIST based on Histogram" has a large hardware overhead since it requires four registers to calculate each parameter.

Since the method of the present invention calculates each parameter at once, the test time is short, and unlike the conventional methods, it is possible to simply calculate the static parameters with two counters without requiring an operator. Profit can be made by transferring the algorithm to the existing tool, and profit can be generated by transferring the BIST technology to the company that produces the ADC module.

Claims (10)

A BIST device for testing analog-to-digital converters (ADCs), A signal generator for generating a test signal to be applied to the input of the ADC A comparator for outputting a test end signal when the signal generated by the signal generator reaches a maximum voltage; A BIST device for an ADC comprising a result analyzer for analyzing the output of the ADC and outputting offset, gain, and NL values. The method of claim 1, wherein the result analyzer A transition detector for detecting a transition (transition) occurrence through the LSB of the ADC 10 output, A counter means for counting a transition signal output from said transition detector. The method of claim 2, wherein the transition detector A first flip-flop to which the LSB signal of the ADC output is input, an XOR gate to which an output signal of the first flip-flop and a signal branched from the input signal of the first flip-flop are input, and an output signal of the XOR gate is inputted Consisting of a second flip-flop A BIST device in an ADC that compares the LSB of the ADC one clock ago with the current LSB and outputs a signal of '1' if the value is different. The method of claim 2, wherein the counter means A counter that counts up to the output value of the ADC 10 until a transition (transition) occurs and stores the frequency H (i) of the i-th code, A first comparator for detecting offset and DNL errors by comparing H (i) stored in the counter with reference value H _ideal whenever a transition occurs; Whenever the output code of the ADC 10 is changed, the down counting by setting only the most significant bit down, and subtracting H (i) from the value stored in the down counter, And a second comparator for comparing a value stored in the down counter with a reference value every time a transition of the LSB of the ADC occurs to detect a gain and an INL error. 2. The BIST device of claim 1, wherein the signal generator generates a ramp signal. BIST method for testing analog-to-digital converters (ADCs), Generating a test signal, Checking whether the test signal reaches the maximum voltage and applying the test signal to the input of the ADC if it has not reached the maximum voltage, Analyzing the signals output from the ADC, and outputting offset, gain, and NL (DNL and INL) values. The method of claim 6, wherein analyzing the ADC output signal comprises: 1) a transition detection step of detecting the occurrence of a transition (transition) through the LSB of the ADC output, 2) storing the frequency H (i) of the i-th code by performing up counting until a transition (transition) occurs in the output value of the ADC 10; 3) detecting an offset and a DNL error by comparing the stored H (i) with a reference value H _ideal whenever a transition occurs; 4) In parallel with the steps 2) and 3), whenever the output code of the ADC 10 changes, only the most significant bit is set and down counted, and H (i) is subtracted from the currently stored value. Steps, 5) The stored value (H _ideal + α) -H (i) includes detecting the gain and INL error compared to the reference value whenever a LSB transition of the ADC 10 occurs. Way. The method of claim 7, wherein step 2) Comparing the LSB of the ADC one clock ago with the current LSB and outputting a signal of '1' if the value is different. The method according to claim 7, wherein the signal generated in the test signal generating step is a ramp signal. A computer recording medium containing a computer program for implementing any one of claims 6 to 9.

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