KR101542190B1 - Apparatus and method for testing analog-to-digital converter - Google Patents

Abstract

The present invention relates to a test device and a test method for an analog-to-digital converter. The test device for an analog-to-digital converter, being series-connected and including a plurality of stages sequentially outputting digital signals corresponding to an input signal, comprises: a histogram data generating unit generating sub-histogram data about each of the stages by accumulating frequencies of the digital signals outputted from each of the stages for each bit value; and a histogram data analyzing unit determining the abnormality of each of the stages based on the sub-histogram data generated about each of the stages.

Description

[0001] APPARATUS AND METHOD FOR TESTING ANALOG-TO-DIGITAL CONVERTER [0002]

The present invention relates to an apparatus and method for testing an analog-to-digital converter.

The present invention is derived from a research carried out by the Ministry of Education, Science and Technology of the Korea Science and Engineering Foundation (KOSEF) as part of a project to support researchers in the field of science and technology (Design No. 2013-8-0719, .

In recent years, as the SOC process becomes finer and more circuits are integrated on a smaller area, the importance of test reliability of electronic circuits is increasing. In the case of many hybrid signal circuits, it is impossible to apply the test method of the existing digital circuit, so more effort and cost are required. Analog-to-digital converters in these hybrid circuits have a direct impact on overall performance, so they need to be tested more precisely, but with increasing operating speed and resolution of the converter, it is becoming increasingly difficult to obtain accurate test results. In this regard, techniques for self-testing an analog-to-digital converter have been studied, but it is difficult to precisely generate and apply an analog test signal, and noise generated in the process of generating an analog test signal must be solved It remains a problem.

On the other hand, in the case of a technique of testing a pipeline analog-to-digital converter by a histogram method, a 1.5-bit output value ('00 ',' 01 ',' 10 ') are sequentially stored in a 2-bit latch of the pipeline latch, and the output value stored in the pipeline latch is output through a digital error correction circuit . In the event of a failure in the sub-digital-to-analog converter or sub-amplification module included in the stage, it is a big problem because it continuously affects the next stage. Conventionally, the data amount of the histogram required for testing the analog-to-digital converter by the histogram method is too large, which leads to a long test time.

An object of the present invention is to provide an apparatus and method for testing an analog-to-digital converter capable of testing an analog-to-digital converter with a small data throughput and shortening a test time.

Another object of the present invention is to provide a test apparatus and method of an analog-to-digital converter capable of judging a failure of a submodule (for example, a sub-digital-analog converter, a sub-amplification module) of each stage of an analog- And the like.

The problems to be solved by the present invention are not limited to the above-mentioned problems. Other technical subjects not mentioned will be apparent to those skilled in the art from the description below.

According to an aspect of the present invention, there is provided an apparatus for testing an analog-to-digital converter, comprising: a plurality of stages connected in series and sequentially outputting digital signals corresponding to input signals, A histogram data generation unit for accumulating the frequency numbers of digital signals output from each of the plurality of stages for each bit value to generate sub-histogram data for each of the plurality of stages; And a histogram data analysis unit for determining whether each of the plurality of stages is abnormal based on the sub-histogram data generated for each of the plurality of stages.

In one embodiment of the present invention, the histogram data analyzing unit determines whether there is an abnormality in the sub-module constituting the high-level stage, based on the sub-histogram data of the low-level stage among the plurality of stages.

In one embodiment of the present invention, each of the plurality of stages includes a sub analog-to-digital converter for converting the input signal or an output signal output from a higher level stage and outputting the digital signal; A sub-digital-analog converter for converting the digital signal into an analog signal; A subtractor for calculating a difference value between the input signal or the output signal and the analog signal; And a sub amplification module for amplifying the difference value by a factor of two.

In one embodiment of the present invention, the submodule includes at least one of the sub-digital-analog converter and the sub-amplification module.

In one embodiment of the present invention, the sub-digital-analog converter outputs the digital signal corresponding to one of '00', '01' and '10'.

In an embodiment of the present invention, the histogram data analyzing unit may include an adder for adding the cumulative frequency of the upper bit value of the sub-histogram data to the cumulative frequency of the lower bit value for the lower level stage; A subtractor for subtracting the cumulative frequency of the lower-bit value from the cumulative frequency of the lower-bit value of the sub-histogram data for the lower-level stage; And a divider that divides the cumulative frequency of the intermediate bit values of the sub histogram data for the lower level stage from the output value of the adder.

In one embodiment of the present invention, the histogram data analyzing unit calculates the differential nonlinear error value of the sub-digital-analog converter based on the output value of the subtracter.

In one embodiment of the present invention, the histogram data analyzing unit calculates the gain of the sub amplification module from the output value of the divider.

In one embodiment of the present invention, the test apparatus of the analog-to-digital converter includes 2-bit latches for transmitting, in every clock cycle, the digital signal output from each of the plurality of stages to the histogram data generation unit in parallel And further includes a pipeline latch.

In an embodiment of the present invention, the histogram data generation unit may include: a pipeline latch analyzer for accumulating the frequency count of the digital signal transmitted from the pipeline latch for each bit value; A sub-stage histogram generator for generating sub-histogram data for each stage according to the accumulated frequency of the digital signal; And a histogram updater that reflects the sub-histogram data updated for each clock in the histogram.

In one embodiment of the present invention, the pipeline latch analyzer comprises: a plurality of first AND gates for determining a bit value of a first digital signal output from the higher level stage; A plurality of second AND gates receiving the outputs of the plurality of first AND gates and determining a bit value of a second digital signal output from the lower level stage for each bit value of the first digital signal; And a plurality of counters receiving the outputs of the plurality of second AND gates and accumulating and counting the bit values of the second digital signals according to the bit values of the first digital signals.

According to another aspect of the present invention, there is provided a digital-to-analog converter comprising: a plurality of stages connected in series and sequentially outputting digital signals corresponding to input signals; A histogram data generation unit for accumulating the frequency numbers of digital signals output from each of the plurality of stages for each bit value to generate sub-histogram data for each of the plurality of stages; And a histogram data analyzing unit for determining whether each of the plurality of stages is abnormal based on the sub-histogram data generated for each of the plurality of stages.

In one embodiment of the present invention, the histogram data analyzing unit determines whether there is an abnormality in the sub-module constituting the high-level stage, based on the sub-histogram data of the low-level stage among the plurality of stages.

In one embodiment of the present invention, each of the plurality of stages includes a sub analog-to-digital converter for converting the input signal or an output signal output from a higher level stage and outputting the digital signal; A sub-digital-analog converter for converting the digital signal into an analog signal; A subtractor for calculating a difference value between the input signal or the output signal and the analog signal; And a sub amplification module for amplifying the difference value by a factor of two.

In one embodiment of the present invention, the analog-to-digital converter comprises a pipeline latch including two-bit latches for transmitting, in every clock cycle, the digital signal output from each of the plurality of stages in parallel to the histogram data generator, (pipeline latch).

According to another aspect of the present invention, there is provided a method of testing an analog-to-digital converter including a plurality of stages connected in series and sequentially outputting digital signals corresponding to input signals, Accumulating the frequency counts of the digital signals output from the stages of each of the plurality of stages by bit values to generate sub-histogram data for each of the plurality of stages; And determining whether each of the plurality of stages is abnormal based on the sub-histogram data generated for each of the plurality of stages.

In one embodiment of the present invention, the step of determining the abnormality determines whether or not an abnormality has occurred in the sub-module constituting the high-level stage, based on the sub-histogram data of the low-level stage of the plurality of stages .

In one embodiment of the present invention, the step of determining the abnormality includes: adding the cumulative frequency of the upper bit value of the sub-histogram data to the cumulative frequency of the lower bit value for the lower level stage; Subtracting the cumulative frequency number of the lower-bit value from the cumulative frequency number of the lower-bit value of the sub-histogram data for the lower-level stage; And dividing the cumulative frequency of the intermediate bit values of the sub histogram data for the lower level stage from the output value of the adder.

In one embodiment of the present invention, the step of determining the abnormality calculates a differential nonlinear error value of the sub-digital-analog converter based on the output value of the subtracter.

In one embodiment of the present invention, the step of determining the abnormality includes calculating a gain of the sub amplification module from an output value of the divider.

According to the embodiments of the present invention, it is an object of the present invention to provide an apparatus and method for testing an analog-to-digital converter capable of testing an analog-to-digital converter with a small data throughput and shortening a test time.

Further, according to the embodiment of the present invention, it is possible to determine a failure of a submodule (for example, a sub-digital-analog converter, a sub-amplification module) of each stage of the analog-digital converter.

The effects of the present invention are not limited to the effects described above. Unless stated, the effects will be apparent to those skilled in the art from the description and the accompanying drawings.

FIG. 1 is a schematic diagram showing a test apparatus of an analog-to-digital converter according to an embodiment of the present invention. Referring to FIG.
2 is a configuration diagram of a stage constituting an analog-to-digital converter according to an embodiment of the present invention.
3 is a more detailed view of a test apparatus of an analog-to-digital converter according to an exemplary embodiment of the present invention.
FIG. 4 is a block diagram illustrating a histogram data generating unit of the test apparatus of the analog-to-digital converter according to an embodiment of the present invention in more detail.
5 is a block diagram illustrating a pipeline latch analyzer constituting a test apparatus of an analog-to-digital converter according to an embodiment of the present invention in more detail.
FIG. 6 is an exemplary diagram illustrating digital signals generated by a test apparatus of an analog-to-digital converter according to an exemplary embodiment of the present invention.
FIG. 7 is a diagram illustrating sub-histogram data generated by a test apparatus of an analog-to-digital converter according to an exemplary embodiment of the present invention.
FIG. 8 is a configuration diagram of a histogram data analysis unit constituting a test apparatus of an analog-to-digital converter according to an embodiment of the present invention.

Other advantages and features of the present invention and methods of achieving them will be apparent by referring to the embodiments described hereinafter in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and the present invention is only defined by the scope of the claims. Although not defined, all terms (including technical or scientific terms) used herein have the same meaning as commonly accepted by the generic art in the prior art to which this invention belongs. A general description of known configurations may be omitted so as not to obscure the gist of the present invention. In the drawings of the present invention, the same reference numerals are used as many as possible for the same or corresponding configurations.

It should be noted that the terms such as '~', '~ period', '~ block', 'module', etc. used in the entire specification may mean a unit for processing at least one function or operation. For example, a hardware component, such as a software, FPGA, or ASIC. However, '~ part', '~ period', '~ block', '~ module' are not meant to be limited to software or hardware. Modules may be configured to be addressable storage media and may be configured to play one or more processors. ≪ RTI ID = 0.0 > Thus, by way of example, the terms 'to', 'to', 'to block', 'to module' refer to components such as software components, object oriented software components, class components and task components Microcode, circuitry, data, databases, data structures, tables, arrays, and the like, as well as components, Variables. The functions provided in the components and in the sections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ' , '~', '~', '~', '~', And '~' modules with additional components.

The test apparatus of the analog-to-digital converter according to the embodiment of the present invention performs histogram analysis on the cumulative frequency counts of the digital signals outputted at every clock generation in the stages of the analog-to-digital converter, For example, a sub-digital-analog converter, or a sub-amplification module). According to the embodiment of the present invention, it is possible to test the analog-to-digital converter with a small data throughput and to shorten the test time of the analog-to-digital converter. In addition, according to the embodiment of the present invention, it is possible to determine the failure of the sub-module of each stage of the analog-to-digital converter and improve the test accuracy.

FIG. 1 is a schematic diagram showing a test apparatus of an analog-to-digital converter according to an embodiment of the present invention. Referring to FIG. Referring to FIG. 1, a test apparatus 100 of an analog-to-digital converter according to an exemplary embodiment of the present invention may test an analog-to-digital converter 110 including a plurality of stages 111, 112, and 113. In the embodiment of FIG. 1, the analog-to-digital converter 110 is provided as a pipelined analog-to-digital converter. In this pipeline analog-to-digital converter, the digital signals output from the stages 111, 112, and 113 are processed in parallel, and the stages 111, 112, and 113 are simultaneously operated in a pipelined manner. The analog-to-digital converter 110 includes a plurality of stages 111, 112 and 113 connected in series, and a 2-bit analog-to-digital converter 114.

The plurality of stages 111, 112, and 113 sequentially output the digital signals DS1, DS2, and DSn corresponding to the input signal IS. Each of the stages 111, 112 and 113 receives the input signal IS or the output signals OS1, OS2 and OSn output from the upper level stage and outputs the output signals OS1, OS2 and OSn corresponding to the input signal IS or the output signals OS1, And outputs digital signals DS1, DS2, DSn. The output signals OS1, OS2, OSn output from the upper level stage are input to the lower level stage. The 2-bit analog-to-digital converter 114 converts the output signal of the n-th stage 113 into a 2-bit digital value.

The test apparatus 100 of the analog-to-digital converter according to the embodiment of the present invention includes a pipeline latch 120, a histogram data generating unit 130, and a histogram data analyzing unit 140. The pipeline latch 120 latches a plurality of 2-bit latches for transmitting the digital signals DS1, DS2, DSn output from each of the stages 111, 112, 113 to the histogram data generator 130 in parallel, (2-bit latch).

The histogram data generating unit 130 generates sub histogram data for each of the plurality of stages 111, 112, and 113 by accumulating the frequency numbers of the digital signals DS1, DS2, and DSn output from each of the plurality of stages 111, 112, do. The histogram data analysis unit 140 determines whether or not each of the plurality of stages 111, 112, and 113 is abnormal based on the sub histogram data generated for each of the plurality of stages 111, 112, and 113. In one embodiment of the present invention, the histogram data analyzing unit 140 analyzes histogram data of sub-modules constituting a high-level stage, based on sub-histogram data of a lower level stage among the plurality of stages 111, 112, It is possible to judge whether or not an abnormality has occurred.

2 is a configuration diagram of a stage constituting an analog-to-digital converter according to an embodiment of the present invention. Referring to FIG. 2, each of the plurality of stages 111, 112, and 113 may include a sub-digital-analog converter, a sub-digital-analog converter, a subtractor, and a sub-amplification module. 1 and 2, the sub analog-to-digital converter 1101 converts an input signal IS or output signals OS1, OS2, OSn output from a higher level stage to output a digital signal DS do. The sub analog-to-digital converter 1101 can output a digital signal DS corresponding to one of '00', '01', and '10'. That is, the digital signals DS1, DS2, and DSn output from the stages 111, 112, and 113 may be 1.5 bit signals having values of '00', '01', and '10'.

The sub-digital-analog converter 1102 receives the digital signal DS from the output terminal of the sub-analog-digital converter 1101. The sub-digital-analog converter 1102 converts the digital signal DS into an analog signal AS. The subtractor 1103 receives the analog signal AS from the output terminal of the sub-digital-analog converter 1102. Subtractor 1103 calculates the difference value DI between the input signal IS or the output signals OS1, OS2 and OSn and the analog signal AS. The sub-amplification module 1104 receives the difference value DI from the output terminal of the sub-subtractor 1103, and amplifies it twice. The output signal OS of the sub-amplification module 1104 is input to the low-level stage.

When a failure occurs in the sub-digital-analog converter 1102 of each of the stages 111, 112 and 113, the output value of the next stage is influenced, so that the frequency distribution of the pipeline latch value in the next stage , It is possible to judge the failure of the sub digital-to-analog converter 1102 of the previous stage (stage of the high level). The failure of the sub amplification module 1104 affects the slope of the output value of the next stage. That is, the intermediate bit value ('01') of the sub analog-to-digital converter 1101 in the next stage (lower level stage) depends on the degree of the gain (slope) of the sub-amplification module 1104 in the previous stage ') Is changed, it is possible to determine the degree of failure of the sub-amplification module 1104 of the previous stage (stage of the higher level). Therefore, the cumulative frequency distribution of the digital signals DS1, DS2, and DSn output from the stages 111, 112, and 113 is analyzed for each bit value, and the submodules (for example, sub- Sub-amplification module) can be predicted, and test time can be shortened by simple hardware addition, and test reliability can be increased.

3 is a more detailed view of a test apparatus of an analog-to-digital converter according to an exemplary embodiment of the present invention. 3, the pipeline latch 120 includes 2-bit latches 121, 122, 123 for transferring the digital signals DS1, DS2, DSn of the stages 111, 112, 113 in parallel. The 2-bit latches 121, 122 and 123 sequentially transmit the digital signals DS1, DS2 and DSn for each clock. The number of 2-bit latches 121, 122 and 123 may be determined as n (n + 1) / 2. The digital signal output from the k (k = 1, 2, ..., n) -th stage can be transferred to the histogram data generator 130 through n-k + 1 2-bit latches.

Since the analog-to-digital converter sequentially outputs the values through each stage, there are many factors that can cause a failure. If a failure occurs in the sub-digital-analog converter and the sub-amplification module included in each stage, it may be a big problem because it continuously affects the next stage. The analog-to-digital converter generates 2 bits in one stage and passes it through a digital error correction unit to some fault tolerance, but the influence is not exerted on the sub-digital-analog converter and the sub-amplification module. However, the test apparatus of the analog-to-digital converter according to the embodiment of the present invention improves the test accuracy by using the internal pipeline latch value to test the analog-to-digital converter, and reduces the test time and the pipeline data area Can be reduced.

FIG. 4 is a block diagram illustrating a histogram data generating unit of the test apparatus of the analog-to-digital converter according to an embodiment of the present invention in more detail. 4, the histogram data generating unit 130 includes a pipeline latch analyzer 131, a sub-stage histogram generating unit 133, and a histogram updater 134. [

3 through 4, the pipeline latch analyzer 131 compares the frequency of the digital signals DS1, DS2, and DSn transmitted from the pipeline latch 120 with the bit values ('00', '01' '10'). The sub-stage histogram generation unit 133 receives the cumulative frequency counts for the bit values ('00', '01', '10') of the digital signals DS1, DS2 and DSn from the pipeline latch analyzer 131. The sub-stage histogram generator 133 generates sub-histogram data for each of the stages 111, 112, and 113 in accordance with the cumulative frequency of the digital signals DS1, DS2, and DSn. The histogram updater 134 receives the sub-histogram data updated every clock, from the sub-stage histogram generator 133, and reflects the sub-histogram data in the histogram.

The analog-to-digital converter according to an embodiment of the present invention further includes a digital error correction circuit (150). The digital error correction unit 150 receives the digital signals DS1, DS2, and DSn provided from the pipeline latch 120 and outputs digital data corresponding to the input signals. The digital error corrector 150 generates, for all stages, the first bit of the 2-bit value output from the lower stage, the second bit of the 2-bit value output from the upper stage, outputs a value obtained by adding carry, carries the higher order stage side, and outputs n bits of digital data.

5 is a block diagram illustrating a pipeline latch analyzer constituting a test apparatus of an analog-to-digital converter according to an embodiment of the present invention in more detail. Referring to FIG. 5, the pipeline latch analyzer 131 includes a plurality of first AND gates 1311, a plurality of second AND gates 1312, and a plurality of counters 1313. The plurality of first AND gates 1311 determine the bit value of the first digital signal DS1 output from the higher level stage 111. [ The plurality of second AND gates 1312 receives the outputs of the plurality of first AND gates 1311 and receives the outputs of the plurality of first AND gates 1311 for each of the bit values ('00', '01', '10' Level stage 112 of the second digital signal DS2. The plurality of counters 1313 receives the output of the plurality of second AND gates 1312 and outputs the second digital signal Ds for each of the bit values (00, 01, 10) of the first digital signal DS1. (DS2) for each of the bit values ('00', '01', '10').

FIG. 6 is an exemplary diagram illustrating digital signals generated by a test apparatus of an analog-to-digital converter according to an exemplary embodiment of the present invention. In Fig. 6, the digital signals displayed in the same row are output from the pipeline latch at the same time, and the digital signals outputted in chronological order for every reference clock are recorded in order from the upper row to the lower row. The case of generating the sub histogram data for the first stage 111 from the first pipeline latch value corresponding to the first stage 111 and the second pipeline latch value corresponding to the second stage 112 For example, 3 and 6, when the histogram data generator 130 receives the digital signal DS1 of the first stage 111 as '00', '00', '01', '00' 00 ',' 01 ',' 01 ',' 00 ', and' 01 'in the order of' 01 ',' 00 ',' 10 ', and the digital signal DS2 of the second stage 112 .

The digital signal DS2 output from the second stage 112 is output after receiving the output signal OS1 from the first stage 111 and therefore the bit value of the digital signal DS1 of the first stage 111 In order to judge the failure state as much as possible, the digital signal DS2 generated one clock later in the second stage 112 should be considered. Accordingly, the failure of the first stage 111 is detected using the data indicated by the dashed line in Fig.

In the example of FIG. 6, when the bit value of the digital signal DS1 of the first stage 111 is '00', the accumulation of the bit value '00' of the digital signal DS2 of the corresponding second stage 112 The value is 2, the accumulated value of '01' is 1, and the accumulated value of '10' is 0. When the bit value of the digital signal DS1 of the first stage 111 is '01', the accumulated value of the bit value '00' of the digital signal DS2 of the corresponding second stage 112 is 0, The accumulated value of '01' is 2, and the accumulated value of '10' is 0. 00 ',' 01 ', and' 10 'of the digital signal DS2 of the corresponding second stage 112 when the bit value of the digital signal DS1 of the first stage 111 is' 10' Are all zero.

FIG. 7 is a diagram illustrating sub-histogram data generated by a test apparatus of an analog-to-digital converter according to an exemplary embodiment of the present invention. 7, 'DNL [0]' for calculating the differential non-linearity error value is a value obtained by subtracting 'DNL [0]' from a lower stage in the case where the bit value of the digital signal DS of the upper stage is '00' 'DNL [2]' is a cumulative value of the digital signal of the lower stage when the bit value of the digital signal DS of the upper stage is '01' 'Indicates the accumulated value of the digital signal of the lower stage when the bit value of the digital signal DS of the higher stage is' 10'. The reason why the bit values of the next stage are accumulated for each of 'DNL [0]', 'DNL [1]' and 'DNL [2]' are '00' and '10' , It is possible to obtain the cumulative frequency number of the bit value '01' at the next stage from the value obtained by subtracting the '10' cumulative frequency.

The gain value can be calculated only by the cumulative value when the bit value of the digital signal DS of the stage is '01'. That is, the sum of the cumulative frequency numbers when the bit value is '00' and the bit value '10' is obtained from the value obtained by subtracting the cumulative frequency number of '01' from the total frequency number, The gain value can be calculated from the ratio of the cumulative value in the case of '01', so that only the cumulative value in the case of '01' can be constructed as the sub histogram data for the gain calculation.

FIG. 8 is a configuration diagram of a histogram data analysis unit constituting a test apparatus of an analog-to-digital converter according to an embodiment of the present invention. 8, the histogram data analysis unit 140 includes an adder 141, a subtractor 142, The adder 141 adds the cumulative frequency ('n _{j +1} (10)') of the upper bit value ('10') of the sub histogram data to the lower bit stage ('N _{j +1} (00)'). The subtractor 142 subtracts the cumulative frequency of the upper bit value ('10') from the cumulative frequency ('n _{j +1} (00)') of the lower bit value ('00') of the sub- Subtracts the number ('n _{j +1} (10)'). The divider 143 divides the cumulative frequency of the output value of the adder 141, that is, the cumulative frequency ('n _{j +1} (10)') of the upper bit value ('10' (N _{j +1} (01) ') of the intermediate bit value (' 01 ') of the sub histogram data for the lower level stage to the cumulative frequency number (' n _{j +1} Share it.

Referring to FIGS. 2 and 8, when a failure occurs, the influence of the sub-digital-analog converter 1102 affects the output value of the next stage. For example, if the Differential Non-Linearity error of the sub-digital-to-analog converter 1102 of the previous stage (upper level stage) has a positive value, The difference value DI obtained by subtracting the signal (voltage) value is output to the next stage (stage at the lower level).

According to the embodiment of the present invention, the frequency of the pipeline latch value at the next stage is measured according to the characteristic of the histogram test for checking the frequency of the digital signal according to the repetitive input to determine whether or not the failure occurs. If a failure occurs in the previous stage, the frequency of the value is measured to be low when examining the frequency of occurrence of a specific value through repetitive execution. This difference can determine the failure of the digital-to-analog converter inside the stage.

In one embodiment of the present invention, the histogram data analyzing unit 140 analyzes the histogram data of the sub-digital-analog converter (stage) of the previous stage (stage of the upper level) based on the output value of the subtracter 142 of the next stage 1102 can be calculated. The failure of the differential nonlinear error (DNL) of the sub-digital-analog converter 1102 can be determined through a differential nonlinear error value calculated according to the following equation (1).

[Formula 1]

In the equation 1, 'j' is the number of the stage, 'dnl _j ' is the differential nonlinear error value of the previous stage, and 'n _{j +1} (00)' is the accumulation of the bit value '00''N _{j +1} (10)' represents the cumulative frequency of the bit value '10' of the digital signal of the next stage, and 'ideal' represents the reference DNL value determined by the design of the analog-to-digital converter. For example, in order to calculate the DNL [0] value of the first stage (j = 1), among the cases where the digital signal of the first stage 111 is '00' The cumulative frequency of the bit value '00' and the cumulative frequency of '10'. Each result is stored as a substage histogram.

The failure of the sub amplification module 1104 affects the slope of the output value of the next stage (lower level stage). That is, the cumulative frequency of the intermediate bit value ('01') of the sub-analog-digital converter 1102 of the next stage and the cumulative frequency of the intermediate bit value , And the cumulative frequency number of both end bit values ('00', '10').

For example, when the sub-amplification module 1104 has a larger gain value as compared with the case where no failure occurs in the sub-amplification module 1104, the cumulative frequency number of the digital signals of the next stage by bit value becomes steeper The ratio of the '01' bit value in the digital signal of the next stage becomes smaller than the '00' and '10' bit value. Conversely, when the sub-amplification module 1104 of the previous stage has a small gain, the ratio of the '01' bit value in the digital signal of the next stage is measured more than in the ideal case.

The histogram data analyzing unit 140 analyzes the histogram data of the sub-amplification module 1104 of the previous stage (higher level stage) from the output value of the divider 143 of the next stage (lower level stage) The gain can be calculated. The failure of the sub-amplification module 1104 can be determined based on a gain (slope) value calculated according to Equation 2 below.

[Formula 2]

In Equation 2, 'j' denotes the stage number, 'gain _j ' denotes the gain value of the sub-amplification module of the previous stage, 'n _{j +1} (00)' denotes the bit value '00' a cumulative total, "n _{j +1} (10)" is the cumulative total of the bit values '10' of the digital signal of the next stage, "n _{j +1} (01), the bit value of the digital signal of the next stage, 01 ', and' ideal 'denotes a reference gain value determined according to the design of the analog-to-digital converter.

According to the embodiment of the present invention, it is possible to judge whether or not a fault exceeding the allowable range has occurred in the previous stage by using the bit value cumulative frequency distribution of the digital signal of the next stage. According to the embodiment of the present invention, a test result similar to that of a lot of tests is displayed, thereby shortening the test time and increasing the reliability of the test result.

It is to be understood that the above-described embodiments are provided to facilitate understanding of the present invention, and do not limit the scope of the present invention, and it is to be understood that various modifications are possible within the scope of the present invention. It is to be understood that the technical scope of the present invention should be determined by the technical idea of the claims and the technical scope of protection of the present invention is not limited to the literary description of the claims, The invention of the present invention.

100: Test equipment for analog-to-digital converters
110: Analog-to-digital converter
1101: Sub-analog-to-digital converter
1102: a sub-digital-analog converter
1103: Sub subtractor
1104: Sub amplification module
111, 112, 113:
114: 2-bit ADC
120: Pipeline latch
121, 122, 123: 2 bit latch
130: histogram data generation unit
131: Pipeline Latch Analyzer
1311: first AND gate
1312: second AND gate
1313: Counter
133: Substage histogram generation unit
134: Histogram Updater
140: histogram data analysis unit
141: adder
142:
143:
150: digital error correction unit

Claims (20)

1. A test apparatus for an analog-to-digital converter comprising a plurality of stages connected in series and sequentially outputting digital signals corresponding to input signals,
A histogram data generation unit for accumulating the frequency numbers of digital signals output from each of the plurality of stages for each bit value to generate sub-histogram data for each of the plurality of stages; And
And a histogram data analyzing section for determining whether each of the plurality of stages is abnormal based on the sub-histogram data generated for each of the plurality of stages. The method according to claim 1,
Wherein the histogram data analyzing unit determines whether the sub-module constituting the high-level stage is abnormal based on the sub-histogram data for the low-level stage among the plurality of stages. 3. The method of claim 2,
Wherein each of the plurality of stages includes:
A sub analog-to-digital converter for converting the input signal or an output signal output from a higher level stage and outputting the digital signal;
A sub-digital-analog converter for converting the digital signal into an analog signal;
A subtractor for calculating a difference value between the input signal or the output signal and the analog signal; And
And a sub amplification module for amplifying the difference value by a factor of two. The method of claim 3,
Wherein the submodule comprises at least one of the sub-digital-analog converter and the sub-amplification module. The method of claim 3,
Wherein the sub-digital-analog converter outputs the digital signal corresponding to one of '00', '01', and '10'. The method of claim 3,
Wherein the histogram data analyzing unit comprises:
An adder for adding the cumulative frequency of the upper bit value of the sub-histogram data to the cumulative frequency of the lower bit value for the lower-level stage;
A subtractor for subtracting the cumulative frequency of the lower-bit value from the cumulative frequency of the lower-bit value of the sub-histogram data for the lower-level stage; And
And a divider that divides the cumulative frequency of the intermediate bit values of the sub histogram data for the lower level stage from the output value of the adder. The method according to claim 6,
Wherein the histogram data analyzing section calculates a differential nonlinear error value of the sub digital-analog converter based on an output value of the subtractor. The method according to claim 6,
Wherein the histogram data analyzing unit calculates the gain of the sub amplification module from the output value of the divider. 6. The method of claim 5,
Further comprising a pipeline latch including 2-bit latches for transmitting, in every clock cycle, a digital signal output from each of the plurality of stages to the histogram data generation unit in parallel, . 10. The method of claim 9,
Wherein the histogram data generating unit comprises:
A pipeline latch analyzer for accumulating the number of frequencies of the digital signal transmitted from the pipeline latch for each bit value;
A sub-stage histogram generator for generating sub-histogram data for each stage according to the accumulated frequency of the digital signal; And
And a histogram updater for reflecting the sub-histogram data updated for each clock in the histogram. 11. The method of claim 10,
Said pipeline latch analyzer comprising:
A plurality of first AND gates for determining a bit value of a first digital signal output from the higher level stage;
A plurality of second AND gates receiving the outputs of the plurality of first AND gates and determining a bit value of a second digital signal output from the lower level stage for each bit value of the first digital signal; And
And a plurality of counters receiving the outputs of the plurality of second AND gates and accumulating and counting the bit values of the second digital signals according to the bit values of the first digital signals. A plurality of stages connected in series and sequentially outputting digital signals corresponding to input signals;
A histogram data generation unit for accumulating the frequency numbers of digital signals output from each of the plurality of stages for each bit value to generate sub-histogram data for each of the plurality of stages; And
And a histogram data analyzing section for determining whether each of the plurality of stages is abnormal based on the sub-histogram data generated for each of the plurality of stages. 13. The method of claim 12,
Wherein the histogram data analyzing unit determines whether the sub-module constituting the high-level stage is abnormal based on the sub-histogram data of the low-level stage among the plurality of stages. 14. The method of claim 13,
Wherein each of the plurality of stages includes:
A sub analog-to-digital converter for converting the input signal or an output signal output from a higher level stage and outputting the digital signal;
A sub-digital-analog converter for converting the digital signal into an analog signal;
A subtractor for calculating a difference value between the input signal or the output signal and the analog signal; And
And a sub amplification module for amplifying the difference value by a factor of two. 15. The method of claim 14,
Further comprising pipeline latches including 2-bit latches for delivering, in every clock, a digital signal output from each of the plurality of stages to the histogram data generator in parallel. A method for testing an analog-to-digital converter comprising a plurality of stages connected in series and sequentially outputting digital signals corresponding to input signals,
Generating sub-histogram data for each of the plurality of stages by accumulating the number of frequency of digital signals output from each of the plurality of stages for each bit value; And
And determining whether each of the plurality of stages is abnormal based on the sub-histogram data generated for each of the plurality of stages. 17. The method of claim 16,
Wherein the step of judging whether or not the abnormality is judged is judged based on sub-histogram data of a lower-level stage among the plurality of stages, judging whether the sub-module constituting the higher-level stage is abnormal. 18. The method of claim 17,
Wherein the step of determining the abnormality comprises:
The adder adding the cumulative frequency number of the upper bit value of the sub histogram data and the cumulative frequency number of the lower bit value for the lower level stage;
Subtracting a cumulative frequency of the lower-bit value from the cumulative frequency of the lower-bit value of the sub-histogram data for the lower-level stage; And
Dividing the cumulative frequency of the intermediate bit values of the sub-histogram data for the lower-level stage from the output value of the adder. 19. The method of claim 18,
Wherein the step of determining the abnormality calculates the differential nonlinear error value of the sub-digital-analog converter of the submodule based on the output value of the subtracter. 19. The method of claim 18,
Wherein the step of determining the abnormality calculates a gain of the sub-amplification module of the sub-module from an output value of the divider.

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