KR20050094066A - Bist method for analogue-to-digital converter - Google Patents

Abstract

The present invention relates to a built-in self test (BIST), and more particularly, to a BIST method capable of efficiently performing self-diagnosis of an analog-to-digital converter. In the present invention, a periodic analog signal is inputted to the ADC to obtain a quantization error through the difference between the analog input signal and the signal passed through the ADC and the DAC. QE occurs even when there is no actual failure.In this QE value, a proper QE value is determined by considering the noise component and signal distortion through other test circuits, and the QE value exceeding this reference value is regarded as an error. Declares a malfunction.

Description

Self-diagnosis method of analog-to-digital converter {BIST method for analogue-to-digital converter}

The present invention relates to a built-in self test (BIST), and more particularly, to a BIST method capable of efficiently performing self-diagnosis of an analog-to-digital converter.

BIST is a testing technology that judges / declares the failure of itself rather than externally determining the failure of a unit. In the case of analog devices, it is very difficult to establish a criterion for determining whether there is a failure, and in particular, in the case of an analog-to-digital converter (ADC), in which analog and digital signals are mixed, many test methodological improvements are required. Is the reality.

ADC's conventional self-test methodology used self-diagnosing faults through differential nonlinear errors (DNL) or cumulative nonlinear errors (INL) using sophisticated, high-quality test signals. As a test signal, a ramp signal, which is a type that is easy to determine whether there is a failure, is frequently used. When this signal is generated by itself and passed through the ADC, it outputs a binary coded signal in digital form. Assuming that the signal goes through the ideal digital-to-analog converter (DAC) again, the difference between this output and the input ramp signal Compare and analyze the INL and DNL to determine the failure. When the output of the ADC is compared with the input signal through several stages of comparators and there is a difference of one or more least significant bits (LSBs), a failure is declared. In this case, as shown in the above example, various types of failures are determined.

Fig. 1A shows a conventional BIST block diagram using a ramp signal, and Fig. 1B shows an example of fault determination using a ramp signal. The ramp signal generated from the ramp signal generator 11 is applied to the test target ADC 13, and the digital signal output from the ADC 13 is compared with the input ramp signal by the error detector 15 and the BIST controller 17 The failure is judged by FIG. 1B shows an example of failure determination for each failure type, that is, a missing code error, a monononocity error, a DNL error, and an INL error using a ramp signal.

In the case of BIST, price efficiency is the most important performance determinant. In the existing external testing method, about 50% of the manufacturing cost of analog devices is made up of the testing cost, and it is intended for the system-on-chip (SoC) orientation to reduce the cost inefficiency and implement the system in one chip. Failure diagnosis (BIST) is necessary.

However, in the conventional ADC BIST technology, there are many problems in this cost efficiency. First of all, the ramp signal, which is mainly used as a testing signal, has a lot of difficulty in generating in a chip, and thus, it has practically no cost efficiency. Because mixed signal test of analog and digital could not be performed in the same dimension, it is necessary to determine the failure by digital output alone, and therefore requires very high quality test signal. There are a lot of difficulties in price or chip area to obtain such high quality test signals. In addition, since the failure determination algorithm is very diverse in each case, the complexity and chip area and complexity increase.

These problems require a new type of ADC BIST methodology that is more cost-competitive and has an easy fault determination algorithm. It should be more efficient in terms of price / area than the ADC's existing testing method, and it is very urgent to develop a testing methodology that can determine whether there is a failure with a testing signal that is more easily generated.

Accordingly, the present inventors have developed the present invention to overcome the disadvantages of the conventional BIST test, especially in the test of the ADC. In general, the ADC is the most basic analog unit in an SoC. Research shows that most SoCs include a pair of DACs that convert the digital signal back to analog with the ADC. Therefore, the present invention intends to determine the presence or absence of the ADC failure using this DAC.

More specifically, the BIST method of the present invention will be described. In the present invention, the quantization error (hereinafter referred to as Q.E) is obtained through the difference between the original analog input signal and the signal passed through the ADC and DAC using the periodic signal. QE occurs even when there is no actual failure.In this QE value, a proper QE value is determined by considering the noise component and signal distortion through other test circuits, and the QE value exceeding this reference value is regarded as an error. Declares a malfunction.

In the present invention, the ADC and the DAC are regarded as one pair. That is, as mentioned above, in most SoCs, the ADC and the DAC exist together, so the DAC is additionally needed in the method for ADC testing, and if a failure is determined due to a malfunction of the DAC rather than the ADC, Also, the entire ADC-DAC will be declared as faulty. ADCs and DACs are very basic analog devices. For the basic purpose of BIST, they only detect / declare faults and do not correct them.

2 is a schematic flowchart for explaining an ADC BIST method according to the present invention. The periodic analog input signal 20 is input to the AD converter 21, the signal output from the AD converter 21 is converted back into the analog output signal 25 from the DA converter 23, and then the AD converter 21 ) Compares the analog input signal 20 inputted with the analog output signal 25 outputted from the DA converter 25 to obtain a QE value and analyzes the same to determine and declare a failure.

The Q.E value can vary depending on the type of ADC 21 and the specific resolution. The analog input signal 20 is a periodic signal. Generally, a sine wave signal, a triangular wave signal, a sawtooth wave signal, a square wave signal, and the like may be used to determine whether there is a failure by providing a proper change in the reference QE value. . In general, the periodic signals can be detected if all signals can be delayed in the same phase by repeating the same pattern.

To declare a failure of the ADC 21, first of all, the establishment of the failure pattern is very important. First of all, if you think about the factors that cause failures, they can be divided into catastrophic faults and parametric faults. The catastrophic failure is the failure of a component, for example a switch, each node or element, such as a short circuit, a disconnection, or a breakdown. Parameter failures are failures that result from minor changes in the parameters of a component, for example the process parameters of a MOS, or from a specified specification. In general, in case of analog devices, disaster failure factors have a much greater influence than parameter failure factors, and failure types can be analyzed through each block failure simulation assuming failure caused by disaster failure factors.

As a result of injecting various fault signals, the Q.E value between the original analog signal and the analog output signal passed through the ADC and DAC can be determined and declared. Fig. 3 shows an example in which an arbitrary failure assuming a disaster failure factor is injected.

<Comparison with conventional technology>

The prior art is a method of comparatively analyzing the output waveform using a sophisticated ramp signal, a frequency fraction method, or a method of analyzing the signal-to-noise ratio in the frequency domain by Fourier transforming a sine wave. In such conventional methods, there are many difficulties in generating a sophisticated test signal or an increase in the area of the chip area due to an increase in the circuit complexity of the fault determination area. It also has the disadvantage of having trouble diagnosing unless the correct input test signal is known.

However, in the test method according to the present invention, since a periodic signal such as a sine wave is used as a test signal, there are many advantages in signal generation and there is an advantage in that it is possible to determine whether there is a failure by simply observing the maximum QE value. In addition, by using the test input signal to diagnose the fault has the advantage that can be diagnosed without being affected by the state of the input signal much. Even in the case of using signals such as triangular waves or square waves other than sine waves, it is possible to determine / declare whether there is a failure sufficiently only by changing the reference QE value. Therefore, the BIST method according to the present invention can determine good / no good of a device regardless of the type of test signal, and in particular, it is possible to use a low-cost test signal such as a sine wave and a triangular wave.

4A and 4B show examples of fault detection through the BIST method of the present invention. Fig. 4A shows that the ADC device finally passed as an example of failure. Fig. 4B shows a failure portion (waveform portion indicated by " 0 ") and a pass portion (waveform portion indicated by " 1 ") as a result of fault detection by injecting an arbitrary fault signal. The results of Figs. 4A and 4B are obtained by using the adder and the inverter Q.E, which is the difference between the input test signal of the ADC and the output of the DAC. Through the comparator, if the QE value is lower than the specified reference value, it is regarded as normal operation, and a pass is declared. If a failure occurs, an error exceeding the standard QE value is detected. do. Pass declarations are arbitrarily marked with a value of "1", and Fail has a value of "0".

The BIST method according to the present invention has several advantages over the existing test method. First, from a technical point of view, since the Q.E value, which is the difference between the original signal and the signal passed through its ADC and DAC, is used to determine whether there is a failure, the sophistication of the test signal itself is not greatly required. In addition, if the test signal is a periodic function, there is an advantage that it is possible to sufficiently determine whether there is a failure by setting an appropriate reference Q.E value. The economic effect is a reduction in testing costs. The reduction in testing costs is due to the use of inexpensive signals such as sinusoidal waves and a simple troubleshooting methodology. This reduction in testing costs is the biggest advantage of the proposed BIST methodology. Also, ADC or DAC are very basic analog units on SoC, and troubleshooting testing of these basic units is very important in the whole manufacturing process. There is a commercial advantage that such failure diagnosis can be performed simultaneously with price / area on SoC, rather than the conventional external application method or the expensive conventional BIST method. The new efficient ADC BIST structure is expected to make a big difference in SoC development.

1A and 1B are exemplary diagrams of failure determination using a conventional BIST block diagram and a ramp signal.

2 is a schematic flowchart for explaining a BIST method according to the present invention;

Figure 3 is an exemplary diagram in the case of injecting a random failure signal assuming disaster failure factors.

4A and 4B are examples of fault detection through the BIST method of the present invention.

Claims (3)

As a method of testing an analog-to-digital converter (ADC), a device under test, using a BIST method, Inputting a periodic analog input signal to an input terminal of the ADC, which is the device under test, Inputting a digital signal output from the ADC to a digital-to-analog converter (DAC), Obtaining a quantization error (Q.E) by comparing the difference between the analog output signal output from the DAC and the analog input signal applied to the ADC as the device under test; And determining that the ADC has failed when the Q.E value is greater than a predetermined reference value. The method of claim 1, wherein the periodic analog input signal input to the ADC is a sine wave. The method of claim 1, wherein the periodic analog input signal input to the ADC is a signal capable of time-delaying a signal in the same phase by repeating a signal pattern of the same type, such as a triangular wave signal, a sawtooth wave signal, and a square wave signal. Self-diagnosis method of analog-to-digital converter.