KR20080008045A - Pad layout of semiconductor device - Google Patents

Abstract

A pad layout of a semiconductor device is provided to enhance a gap-fill characteristic of an SOC(Spin On Glass) film by securing a space region by removing a first metal wiring formed on a dummy region of a pad region. A pad layout of a semiconductor device includes a plurality of first metal wirings(113), a plurality of pads(115), a plurality of first metal wirings for a peripheral circuit(119), and a dummy line pattern(117). The first metal wirings are formed on a pad region(111) in a slit type and spaced apart from each other at predetermined intervals in a one side direction. The plurality of pads are formed on both sides of first metal wirings. The plurality of first metal wirings for the peripheral circuit are spaced apart from the plurality of pads outside the pads at predetermined intervals and formed in a direction perpendicular to the plurality of first metal wirings. The dummy line pattern is formed between the pads and the first metal wirings for the peripheral circuit.

Description

Pad layout of semiconductor device {PAD LAYOUT OF SEMICONDUCTOR DEVICE}

1A and 1B are pad layout diagrams of a semiconductor device according to the prior art.

2a to 2e are photographs for explaining the problem of the pad layout of the semiconductor device according to the prior art.

3 is a pad layout diagram of a semiconductor device according to a first embodiment of the present invention;

4 is a pad layout diagram of a semiconductor device according to a second exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pad layout of a semiconductor device. In particular, when a spin on glass (SOG) film is formed on an upper portion of a first metal wiring constituting a pad, a semiconductor device capable of improving a gap-fill characteristic is disclosed. Pad layout.

In general, a metal pad is disposed on the top of a semiconductor device having a laminated structure. Such a metal pad is provided for electrical connection with an external circuit in a packaging process for a manufactured semiconductor device, that is, several semiconductor chips manufactured in a wafer state.

Meanwhile, as an interlayer insulating film of a metal pad, a spin on glass (SOG) having a lower dielectric constant than that of other oxide films is used. However, SOG has a weaker strength than other oxides, causing pad failure during evaluation after the pad process.

1A and 1B are diagrams illustrating pad layouts of a semiconductor device according to the related art, which will be described using a double data rate (DDR2) product of 512Mb as an example. 1B illustrates a dummy pattern of the pad area.

Referring to FIG. 1A, a plurality of first metal wires 13 having a slit shape and spaced at regular intervals in one direction are formed in a central portion of the pad region 11. In addition, a plurality of pads 15 are formed at both sides of the first metal wire 13.

In addition, a plurality of first metal wires 17 for peripheral circuits are formed on the pad 15 and spaced apart from the pad 15 at a predetermined interval and perpendicular to the first metal wires 13.

In this case, the pad 13 and the first metal wiring 17 for the peripheral circuit are spaced apart at an interval of 3.5 to 10 μm.

Here, the first metal wiring 17 for the peripheral circuit is used as a ground voltage line, an address line, or the like.

Referring to FIG. 1B, a plurality of first metal wires 23 having a slit shape and spaced at a predetermined interval in one direction are formed in a central portion of the pad region 21.

In addition, a plurality of first metal wires 25 for peripheral circuits are formed on the outer side of the first metal wire 23 at regular intervals in a direction perpendicular to the first metal wire 23.

At this time, the first metal wiring 23 and the first metal wiring 25 for the peripheral circuit are spaced apart at an interval of 3.5 ~ 10μm.

Here, the first metal wiring 25 for the peripheral circuit is used as a ground voltage line, an address line, and the like.

2a to 2e are photographs for explaining the problem of the pad layout of the semiconductor device according to the prior art, Figures 2a to 2d is a planar photograph, Figure 2e is a sectional photograph.

Referring to FIGS. 2A to 2E, in the conventional pad layout, an interlayer insulating layer (not shown) such as an SOG (Spin On Glass) is formed on an entire surface including the first metal wires 13 and 23. It happens that there is no gap-fill. In this case, in the subsequent thermal process, the air in the non-gap-filled portion expands causing cracks A to the vulnerable portions (arrows indicated).

In the above-described method for forming a pad of a semiconductor device according to the related art, a space is formed between the first metal wires 13 and 23 and the first metal wires 17 and 25 for the peripheral circuit formed in the center portion of the pad area. ) Is present, so that gap-filling may not occur due to a density difference in forming an interlayer insulating film such as SOG (Spin On Glass). This causes a crack (A) during the subsequent thermal process to corrode the first metal wires (13, 23) in the package to reduce the reliability of the device.

The present invention has been made to solve the above problems, and can improve the gap-fill characteristics of the SOG film when the SOG film is formed on the first metal wiring constituting the pad. The purpose is to provide a pad layout of a semiconductor device.

The pad layout of the semiconductor device of the present invention for achieving the above object, a plurality of first metal wires having a slit form in the center of the pad region, spaced apart at regular intervals in one direction; A plurality of pads formed on both sides of the plurality of first metal wires; A plurality of first metal wires for peripheral circuits spaced apart from the pads at a predetermined distance from the outside of the plurality of pads and formed in a direction perpendicular to the plurality of first metal wires; And a dummy line pattern formed between the pad and the first metal wiring for the peripheral circuit.

In addition, the present invention is formed in the dummy region of the pad region, the first metal wiring for the peripheral circuit formed in the outermost of the dummy region; And a space region formed inside the first metal wiring for the peripheral circuit, wherein the space region is formed to be 10 μm × 10 μm or more.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 illustrates a pad layout of a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 3, a plurality of first metal wires 113 having a slit shape and spaced at regular intervals in one direction are formed in a central portion of the pad region 111. In addition, a plurality of pads 115 are formed at both sides of the first metal wire 113.

In addition, a plurality of first metal wires 119 for peripheral circuits are formed on the outside of the pad 115 at a predetermined distance from the pad 115 and in a direction perpendicular to the first metal wires 113.

In this case, the peripheral metal first metal wire 119 is preferably used as a ground voltage line, an address line, or the like.

A dummy line pattern 117 is formed between the pad 115 and the first metal wiring 119 for the peripheral circuit.

In this case, the gap between the pad 115 and the dummy line pattern 117 may be formed to be 3.5 μm or less.

In addition, the dummy line pattern 117 may be connected to the first metal wire 119 for the peripheral circuit without floating.

Accordingly, by forming the dummy line pattern 117 in the space area between the first metal wiring 113 and the first metal wiring 119 for the peripheral circuit, the difference in density between the patterns is reduced to form an upper surface of the entire surface. When forming a SOG (Spin On Glass) film, a gap-fill may be improved.

4 is a pad layout diagram of a semiconductor device according to a second exemplary embodiment of the present invention, illustrating a dummy region of a pad region.

Referring to FIG. 4, the first metal wire 213 for the peripheral circuit is formed in the outermost region of the pad region 211.

At this time, it is preferable to form the space region 215 or more in the space of the first metal wiring 213 for the peripheral circuit 215 10μm or more.

In the above structure, when the gap between the pad 115 and the dummy line pattern 117 as shown in FIG. 3 is not formed to be 3.5 μm or less, the first metal wire 113 having a slit shape in the center thereof is formed. The space area 215 is obtained by removing the space.

Accordingly, since there is no pattern in the center portion when forming a spin on glass (SOG) film, a gap-fill characteristic can be improved.

Meanwhile, in the embodiment of the present invention, only the pad region has been described as an example, but the present invention may be applied to the ferry region.

As described above, in the pad layout of the semiconductor device according to the present invention, a gap of the SOG film is formed when a spin on glass (SOG) film is formed on the first metal wire by inserting a dummy line pattern around the first metal wire constituting the pad. Improves the gap-fill characteristics to prevent cracking during subsequent thermal processes, thereby providing the effect of preventing IDD failures.

In addition, the present invention provides an effect of improving a gap-fill characteristic when forming an SOG film by removing a first metal wiring formed in a dummy region of a pad region to secure a space region.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (3)

A plurality of first metal wires having a slit shape at a central portion of the pad area and spaced apart at a predetermined interval in one direction; A plurality of pads formed on both sides of the plurality of first metal wires; A plurality of first metal wires for peripheral circuits spaced apart from the pads at a predetermined distance from the outside of the plurality of pads and formed in a direction perpendicular to the plurality of first metal wires; And Dummy line pattern formed between the pad and the first metal wiring for the peripheral circuit Pad layout of a semiconductor device comprising a. The pad layout of claim 1, wherein an interval between the pad and the dummy line pattern is 3.5 μm or less. A first metal wire formed in the dummy area of the pad area, the first metal wire for the peripheral circuit formed at the outermost part of the dummy area; And And a space region formed inside the first metal wiring for the peripheral circuit, wherein the space region is formed to be 10 μm × 10 μm or more.

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