KR20080002593A - Semiconductor memory circuit in which the operation mode is set up by a mrs command - Google Patents

Semiconductor memory circuit in which the operation mode is set up by a mrs command Download PDF

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KR20080002593A
KR20080002593A KR1020060061490A KR20060061490A KR20080002593A KR 20080002593 A KR20080002593 A KR 20080002593A KR 1020060061490 A KR1020060061490 A KR 1020060061490A KR 20060061490 A KR20060061490 A KR 20060061490A KR 20080002593 A KR20080002593 A KR 20080002593A
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mrs
signal
unit
generator
output
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Korean (ko)
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노영규
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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Abstract

A semiconductor memory device setting an operation mode by an MRS(Mode Register Set) command is provided to prevent the change of the operation mode by setting the operation mode by an MRS only one time, even though external noise or a random MRS command is inputted. An MRS(Mode Register Set) generation part(110) generates an MRS command from an MRS input signal applied from the outside. An MRS level maintaining part(130) receives an output signal of the MRS generation part, and maintains the output of the MRS generation part in response to the fed-back output signal regardless of additional input of an MRS input signal from the outside.

Description

ＭＲＳ 명령에 의해 동작 모드가 설정되는 반도체 메모리 장치{Semiconductor Memory Circuit in which the Operation Mode is set up by a MRS Command}Semiconductor Memory Device in which the Operation Mode is Set Up by a MRS Command

도 1은 본 발명에 따른 MRS 명령에 따라 동작 모드가 설정되는 반도체 메모리 장치를 나타낸 회로도이다.1 is a circuit diagram illustrating a semiconductor memory device in which an operation mode is set according to an MRS command according to the present invention.

본 발명은 반도체 메모리 장치에 관한 것으로, 보다 구체적으로는 MRS(Mode Register Set) 명령(command)에 의하여 동작 모드가 설정되는 반도체 메모리 장치에 관한 것이다.The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device in which an operation mode is set by a mode register set (MRS) command.

MRS 명령은 SDRAM(Synchronous Dynamic Random Access Memory)의 동작 중 그 시작을 알리는 중요한 명령으로, 외부 명령들의 조합에 의해 칩 내부에서 생성된다. 상기 SDRAM은 CAS 레이턴시(latency) 및 버스트 랭스(burst length)를 프로그 램화하여 가지고 있으며, 상기 MRS 명령에 의해 외부에서 들어온 어드레스 조합에 의한 코딩에 맞추어 CAS 레이턴시 및 버스트 랭스 등의 동작 모드를 발생(설정)시킨다. The MRS instruction is an important instruction that signals the start of the operation of the synchronous dynamic random access memory (SDRAM). The MRS instruction is generated in the chip by a combination of external instructions. The SDRAM programs CAS latency and burst length and generates an operation mode such as CAS latency and burst length in accordance with coding by an address combination input from the outside by the MRS instruction. )

그런데, 종래 SDRAM은 외부의 노이즈가 입력되거나 임의의 MRS 입력신호가 입력되면 내부에서 다시 MRS에 따른 새로운 동작 모드가 발생할 수 있도록 설계되어 있어, 초기에 결정된 MRS 동작 모드 방식이 변하게 되는 문제점이 있었다. 이로 인해 SDRAM은 새롭게 발생된 MRS 명령에 의해 원치 않는 동작을 수행하게 되어 동작 오류가 발생되는 문제점이 있었다.However, the conventional SDRAM is designed to generate a new operation mode according to the MRS again when external noise is input or an arbitrary MRS input signal is input, thereby changing the MRS operation mode determined initially. As a result, the SDRAM performs an undesired operation by the newly generated MRS command, causing an operation error.

따라서, 본 발명이 이루고자 하는 기술적 과제는 외부의 노이즈나 임의의 MRS 명령이 입력되더라도, MRS에 의한 동작 모드 설정은 초기 한 번만 진행되도록 하여 동작 모드의 변경을 방지할 수 있는 반도체 메모리 장치를 제공하는데 있다.Accordingly, a technical object of the present invention is to provide a semiconductor memory device capable of preventing the operation mode from changing once the operation mode is set only once, even if external noise or an arbitrary MRS command is input. have.

상기 기술적 과제를 달성하기 위하여, 본 발명은 외부로부터 인가되는 MRS 입력 신호로부터 MRS 명령을 발생시키는 MRS 발생부와; 상기 MRS 발생부의 출력 신호를 피드백하여 입력받고, 상기 MRS 명령에 의해 동작 모드가 일단 설정되면, 외부로부터의 MRS 입력신호의 추가적인 유입에 상관없이 상기 피드백된 출력신호에 응답하여 상기 MRS 발생부의 출력을 유지시키는 MRS 레벨 유지부를 포함하여 구성 되는 반도체 메모리 장치를 제공한다.In order to achieve the above technical problem, the present invention and the MRS generation unit for generating an MRS command from the MRS input signal applied from the outside; The MRS generator outputs the MRS generator in response to the fed back output signal, and once the operation mode is set by the MRS command, the MRS generator outputs the MRS generator in response to the feedback signal. Provided is a semiconductor memory device including an MRS level holding unit for holding.

본 발명에서, 상기 MRS 발생부는 초기 파워업 신호에 응답하여 소정 노드를 풀다운 구동하는 풀다운 소자와; 상기 노드의 신호를 래치시키는 래치부와; 외부로부터 인가되는 상기 MRS 입력 신호와 상기 래치부의 출력 신호를 논리연산하여 그 결과를 출력하는 논리부를 포함하는 것이 바람직하다.In the present invention, the MRS generation unit and the pull-down element for driving down a predetermined node in response to the initial power-up signal; A latch unit for latching a signal of the node; It is preferable to include a logic unit for performing a logic operation on the MRS input signal and an output signal of the latch unit applied from the outside to output the result.

본 발명에서, 상기 래치부는 상기 노드의 신호를 래치시킴과 동시에 반전시켜 출력하는 것이 바람직하다.In the present invention, the latch unit may latch the signal of the node and at the same time invert the output.

본 발명에서, 상기 논리부는 논리곱 연산을 수행하는 것이 바람직하다.In the present invention, it is preferable that the logic unit performs an AND operation.

본 발명에서, 상기 MRS 레벨 유지부는 상기 MRS 발생부의 출력 신호를 소정 구간 지연시켜 출력하는 지연회로부와; 상기 지연 회로부로부터 입력되는 신호에 따라 상기 MRS 발생부의 출력신호를 제어하는 제어부를 포함하는 것이 바람직하다.In the present invention, the MRS level maintenance unit and the delay circuit unit for delaying the output signal of the MRS generation section by a predetermined period; It is preferable to include a control unit for controlling the output signal of the MRS generation unit in accordance with the signal input from the delay circuit unit.

본 발명에서, 상기 제어부는 소정 MRS 인에이블신호에 응답하여 인에이블되는 것을 특징으로 한다.In the present invention, the controller is enabled in response to a predetermined MRS enable signal.

본 발명에서, 상기 제어부는 상기 지연회로부로부터의 신호와 상기 MRS 인에이블신호를 버퍼링하는 버퍼와; 상기 버퍼의 출력신호에 응답하여 상기 노드를 풀업구동하는 풀업소자를 포함하는 것이 바람직하다.In the present invention, the control unit includes a buffer for buffering the signal from the delay circuit unit and the MRS enable signal; And a pull-up element for pull-up driving the node in response to an output signal of the buffer.

이하, 실시예를 통하여 본 발명을 더욱 상세히 설명하기로 한다. 이들 실시예는 단지 본 발명을 예시하기 위한 것이며, 본 발명의 권리 보호 범위가 이들 실시예에 의해 제한되는 것은 아니다.Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

도 1은 본 발명에 의한 일실시예에 따른 반도체 메모리 장치를 나타낸 회로도이다.1 is a circuit diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

도 1에 도시된 바와 같이, 본 실시예에 따른 반도체 메모리 장치는 외부로부터 인가되는 MRS 입력 신호(MRS IN)로부터 MRS 명령(MRS OUT)을 발생시키는 MRS 발생부(110)와; 상기 MRS 발생부(110)의 출력 신호를 피드백하여 입력받고, 상기 MRS 명령(MRS OUT)에 의해 동작 모드가 일단 설정되면, 외부로부터의 MRS 입력신호(MRS IN)의 추가적인 유입에 상관없이 상기 피드백된 출력신호에 응답하여 상기 MRS 발생부(110)의 출력을 유지시키는 MRS 레벨 유지부(130)를 포함하여 구성된다.As shown in FIG. 1, the semiconductor memory device according to the present exemplary embodiment includes an MRS generator 110 generating an MRS command MRS OUT from an MRS input signal MRS IN applied from the outside; When the output mode of the MRS generator 110 is fed back and received, and the operation mode is set by the MRS command (MRS OUT), the feedback regardless of the additional inflow of the MRS input signal MRS IN from the outside And an MRS level maintaining unit 130 for maintaining the output of the MRS generator 110 in response to the output signal.

상기 MRS 발생부(110)는 초기 파워업 신호(PWRUP)에 응답하여 소정 노드(n1)를 풀다운 구동하는 NMOS 트랜지스터(N10)와; 상기 노드(n1)의 신호를 래치시키는 래치부(115)와; 외부로부터 인가되는 상기 MRS 입력 신호(MRS IN)와 상기 래치부(115)의 출력 신호를 논리곱 연산하여 그 결과를 출력하는 논리부(120)를 포함한다.The MRS generation unit 110 includes an NMOS transistor N10 that pulls down a predetermined node n1 in response to an initial power-up signal PWRUP; A latch unit 115 for latching a signal of the node n1; And a logic unit 120 for performing an AND operation on the MRS input signal MRS IN and an output signal of the latch unit 115 and outputting the result.

MRS 레벨 유지부(130)는 상기 MRS 발생부(110)의 출력 신호를 소정 구간 지연시켜 출력하는 지연회로부(135)와; 지연 회로부(135)로부터 입력되는 신호에 따라 상기 MRS 발생부(110)의 출력신호를 제어하는 제어부(140)를 포함하여 구성된다. 상기 제어부(140)는 지연회로부(135)로부터의 신호와 MRS 인에이블신호(MRS ENABLE)를 반전버퍼링하는 인버터(IN2)와; 상기 인버터(IN2)의 출력신호에 응답하여 상기 노드(n1)를 풀업구동하는 PMOS 트랜지스터(P10)를 포함하여 구성된다.The MRS level maintaining unit 130 includes a delay circuit unit 135 for delaying and outputting the output signal of the MRS generator 110 by a predetermined period; The controller 140 may control the output signal of the MRS generator 110 according to a signal input from the delay circuit unit 135. The controller 140 includes an inverter IN2 that inverts the signal from the delay circuit unit 135 and the MRS enable signal MRS ENABLE; And a PMOS transistor P10 that pulls up the node n1 in response to an output signal of the inverter IN2.

이와 같이 구성된 본 실시예에 따른 반도체 메모리 장치의 동작을 도 1을 참조하여 구체적으로 설명한다.The operation of the semiconductor memory device according to the present embodiment configured as described above will be described in detail with reference to FIG. 1.

우선, MRS 명령에 의해 동작 모드를 설정하기 전 반도체 메모리 장치의 초기화 단계에서 파워업 신호(PURUP) 신호가 인가된다. 그러면, NMOS 트랜지스터(N10)가 턴온되어 노드(n1)는 로우(low) 레벨로 풀다운 구동된다. 그리고, 이러한 노드(n1)의 전위는 래치부(115)의 작용에 의해 소정 구간 유지되며, 래치부(115)의 출력은 하이(High) 레벨로 유지된다. First, the power-up signal PURUP signal is applied in the initialization step of the semiconductor memory device before setting the operation mode by the MRS command. Then, the NMOS transistor N10 is turned on so that the node n1 is pulled down to a low level. The potential of the node n1 is maintained for a predetermined period by the action of the latch unit 115, and the output of the latch unit 115 is maintained at a high level.

이 때, MRS 입력 신호(MRS IN)는 외부 명령의 조합으로서 로우 상태이며, 이에 따라 낸드게이트(ND10)와 인버터(IN1)으로 구성된 논리부(120)의 출력인 MRS 출력(MRS OUT)은 로우레벨이 된다. 그리고, 이러한 로우레벨의 MRS 출력(MRS OUT)은 다시 조절 가능한 지연 회로부(135)를 통해 제어부(140)으로 피드백되어 입력되고, 제어부(140)는 동작하지 않게 된다. 즉, 로우 상태의 MRS 출력(MRS OUT)가 제어부(140)에 입력되면, 상기 로우레벨의 신호는 인버터(IN2)에 의해 하이레벨로 되어 PMOS 트랜지스터(P10)를 턴-오프시킨다.At this time, the MRS input signal MRS IN is in a low state as a combination of external commands, and accordingly, the MRS output MRS OUT, which is an output of the logic unit 120 composed of the NAND gate ND10 and the inverter IN1, is low. It becomes a level. The low level MRS output MRS OUT is fed back to the controller 140 through the adjustable delay circuit 135 and the controller 140 is not operated. That is, when the low MRS output MRS OUT is input to the controller 140, the low level signal is turned high by the inverter IN2 to turn off the PMOS transistor P10.

여기서, 상기에서 본 바와 같이 래치부(115)의 출력은 하이레벨의 상태를 유지하고 있다. 따라서, 이후 외부로부터 MRS 입력 신호(MRS IN)가 입력되면 논리부(120)는 이러한 MRS 입력신호(MRS IN)와 래치부(115)의 출력신호를 논리곱 연산하여 MRS 명령(MRS OUT)을 발생시킨다. 이와 같이 하여 MRS 명령(MRS OUT)에 의해 반도체 메모리 장치의 동작 모드가 설정되게 된다.Here, as described above, the output of the latch unit 115 maintains a high level. Therefore, when the MRS input signal MRS IN is input from the outside, the logic unit 120 performs an AND operation on the MRS input signal MRS IN and the output signal of the latch unit 115 to perform an MRS command MRS OUT. Generate. In this way, the operation mode of the semiconductor memory device is set by the MRS command (MRS OUT).

한편, 상기와 같이 생성된 MRS 명령(MRS OUT)은 지연회로부(135)를 통하여 소정 구간 지연된 후 제어부(I40)에 피드백되어 입력된다. 인버터(IN2)는 이러한 하이레벨의 신호를 반전시켜 출력하고, PMOS(P10)는 인버터(IN2)의 출력신호에 응답하여 노드(n1)를 풀업 구동한다. 이에 따라, 노드(n1)는 하이레벨로 되고, 이러한 노드(n1)의 전위는 래치부(115)의 작용에 의해 유지되며, 래치부(115)의 출력은 로우 레벨로 유지된다.On the other hand, the MRS command (MRS OUT) generated as described above is delayed by a predetermined section through the delay circuit unit 135 is fed back to the control unit (I40). The inverter IN2 inverts and outputs this high level signal, and the PMOS P10 pulls up the node n1 in response to the output signal of the inverter IN2. Accordingly, the node n1 becomes high level, the potential of the node n1 is maintained by the action of the latch unit 115, and the output of the latch unit 115 is kept low level.

이에 따라, 이후 외부로부터 노이즈성의 외부명령이 MRS 입력신호(MRS IN)로서 입력되거나 혹은 임의의 MRS 입력신호(MRS IN)가 유입되는 경우에도, 반도체 칩이 다시 초기화시퀀스인 파워업(POWER UP) 동작을 수행하지 않는 한은 MRS 명령(MRS OUT)은 다시 생성되지 않게 된다. 즉, 상술한 바와 같이 지연회로부(135)를 통하여 지연 피드백된 MRS 명령(MRS OUT)에 응답한 제어부(140)의 동작에 의해 노드(n1)가 하이레벨로 천이되고 래치부(115)의 출력은 로우레벨로 유지되고 있다. 따라서, 외부로부터 노이즈성의 외부명령이 MRS 입력신호(MRS IN)로서 입력되거나 혹은 임의의 MRS 입력신호(MRS IN)가 유입된다 하더라도, 낸드게이트(ND10)의 일측 입력단이 계속 로우상태를 유지하고 있으므로, 논리부(120)의 출력인 MRS 출력(MRS OUT)은 계속 로우레벨의 상태를 유지한다. Accordingly, even when a noisy external command is input as the MRS input signal (MRS IN) or an arbitrary MRS input signal (MRS IN) is introduced from the outside, the semiconductor chip is again powered up. As long as the operation is not performed, the MRS command MRS OUT is not generated again. That is, as described above, the node n1 transitions to a high level by the operation of the control unit 140 in response to the MRS command MRS OUT fed back through the delay circuit unit 135, and the output of the latch unit 115 is output. Remains at the low level. Therefore, even if a noisy external command is input as the MRS input signal MRS IN or an arbitrary MRS input signal MRS IN is input from the outside, one input terminal of the NAND gate ND10 remains low. The MRS output MRS OUT, which is an output of the logic unit 120, continues to be at a low level.

결국, 본 실시예에 따르면, 초기화동작 이후 MRS 명령(MRS OUT)이 생성되어 반도체 메모리 장치의 동작모드가 일단 설정된 경우에는, 이후 반도체 칩이 다시 초기화시퀀스인 파워업(POWER UP) 동작을 수행하지 않는 한은 MRS 명령(MRS OUT)은 다시 생성되지 않게 된다. 이에 따라, 본 실시예에 따른 반도체 메모리 장치에서는 외부 노이즈나 오류 등에 의해 동작 모드가 재설정되는 것이 방지된다.As a result, according to the present embodiment, when the MRS command MRS OUT is generated after the initialization operation and the operation mode of the semiconductor memory device is set once, the semiconductor chip does not perform the power-up operation of the initialization sequence again. Unless the MRS command (MRS OUT) is not generated again. Accordingly, in the semiconductor memory device according to the present embodiment, the operation mode is prevented from being reset by external noise, an error, or the like.

이상 설명한 바와 같이, 본 발명에 따르면, MRS 명령에 의해 동작 모드가 설정된 후, MRS 입력으로 다른 외부 명령 또는 노이즈가 인가된다 하더라도 반도체 메모리 장치의 동작 모드가 재설정되는 등의 오동작을 방지할 수 있다.As described above, according to the present invention, even if another external command or noise is applied to the MRS input after the operation mode is set by the MRS command, a malfunction such as resetting the operation mode of the semiconductor memory device can be prevented.

Claims (7)

외부로부터 인가되는 MRS 입력 신호로부터 MRS 명령을 발생시키는 MRS 발생부와;An MRS generator for generating an MRS command from an MRS input signal applied from the outside; 상기 MRS 발생부의 출력 신호를 피드백하여 입력받고, 상기 MRS 명령에 의해 동작 모드가 일단 설정되면, 외부로부터의 MRS 입력신호의 추가적인 유입에 상관없이 상기 피드백된 출력신호에 응답하여 상기 MRS 발생부의 출력을 유지시키는 MRS 레벨 유지부를 포함하여 구성되는 반도체 메모리 장치.The MRS generator outputs the MRS generator in response to the fed back output signal, and once the operation mode is set by the MRS command, the MRS generator outputs the MRS generator in response to the feedback signal. And a MRS level holding unit for holding. 제 1 항에 있어서, The method of claim 1, 상기 MRS 발생부는The MRS generating unit 초기 파워업 신호에 응답하여 소정 노드를 풀다운 구동하는 풀다운 소자와;A pull-down element configured to pull down a predetermined node in response to an initial power-up signal; 상기 노드의 신호를 래치시키는 래치부와;A latch unit for latching a signal of the node; 외부로부터 인가되는 상기 MRS 입력 신호와 상기 래치부의 출력 신호를 논리연산하여 그 결과를 출력하는 논리부를 포함하는 반도체 메모리 장치.And a logic unit configured to logically operate the MRS input signal and an output signal of the latch unit applied from an external device, and output a result thereof. 제 2 항에 있어서, The method of claim 2, 상기 래치부는 상기 노드의 신호를 래치시킴과 동시에 반전시켜 출력하는 반 도체 메모리 장치.And the latch unit latches a signal of the node and simultaneously inverts the signal of the node and outputs the inverted signal. 제 2 항에 있어서, The method of claim 2, 상기 논리부는 논리곱 연산을 수행하는 반도체 메모리 장치.And the logic unit performs an AND operation. 제 2 항에 있어서, The method of claim 2, 상기 MRS 레벨 유지부는The MRS level maintenance unit 상기 MRS 발생부의 출력 신호를 소정 구간 지연시켜 출력하는 지연회로부와;A delay circuit unit configured to delay and output the output signal of the MRS generator by a predetermined period; 상기 지연 회로부로부터 입력되는 신호에 따라 상기 MRS 발생부의 출력신호를 제어하는 제어부를 포함하는 반도체 메모리 장치.And a controller configured to control an output signal of the MRS generator according to a signal input from the delay circuit unit. 제 5 항에 있어서, The method of claim 5, 상기 제어부는 소정 MRS 인에이블신호에 응답하여 인에이블되는 것을 특징으로 하는 반도체 메모리 장치.And the controller is enabled in response to a predetermined MRS enable signal. 제 6 항에 있어서, The method of claim 6, 상기 제어부는The control unit 상기 지연회로부로부터의 신호와 상기 MRS 인에이블신호를 버퍼링하는 버퍼와;A buffer for buffering the signal from the delay circuit unit and the MRS enable signal; 상기 버퍼의 출력신호에 응답하여 상기 노드를 풀업구동하는 풀업소자를 포함하는 반도체 메모리 장치.And a pull-up device configured to pull-up the node in response to an output signal of the buffer.
KR1020060061490A 2006-06-30 2006-06-30 Semiconductor memory circuit in which the operation mode is set up by a mrs command KR20080002593A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100891304B1 (en) * 2007-09-10 2009-04-06 주식회사 하이닉스반도체 Semiconductor memory device including test mode circuit
KR100949267B1 (en) * 2008-11-06 2010-03-25 주식회사 하이닉스반도체 Seiconductor memory device and thereof control method
US8050117B2 (en) 2008-10-02 2011-11-01 Hynix Semiconductor Inc. Command generation circuit and semiconductor memory device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100891304B1 (en) * 2007-09-10 2009-04-06 주식회사 하이닉스반도체 Semiconductor memory device including test mode circuit
US8214171B2 (en) 2007-09-10 2012-07-03 Hynix Semiconductor Inc. Semiconductor memory device including test mode circuit
US8050117B2 (en) 2008-10-02 2011-11-01 Hynix Semiconductor Inc. Command generation circuit and semiconductor memory device
US8817556B2 (en) 2008-10-02 2014-08-26 Hynix Semiconductor Inc. Command generation circuit and semiconductor memory device
KR100949267B1 (en) * 2008-11-06 2010-03-25 주식회사 하이닉스반도체 Seiconductor memory device and thereof control method

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