KR20080001529A - Method for fabricating the same of semiconductor device with dual poly gate - Google Patents

Method for fabricating the same of semiconductor device with dual poly gate Download PDF

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KR20080001529A
KR20080001529A KR1020060060008A KR20060060008A KR20080001529A KR 20080001529 A KR20080001529 A KR 20080001529A KR 1020060060008 A KR1020060060008 A KR 1020060060008A KR 20060060008 A KR20060060008 A KR 20060060008A KR 20080001529 A KR20080001529 A KR 20080001529A
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polysilicon layer
conductive polysilicon
semiconductor device
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layer
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KR1020060060008A
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Korean (ko)
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오상원
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for fabricating a semiconductor device having a dual poly gate is provided to prevent generation of a residual photoresist layer caused by an ion implantation process by forming a dual poly gate by a deposition method or a growth method. A gate insulation layer(32) is formed on a semiconductor substrate(31). A polysilicon layer of a first conductivity type is formed on the gate insulation layer. One lateral surface of the polysilicon layer of the first conductivity type is etched. A polysilicon layer of a second conductivity type is formed on the gate insulation layer opened by the etching process. The polysilicon layers of the first and second conductivity types are patterned to form a dual poly gate electrode. The polysilicon layers of the first and second conductivity types are made of polysilicons doped with different impurities, having the same width. The polysilicon layer of the first conductivity type is made of an N-type polysilicon layer(33), and the polysilicon layer of the second conductivity type is made of a P-type polysilicon layer.

Description

듀얼폴리 게이트를 갖는 반도체 소자의 제조방법{METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE WITH DUAL POLY GATE}Method for manufacturing a semiconductor device having a dual poly gate {METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE WITH DUAL POLY GATE}

도 1a 및 도 1b는 종래 기술에 따른 듀얼폴리 게이트를 갖는 반도체 소자의 제조방법을 설명하기 위한 공정 단면도,1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to the prior art;

도 2a 내지 도 2c는 도즈용량에 따른 감광막 잔류물을 나타내는 TEM사진,2A to 2C are TEM photographs showing the photoresist residue according to the dose;

도 3a 내지 도 3g는 본 발명의 바람직한 실시예에 따른 듀얼폴리 게이트를 갖는 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to a preferred embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

31 : 반도체 기판 32 : 게이트절연막31 semiconductor substrate 32 gate insulating film

33B : N형 폴리실리콘전극 34A : 하드마스크패턴33B: N-type polysilicon electrode 34A: hard mask pattern

35 : 감광막패턴 36B : P형 폴리실리콘전극35 photosensitive film pattern 36B P-type polysilicon electrode

본 발명은 반도체 제조 기술에 관한 것으로, 특히 듀얼폴리 게이트를 갖는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for manufacturing a semiconductor device having a dual poly gate.

최근에 디자인룰 감소에 따른 숏채널효과(Short channel effect) 등의 문제를 해결하기 위해 듀얼폴리게이트(Dual poly gate) 사용의 필요성이 대두되고 있다. Recently, in order to solve problems such as short channel effects due to the reduction of design rules, the necessity of using a dual poly gate has emerged.

듀얼 폴리 게이트는 N형 불순물이 도핑된 N 도우프드 폴리실리콘(N doped polysilicon)을 NMOS영역/PMOS영역의 게이트로 모두 사용하는 것이 아니라, NMOS 트랜지스터는 N형 불순물이 도핑된 N 도우프드 폴리실리콘을 게이트로 사용하고, PMOS 트랜지스터는 P형 불순물이 도핑된 P 도우프드 폴리실리콘을 게이트로 사용하는 기술이다.The dual poly gate does not use both N-doped polysilicon doped with N-type impurities as the gate of the NMOS region / PMOS region, but the NMOS transistor uses N-doped poly-silicon doped with N-type impurities. As a gate, a PMOS transistor is a technique of using P-doped polysilicon doped with P-type impurities as a gate.

도 1a 및 도 1b는 종래 기술에 따른 듀얼폴리 게이트를 갖는 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to the prior art.

도 1a에 도시된 바와 같이, NMOS영역과 PMOS영역이 정의된 반도체 기판(11) 상에 게이트절연막(12)을 형성하고, 게이트절연막(12) 상에 N형 폴리실리콘층(13)을 형성하고, N형 폴리실리콘층(13) 상에 PMOS영역의 N형 폴리실리콘층(13)을 오픈시키는 감광막패턴(14)을 형성한다.As shown in FIG. 1A, a gate insulating film 12 is formed on a semiconductor substrate 11 on which an NMOS region and a PMOS region are defined, and an N-type polysilicon layer 13 is formed on the gate insulating film 12. On the N-type polysilicon layer 13, a photosensitive film pattern 14 for opening the N-type polysilicon layer 13 of the PMOS region is formed.

이어서, 감광막패턴(14)을 이온주입 배리어로 PMOS영역의 N형 폴리실리콘층(13)에 P형 불순물을 이온주입하여 P형 폴리실리콘층(15)으로 반전시킨다.Subsequently, P-type impurities are ion-implanted into the N-type polysilicon layer 13 in the PMOS region using the photosensitive film pattern 14 as an ion implantation barrier to invert the P-type polysilicon layer 15.

도 1b에 도시된 바와 같이, 감광막패턴(14)을 스트립한다. 따라서, NMOS영역에는 N형 폴리실리콘전극(13A), PMOS영역에는 P형 폴리실리콘전극(15)이 형성된다.As shown in FIG. 1B, the photosensitive film pattern 14 is stripped. Accordingly, the N-type polysilicon electrode 13A is formed in the NMOS region, and the P-type polysilicon electrode 15 is formed in the PMOS region.

위와 같이, 종래 기술은 N형 폴리실리콘층(13)을 P형 폴리실리콘층(13A)으로 반전(Convert)시키기 위해, 이전보다 매우 강력한 이온주입 도즈(Implant Dose)용량을 사용한다. 예컨대, 도즈를 이전 이온주입 도즈의 단위 E15/cm2 에서 E16/cm2로 10배이상 증가시켜 실시한다.As described above, the prior art uses a much stronger ion implant dose than before to convert the N-type polysilicon layer 13 to the P-type polysilicon layer 13A. For example, the dose is increased by 10 times or more from the unit E15 / cm 2 of the previous ion implantation dose to E16 / cm 2 .

그러나, 종래 기술은 증가된 이온주입 도즈로 인해 이온주입배리어로 사용된 감광막패턴(14)이 경화되는 문제점이 있다. 또한, 경화된 감광막패턴(14)은 후속 스트립공정에서 제거되지 않고 잔류(14A)한다. 이러한 잔류물(14A)없이 스트립하기 위해서는 N2H2 또는 Hot 탈이온수와 O3 전처리를 실시한 후 스트립을 실시하는 추가공정을 실시해야한다. 특히, 이온주입 도즈가 현재보다 더 증가되는 경우 전처리를 실시해도 잔류물(14A)이 존재하는 문제점이 있다.However, the prior art has a problem in that the photosensitive film pattern 14 used as the ion implantation barrier is cured due to the increased ion implantation dose. In addition, the cured photoresist pattern 14 remains 14A without being removed in a subsequent stripping process. In order to strip without these residues 14A, an additional step of stripping after N 2 H 2 or Hot deionized water and O 3 pretreatment should be performed. In particular, when the ion implantation dose is increased more than present, there is a problem that the residue 14A exists even if pretreatment is performed.

또한, 현재 이온주입 공정시간을 단축시키기 위해 플라즈마 도핑(Plasma Doping:PLAD)을 도입하고 있는데, 플라즈마 도핑의 경우 기존의 이온주입공정보다 원치않는 불순물들이 감광막패턴에 더욱 주입되는 문제점이 있다.In addition, plasma doping (PLAD) is introduced to shorten the ion implantation process time. In the case of plasma doping, unwanted impurities are more injected into the photoresist pattern than the conventional ion implantation process.

도 2a 내지 도 2c는 도즈용량에 따른 감광막 잔류물을 나타내는 TEM사진이다.2A to 2C are TEM photographs showing the photoresist residue according to the dose.

도 2a를 참조하면, 감광막패턴을 형성한 후 이온주입을 실시한 후를 살펴볼 수 있다. 이때, 도 2a에서 낮은 도즈로 이온주입을 실시했을 경우, 도 2b와 같이 감광막패턴이 잔류하지 않고 모두 제거된 것을 알 수 있다. 또한, 도 2a에서 높은 도즈로 이온주입을 실시했을 경우, 도 2c와 같이 감광막패턴의 경화로 인해 제거되 지 않아서 잔류물(100)이 존재하는 것을 알 수 있다.Referring to FIG. 2A, after the photoresist pattern is formed, ion implantation may be performed. In this case, when the ion implantation is performed at a low dose in FIG. 2A, it can be seen that the photoresist pattern is not removed as shown in FIG. 2B. In addition, when ion implantation is performed at a high dose in FIG. 2A, it may be seen that the residue 100 is not removed due to curing of the photosensitive film pattern as shown in FIG. 2C.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 듀얼폴리 게이트를 형성하기 위한 이온주입 공정시 감광막패턴의 경화로 발생하는 잔류물을 방지하기 위한 듀얼폴리 게이트를 갖는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, the manufacturing of a semiconductor device having a dual poly gate to prevent residues caused by curing of the photosensitive film pattern during the ion implantation process for forming a dual poly gate The purpose is to provide a method.

본 발명에 의한 듀얼폴리 게이트를 갖는 반도체 소자의 제조방법은 반도체 기판 상부에 게이트절연막을 형성하는 단계, 상기 게이트절연막 상에 제1도전형폴리실리콘층을 형성하는 단계, 상기 제1도전형폴리실리콘층의 한측면을 식각하는 단계, 상기 식각에 의해 오픈된 게이트절연막 상에 제2도전형폴리실리콘층을 형성하는 단계, 상기 제1 및 제2도전형폴리실리콘층을 각각 패터닝하여 듀얼폴리게이트전극을 형성하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a semiconductor device having a dual poly gate according to the present invention may include forming a gate insulating film on a semiconductor substrate, forming a first conductive polysilicon layer on the gate insulating film, and forming the first conductive polysilicon. Etching one side of the layer; forming a second conductive polysilicon layer on the gate insulating film opened by the etching; and patterning the first and second conductive polysilicon layers, respectively, to form a dual poly gate electrode. It characterized in that it comprises a step of forming.

또한, 상기 제1 및 제2도전형폴리실리콘층은 서로 다른 불순물이 도핑된 폴리실리콘으로 형성하고, 같은 폭을 갖도록 형성한다. 그리고, 제1도전형폴리실리콘층은 N형 폴리실리콘층으로, 상기 제2도전형폴리실리콘층은 P형 폴리실리콘층으로 형성하거나, 제1도전형폴리실리콘층은 P형 폴리실리콘층으로, 상기 제2도전형폴리실리콘층은 N형 폴리실리콘층으로 형성한다.In addition, the first and second conductive polysilicon layers are formed of polysilicon doped with different impurities and are formed to have the same width. The first conductive polysilicon layer is formed of an N-type polysilicon layer, and the second conductive polysilicon layer is formed of a P-type polysilicon layer, or the first conductive polysilicon layer is a P-type polysilicon layer. The second conductive polysilicon layer is formed of an N-type polysilicon layer.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 3a 내지 도 3g는 본 발명의 바람직한 실시예에 따른 듀얼폴리 게이트를 갖는 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to a preferred embodiment of the present invention.

도 3a에 도시된 바와 같이, NMOS영역과 PMOS영역이 정의된 반도체 기판(31) 상에 게이트절연막(32)을 형성한다. 여기서, 반도체 기판(31)은 소자분리막과 웰(Well)을 포함하고, 게이트절연막(32)은 열산화 또는 증착방법을 형성한 산화막으로 형성한다.As shown in FIG. 3A, a gate insulating film 32 is formed on a semiconductor substrate 31 in which an NMOS region and a PMOS region are defined. Here, the semiconductor substrate 31 includes an isolation layer and a well, and the gate insulating layer 32 is formed of an oxide film formed by a thermal oxidation or deposition method.

이어서, 게이트절연막(32) 상에 N형 폴리실리콘층(33)을 형성한다. 여기서, N형 폴리실리콘층(33)은 이온주입 공정을 실시하지 않고 N형 불순물이 도핑된 폴리실리콘으로 형성한다. 따라서, 이온주입 공정후 도펀트의 활성화를 위한 어닐공정을 실시하지 않기 때문에, 열처리로 인해 비정질실리콘에서 결정질실리콘으로 변경되는 것을 방지할 수 있다. 이로 인해, 후속 게이트패턴 형성을 위한 식각공정에서 실리콘의 결정화로 식각이 잘되지 않는 어려움을 방지할 수 있다.Subsequently, an N-type polysilicon layer 33 is formed on the gate insulating film 32. Here, the N-type polysilicon layer 33 is formed of polysilicon doped with N-type impurities without performing an ion implantation process. Therefore, since the annealing process for activating the dopant is not performed after the ion implantation process, it is possible to prevent the change from amorphous silicon to crystalline silicon due to the heat treatment. As a result, it is possible to prevent difficulty in etching due to crystallization of silicon in an etching process for forming a subsequent gate pattern.

도 3b에 도시된 바와 같이, N형 폴리실리콘층(33) 상에 하드마스크층(34)을 형성한다. 여기서, 하드마스크패턴(34)은 N형 폴리실리콘층(33)을 식각하기 위한 식각배리어 및 후속 폴리실리콘전극을 형성하기 위한 평탄화공정에서 CMP(Chemical Mechanical Polishing)배리어로 사용하기 위한 것으로, 질화막, 산화막, 유전막 또 는 메탈계물질의 그룹 중에서 선택된 어느 하나로 형성할 수 있다. 특히, 메탈계물질은 텅스텐(Ｗ), 알루미늄(Al), 티타늄(Ti) 및 티타늄질화막(TiN)의 그룹 중에서 선택된 어느 하나를 사용할 수 있다. As shown in FIG. 3B, a hard mask layer 34 is formed on the N-type polysilicon layer 33. Here, the hard mask pattern 34 may be used as a chemical mechanical polishing (CMP) barrier in a planarization process for forming an etching barrier for etching the N-type polysilicon layer 33 and a subsequent polysilicon electrode. It may be formed of any one selected from the group consisting of an oxide film, a dielectric film or a metal-based material. In particular, the metal-based material may be any one selected from the group consisting of tungsten, aluminum (Al), titanium (Ti), and titanium nitride film (TiN).

또한, 상기한 하드마스크층(34) 외에 폴리실리콘(예컨대, 언도프드 폴리실리콘, N형 또는 P형 불순물이 도핑된 폴리실리콘)을 추가적으로 형성하여 하드마스크 및 CMP배리어로 사용할 수 있다.Further, in addition to the hard mask layer 34 described above, polysilicon (eg, undoped polysilicon, polysilicon doped with N-type or P-type impurities) may be additionally formed to be used as a hard mask and a CMP barrier.

혹은, 하드마스크층(34)을 형성하지 않고, 감광막패턴(35)만 단독으로 형성할 수 있다.Alternatively, only the photoresist pattern 35 may be formed alone without forming the hard mask layer 34.

이어서, 하드마스크층(34) 상에 감광막패턴(35)을 형성한다. 여기서, 감광막패턴(35)은 하드마스크층(34) 상에 감광막을 코팅한 후 노광 및 현상으로 후속 P형 폴리실리콘층이 형성될 영역이 오픈되도록 패터닝한다.Subsequently, the photoresist pattern 35 is formed on the hard mask layer 34. Here, the photoresist pattern 35 is coated on the hard mask layer 34 and then patterned so as to open a region where a subsequent P-type polysilicon layer is to be formed by exposure and development.

도 3c에 도시된 바와 같이, 감광막패턴(35)을 식각마스크로 상기 하드마스크층(34)을 식각하여 하드마스크패턴(34A)을 형성한다. 여기서, 하드마스크패텅(34A)은 PMOS영역의 N형 폴리실리콘층(33)을 오픈시킨다.As shown in FIG. 3C, the hard mask layer 34 is etched using the photoresist pattern 35 as an etch mask to form a hard mask pattern 34A. Here, the hard mask patch 34A opens the N-type polysilicon layer 33 in the PMOS region.

도 3d에 도시된 바와 같이, 감광막패턴(35) 및 하드마스크패턴(34A)을 식각마스크로 PMOS영역의 N형 폴리실리콘층(33)을 식각한다. As shown in FIG. 3D, the N-type polysilicon layer 33 of the PMOS region is etched using the photoresist pattern 35 and the hard mask pattern 34A as an etch mask.

따라서, NMOS영역에만 N형 폴리실리콘층(33A)이 잔류하고, PMOS영역은 N형 폴리실리콘층(33A)이 식각되어 게이트절연막(32)이 오픈된다.Accordingly, the N-type polysilicon layer 33A remains only in the NMOS region, and the N-type polysilicon layer 33A is etched in the PMOS region to open the gate insulating film 32.

도 3e에 도시된 바와 같이, 감광막패턴(35)을 제거한다. 여기서, 감광막패턴(35)은 산소스트립공정으로 제거할 수 있다.As shown in FIG. 3E, the photosensitive film pattern 35 is removed. Here, the photoresist pattern 35 may be removed by an oxygen strip process.

이어서, PMOS영역에 P형 폴리실리콘층(36)을 형성한다. 여기서, P형 폴리실리콘층(36)은 적어도 NMOS영역의 N형 폴리실리콘층(33A)과 동일한 높이를 갖도록 형성한다. 또한, P형 폴리실리콘층(36)은 N형 폴리실리콘층(33)과 마찬가지로 이온주입 공정을 실시하지 않고 P형 불순물이 도핑된 폴리실리콘으로 형성한다. Subsequently, a P-type polysilicon layer 36 is formed in the PMOS region. Here, the P-type polysilicon layer 36 is formed to have at least the same height as the N-type polysilicon layer 33A in the NMOS region. In addition, like the N-type polysilicon layer 33, the P-type polysilicon layer 36 is formed of polysilicon doped with P-type impurities without performing an ion implantation process.

따라서, 이온주입 공정후 도펀트의 활성화를 위한 어닐공정을 실시하지 않기 때문에 열처리로 인해 비정질실리콘에서 결정질실리콘으로 변경되는 것을 방지한다. 이로 인해, 후속 게이트패턴 형성을 위한 식각공정에서 실리콘의 결정화로 식각이 잘되지 않는 어려움을 방지할 수 있다. 또한, 이온주입 도즈로 인해 감광막이 경화되어 스트립되지 않고 잔류하는 것을 방지할 수 있다.Therefore, since the annealing process for activating the dopant is not performed after the ion implantation process, the change from amorphous silicon to crystalline silicon due to heat treatment is prevented. As a result, it is possible to prevent difficulty in etching due to crystallization of silicon in an etching process for forming a subsequent gate pattern. In addition, the ion implantation dose can prevent the photosensitive film from curing and remaining without being stripped.

도 3f에 도시된 바와 같이, N형 및 P형 폴리실리콘층(33A, 36)에 평탄화 공정을 실시한다. 여기서, 평탄화 공정은 N형 폴리실리콘층(33A)을 타겟으로 실시한다. 즉, 폴리실리콘과 물질이 서로 다른 하드마스크패턴(34A)과 N형 폴리실리콘층(33A)의 경계를 타겟으로 실시한다. 따라서, NMOS영역의 N형 폴리실리콘층(33A) 상부에 하드마스크패턴(34A) 및 불필요한 P형 폴리실리콘층(36)이 식각되어, N형 폴리실리콘층(33A)과 동일한 높이를 갖는 P형 폴리실리콘층(36A)이 잔류한다.As shown in FIG. 3F, planarization processes are performed on the N-type and P-type polysilicon layers 33A and 36. Here, the planarization process is performed using the N-type polysilicon layer 33A as a target. That is, the target is formed by the boundary between the hard mask pattern 34A and the N-type polysilicon layer 33A having different polysilicon and materials. Accordingly, the hard mask pattern 34A and the unnecessary P-type polysilicon layer 36 are etched on the N-type polysilicon layer 33A in the NMOS region, so that the P-type has the same height as the N-type polysilicon layer 33A. The polysilicon layer 36A remains.

또한, 평탄화 공정은 화학적기계적연마(Chemical Mechanical Polishing:CMP) 또는 건식식각으로 실시할 수 있다. 그리고, 하드마스크패턴(34)을 사용하지 않은 경우는 각각의 폴리실리콘층(33A, 36A)이 분리되는 높이를 타겟으로 실시한다.In addition, the planarization process may be carried out by chemical mechanical polishing (CMP) or dry etching. In the case where the hard mask pattern 34 is not used, the height at which the respective polysilicon layers 33A and 36A are separated is performed as a target.

도 3g에 도시된 바와 같이, N형 및 P형 폴리실리콘층(33A, 36A)를 패터닝하여 NMOS영역에는 N형 폴리실리콘전극(33B), PMOS영역에는 P형 폴리실리콘전극(36B) 을 형성한다.As shown in FIG. 3G, the N-type and P-type polysilicon layers 33A and 36A are patterned to form an N-type polysilicon electrode 33B in the NMOS region and a P-type polysilicon electrode 36B in the PMOS region. .

상기한 본 발명은, 감광막을 이온주입 배리어로 N형 폴리실리콘층에 P형 불순물을 도핑하여 듀얼폴리 게이트를 형성하는 대신 N형 또는 P형 불순물이 도핑된 폴리실리콘을 직접 형성한다. 즉, 높은 도즈의 이온주입이 생략되므로 감광막 경화가 발생하지 않아서 후속 스트립시 잔류물 없이 감광막을 제거할 수 있다. 또한, 이온주입 후 어닐공정으로 인한 폴리실리콘의 경화도 방지할 수 있다.In the present invention described above, instead of forming a dual poly gate by doping a P-type impurity to an N-type polysilicon layer using a photosensitive film as an ion implantation barrier, polysilicon doped with N-type or P-type impurities is directly formed. That is, since high dose ion implantation is omitted, the photoresist hardening does not occur so that the photoresist may be removed without residue during subsequent stripping. In addition, the curing of the polysilicon due to the annealing process after the ion implantation can be prevented.

본 발명의 바람직한 실시예는 N형 폴리실리콘층을 먼저 형성한 후 P형 폴리실리콘층을 형성하여 듀얼폴리 게이트를 갖는 반도체 소자를 형성하였으나, N형 폴리실리콘을 형성하기 전에 P형 폴리실리콘층을 먼저 형성한 후 N형 폴리실리콘층을 형성할 수도 있다.In the preferred embodiment of the present invention, an N-type polysilicon layer is first formed, and then a P-type polysilicon layer is formed to form a semiconductor device having a dual poly gate, but before the N-type polysilicon is formed, the P-type polysilicon layer is formed. After forming first, an N-type polysilicon layer may be formed.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 이온주입이 아닌 증착 또는 성장방법으로 듀얼폴리게이트를 형성함으로써, 이온주입 공정으로 인한 감광막잔류물을 방지하고, 이온주입 후 어닐공정을 통한 폴리실리콘 결정화를 방지하여 소자의 신뢰성 및 수율 향상의 효 과가 있다.The present invention described above forms dual polygates by deposition or growth method rather than ion implantation, thereby preventing photoresist residues caused by ion implantation process, and preventing polysilicon crystallization through annealing process after ion implantation. There is an effect of yield improvement.

Claims (9)

반도체 기판 상부에 게이트절연막을 형성하는 단계;Forming a gate insulating film on the semiconductor substrate; 상기 게이트절연막 상에 제1도전형폴리실리콘층을 형성하는 단계;Forming a first conductive polysilicon layer on the gate insulating film; 상기 제1도전형폴리실리콘층의 한측면을 식각하는 단계;Etching one side of the first conductive polysilicon layer; 상기 식각에 의해 오픈된 게이트절연막 상에 제2도전형폴리실리콘층을 형성하는 단계; 및Forming a second conductive polysilicon layer on the gate insulating film opened by the etching; And 상기 제1 및 제2도전형폴리실리콘층을 각각 패터닝하여 듀얼폴리게이트전극을 형성하는 단계Patterning the first and second conductive polysilicon layers, respectively, to form a dual polygate electrode; 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 제1 및 제2도전형폴리실리콘층은 서로 다른 불순물이 도핑된 폴리실리콘으로 형성하고, 같은 폭을 갖는 것을 특징으로 하는 반도체 소자의 제조방법.The first and second conductive polysilicon layers are formed of polysilicon doped with different impurities, and have a same width. 제2항에 있어서,The method of claim 2, 상기 제1도전형폴리실리콘층은 N형 폴리실리콘층으로, 상기 제2도전형폴리실리콘층은 P형 폴리실리콘층으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.Wherein the first conductive polysilicon layer is formed of an N-type polysilicon layer, and the second conductive polysilicon layer is formed of a P-type polysilicon layer. 제2항에 있어서,The method of claim 2, 상기 제1도전형폴리실리콘층은 P형 폴리실리콘층으로, 상기 제2도전형폴리실리콘층은 N형 폴리실리콘층으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.Wherein the first conductive polysilicon layer is formed of a P-type polysilicon layer, and the second conductive polysilicon layer is formed of an N-type polysilicon layer. 제1항에 있어서,The method of claim 1, 상기 제1도전형폴리실리콘층의 한측면을 식각하는 단계는,Etching one side of the first conductive polysilicon layer, 상기 제1도전형폴리실리콘층 상에 하드마스크패턴을 형성하는 단계; 및Forming a hard mask pattern on the first conductive polysilicon layer; And 상기 하드마스크패턴을 식각마스크로 상기 제1도전형폴리실리콘층의 한측면을 식각하는 단계Etching one side of the first conductive polysilicon layer using the hard mask pattern as an etching mask 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제5항에 있어서,The method of claim 5, 상기 하드마스크패턴은,The hard mask pattern, 질화막, 산화막, 유전막 및 메탈계물질의 그룹 중에서 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.A method for manufacturing a semiconductor device, characterized in that formed by any one selected from the group consisting of a nitride film, an oxide film, a dielectric film and a metal-based material. 제6항에 있어서,The method of claim 6, 상기 메탈계물질은 텅스텐(Ｗ), 알루미늄(Al), 티타늄(Ti) 및 티타늄질화막(TiN)의 그룹 중에서 선택된 어느 하나를 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The metal-based material manufacturing method of the semiconductor device, characterized in that using any one selected from the group of tungsten (Al), aluminum (Al), titanium (Ti) and titanium nitride film (TiN). 제1항 내지 제7항에 중 어느 한 항에 있어서,The method according to any one of claims 1 to 7, 상기 제2도전형폴리실리콘층을 형성하는 단계는,Forming the second conductive polysilicon layer, 상기 오픈된 게이트절연막 및 하드마스크패턴 상에 제2도전형폴리실리콘층을 형성하는 단계; 및Forming a second conductive polysilicon layer on the open gate insulating layer and the hard mask pattern; And 상기 제1도전형폴리실리콘층의 표면을 타겟으로 평탄화하는 단계Planarizing the surface of the first conductive polysilicon layer to a target 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제8항에 있어서,The method of claim 8, 상기 평탄화는 화학적기계적연마(Chemical Mechanical Polishing:CMP) 또는 건식식각으로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The planarization method of manufacturing a semiconductor device, characterized in that performed by chemical mechanical polishing (CMP) or dry etching.
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