KR20080001403A - Shift register and liquid crystal display device using the same - Google Patents

Abstract

A shift register and an LCD(Liquid Crystal Display) device are provided to prevent ripples by using two output terminals, which have different loads from each other while two output signals are in low voltages, of the shift register. A shift register includes first and second stages(S1,S2), and a ripple down controller(100). The first stage charges a first output terminal in response to the voltage of a first node and discharges the first output terminal in response to the voltage of a second node. The second stage is operated according to the voltage of the first output terminal, charges a second output terminal in response to the voltage of a third node, and discharge the second output terminal in response to the voltage of a fourth node. The ripple down controller connects the first and second output terminals in response to the voltage of the fourth node.

Description

SHIFT REGISTER AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME}

1 is a view showing a conventional liquid crystal display device.

FIG. 2 is a diagram showing the configuration of the gate driving circuit shown in FIG. 1; FIG.

3 is a detailed circuit diagram of the first stage shown in FIG.

4 is a drive waveform diagram of the first stage shown in FIG.

5 is a diagram showing an output waveform of a conventional shift register.

6 is a diagram illustrating a shift register according to a first embodiment of the present invention.

Fig. 7 is a diagram showing examples of first and second stage circuit configurations among the shift registers according to the first embodiment of the present invention.

FIG. 8 is a drive waveform diagram of the first and second stages shown in FIG. 7; FIG.

9 is a diagram illustrating a shift register according to a second embodiment of the present invention.

FIG. 10 is a diagram showing an example of first and second stage circuit configurations among the shift registers according to the second embodiment of the present invention; FIG.

11A and 11B are drive waveform diagrams of the first and second stages shown in FIG.

12 is a view showing an output waveform of a shift register according to the present invention.

<Brief description of symbols for the main parts of the drawings>

11 data driving circuit 12 gate driving circuit

13: liquid crystal display panel 15: shift register

21: output buffer 22: control unit

100, 200: ripple down control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register and a liquid crystal display using the same, and more particularly, to a shift register capable of reducing ripple generated in an output signal and a liquid crystal display using the same.

Liquid crystal displays are widely used in display devices of office equipment, monitors of computers, and even large-screen televisions with the recent development of process and driving technologies. Such a liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

Referring to FIG. 1, in the conventional LCD, m × n liquid crystal cells Clc are arranged in a matrix type, m data lines D1 to Dm and n gate lines G1 to Gn. Intersect with the liquid crystal display panel 13 to which the thin film transistor TFT is connected, and the data driver circuit 11 for supplying data to the data lines D1 to Dm of the liquid crystal display panel 13. And a gate driving circuit 12 supplying a scan pulse to the gate lines G1 to Gn.

The liquid crystal display panel 13 is formed by bonding a thin film transistor substrate on which a thin film transistor array is formed and a color filter substrate on which a color filter array is formed, with the liquid crystal layer interposed therebetween. The data lines D1 to Dm and the gate lines G1 to Gn formed on the thin film transistor substrate of the liquid crystal display panel 13 are perpendicular to each other. The thin film transistor TFT connected to the intersection of the data lines D1 to Dm and the gate lines G1 to Gn may connect the data lines D1 to Dn in response to a scan pulse of the gate lines G1 to Gn. The supplied data voltage is supplied to the pixel electrode of the liquid crystal cell Clc. A black matrix, a color filter, a common electrode, and the like are formed on the color filter substrate. Accordingly, in the liquid crystal cell Clc, the liquid crystal having dielectric anisotropy is rotated to adjust the light transmittance by a potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode. On the thin film transistor substrate and the color filter substrate of the liquid crystal display panel 13, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment layer for determining the pretilt angle of the liquid crystal is further formed on the inner side of the liquid crystal layer. In addition, a storage capacitor Cst is further formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode and the front gate line, or is formed between the pixel electrode and a common line (not shown) to keep the data voltage charged in the liquid crystal cell Clc constant.

The data driving circuit 11 converts the input digital video data into an analog data voltage using a gamma voltage and supplies the analog data voltage to the data lines D1 to Dm.

The gate driving circuit 12 sequentially supplies scan pulses to the gate lines G1 to Gn to select a horizontal line of the liquid crystal cell Clc to which data is to be supplied.

Specifically, as shown in FIG. 2, the gate driving circuit 12 is first to first connected to the start pulse Vst input line in order to sequentially supply scan pulses to the gate lines G1 to Gn. a shift register 15 having n stages S1 to Sn. The clock signals CLKs are commonly supplied to the first to nth stages S1 to Sn shown in FIG. 2 together with the high potential driving voltage Vdd and the low potential driving voltage Vss, and the start pulse Vst is provided. ) Or the output signal of the previous stage is supplied. The first stage S1 outputs a scan pulse to the first gate line G1 in response to the start pulse Vst and the clock signal CLK. The second to nth stages S2 to Sn sequentially output scan pulses to the second to nth gate lines G2 to Gn in response to the output signal and the clock signals CLKs of the previous stage. do. In other words, the first to nth stages S1 to Sn have the same circuit configuration, and at least two clock signals having different phases are supplied to the clock signals CLKs.

FIG. 3 is a diagram illustrating an example of a first stage circuit configuration among the shift registers shown in FIG. 2.

Referring to FIG. 3, the first stage has a low potential under the control of the pull-up transistor T6 and the QB node which output the first clock signal CLK1 to the first gate line G1 under the control of the Q node. An output buffer 21 composed of a pull-down transistor T7 for outputting a driving voltage Vss to the first gate line G1, and first to fifth a transistors T1 to T5a for controlling the Q node and the QB node. It is provided with a control unit 22 composed of a). The first stage is supplied with the high potential driving voltage Vdd, the low potential driving voltage Vss, and the start pulse Vst, and the first and second clock signals CLK1 having different phases as shown in FIG. , CLK2) is supplied. Hereinafter, an operation process of the first stage will be described in detail with reference to the driving waveform shown in FIG. 4.

Referring to FIG. 4, in the period A, the first transistor T1 is turned on by the high voltage of the start pulse Vst so that the high voltage is pre-charged to the Q node. The pull-up transistor T6 is turned on by the high voltage pre-charged to the Q node, and the low voltage of the first clock signal CLK1 is supplied to the first gate line G1 as the output signal Vg_out1. . At this time, the QB node is in a low voltage state by the fifth transistor T5 turned on according to the high voltage of the start pulse Vst and the fifth a transistor T5a turned on according to the high voltage of the Q node. And the pull-down transistors T3 and T7 are turned off.

In period B, the first node T1 is turned off by the low voltage of the start pulse Vst, so the Q node is floated to a high voltage state, and the pull-up transistor T6 remains turned on. . At this time, due to the high voltage of the first clock signal CLK1, the Q node is bootstrapping due to the parasitic capacitance formed by overlapping the gate electrode and the drain electrode of the pull-up transistor T6, and thus, the A period. It is charged to a higher voltage. Accordingly, the pull-up transistor T6 is reliably turned on so that the high voltage of the first clock signal CLK1 is quickly supplied to the first gate line G1 as the output signal Vg_out1. Meanwhile, the QB node discharged through the 5a transistor T5a turned on by the Q node maintains a low voltage state.

In the C period, the third transistor T3a is turned on by the high voltage of the next second stage gate output signal Vg_out2 and the fourth transistor T4 is turned on by the high voltage of the second clock signal CLK2. The high potential driving voltage Vdd is supplied to the QB node to turn on the high voltage state and turn on the third and pull-down transistors T3 and T7. The Q node is quickly discharged by the turned-on third and third a transistors, and a low voltage is supplied to the first gate line G1 as the output signal Vg_out1 by the turned-on pull-down transistor T7.

In the D period, the QB node floated to the high voltage state in the C period maintains the floating state to turn on the third and pull-down transistors T3 and T7. As a result, the Q node is discharged to maintain the low voltage state, and the low voltage is supplied to the first gate line G1 as the output signal Vg_out1. The low voltage output signal Vg_out1 maintains the low voltage state of the D period until the start pulse Vst is supplied in the next frame.

In the case where the gate driving circuit having such a structure is to be incorporated in the liquid crystal display panel, the size of the output buffer of each stage, that is, the pull-up and pull-down transistors should be very large in order to reduce the deterioration of the characteristics of the output signal. By design, the output buffer should have a channel width of more than a few thousand micrometers, and transistors with a channel width of more than 20,000 micrometers may be used for gate driving circuits of liquid crystal display panels of 10 "or more medium-large size. In particular, pull-down transistors As shown in FIG. 4, since it is necessary to turn off only for two horizontal periods in one frame and to turn on for the rest of the period, the deterioration speed is increased and the life of the gate driving circuit is shortened. To do this, the area occupied by the built-in shift resistor must be large, but due to product specifications, there is a limit to increasing the circuit area within the non-display area, thereby reducing the degradation rate while reducing the size of the pull-down transistor. Various technologies have been developed, such as down transistors, but high voltage tie Despite the fact that the output signal must maintain a low voltage except that, as the size of the pull-down transistor that maintains the low voltage of the output signal is reduced, the low voltage state of the output signal is not properly maintained and the ripple ( In addition, as the size of the pull-down transistor is reduced, the capacitance value connected to the output terminal is reduced, resulting in a higher ripple height.

This ripple is synchronized with the high voltage timing of the clock signal indicating the high voltage timing of each stage output signal, for example, the first clock signal CLK1 shown in FIGS. 3 and 4, as shown in FIG. Occurs.

Accordingly, an object of the present invention is to provide a shift register and a liquid crystal display device using the same which can reduce ripple generated in an output signal.

In order to achieve the above object, a shift register according to an embodiment of the present invention is configured to charge a first output terminal in response to a voltage of a first node, and to discharge the first output terminal in response to a voltage of a second node. 1 stage; A second stage for driving according to the voltage of the first output terminal and charging the second output terminal in response to the voltage of the third node and discharging the second output terminal in response to the voltage of the fourth node; And a ripple down controller connecting the first output terminal and the second output terminal in response to the voltage of the fourth node.

The output signal of the first output terminal and the output signal of the second output terminal are synchronized to a low voltage when the fourth node is at a high voltage.

The ripple down controller includes a ripple down transistor having a gate terminal connected to the fourth node and a source and drain terminal connected to the first and second output terminals, respectively.

A shift register according to another embodiment of the present invention may include a first stage that charges a first output terminal in response to a voltage of a first node and discharges the first output terminal in response to voltages of a second and third node; A second stage driving according to the voltage of the first output terminal and charging the second output terminal in response to the voltage of the fourth node and discharging the second output terminal in response to the voltages of the fifth and sixth nodes; And a ripple down controller connecting the first output terminal and the second output terminal in response to the voltage of the fourth node.

The second and fifth nodes discharge the first and fourth nodes during an odd frame period, and the third and sixth nodes discharge the first and fourth nodes during an even frame period.

The output signal of the first output terminal and the output signal of the second output terminal are synchronized to a low voltage when the fifth and sixth nodes are high voltage.

The ripple down controller may include: a first ripple down transistor having a gate terminal connected to the fifth node and a source and drain terminal connected to the first and second output terminals, respectively; And a second ripple down transistor having a gate terminal connected to the sixth node and a source and drain terminal connected to the first and second output terminals, respectively.

According to an exemplary embodiment of the present invention, a liquid crystal display includes: a liquid crystal display panel in which a plurality of gate lines and a plurality of data lines intersect and a plurality of liquid crystal cells are disposed; A first stage that charges a first output terminal in response to a voltage of a first node, discharges the first output terminal in response to a voltage of a second node, and drives according to a voltage of the first output terminal A second stage that charges a second output terminal in response to a voltage of the second output terminal, and discharges the second output terminal in response to a voltage of a fourth node; and the first output terminal and the response in response to a voltage of the fourth node. A gate driving circuit sequentially supplying scan pulses to the gate lines, including a shift register having a ripple down control unit connecting a second output terminal; And a data driver circuit for supplying data voltages to the data lines.

According to another exemplary embodiment of the present invention, a liquid crystal display includes: a liquid crystal display panel in which a plurality of gate lines and a plurality of data lines intersect and a plurality of liquid crystal cells are disposed;

Charging a first output terminal in response to a voltage of a first node, driving a first stage to discharge the first output terminal in response to voltages of a second node and a third node, and driving according to a voltage of the first output terminal A second stage for charging the second output terminal in response to the voltage of the fourth node, discharging the second output terminal in response to the voltages of the fifth and sixth nodes, and in response to the voltage of the fourth node; A gate driving circuit sequentially supplying scan pulses to the gate lines, including a shift register having a ripple down control unit connecting a first output terminal to the second output terminal; And a data driver circuit for supplying data voltages to the data lines.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 6 to 12.

6 is a diagram illustrating a shift register according to a first embodiment of the present invention.

Referring to FIG. 6, the shift register according to the first embodiment of the present invention may include first to second slaves connected to the start pulse Vst input line to sequentially supply scan pulses to the gate lines G1 to Gn. Nth stages S1 to Sn. Each of these stages S1 to Sn is connected to an output terminal and includes an output buffer for supplying an output signal and a controller for controlling the output buffer.

The control unit is an S terminal receiving the start pulse Vst or the output signal of the previous stage stage to start driving the stage, an R terminal receiving the output signal of the next stage stage as a reset signal to reset the stage output signal, a full- A Q node connected to the gate terminal of the up transistor Fu to control the pull-up transistor Fu, and a QB node connected to the gate terminal of the pull-down transistor Fd to control the pull-down transistor Fd. It includes.

The output buffer outputs a pull-up transistor Fu that outputs one of the clock signals CLK1 to CLK4 to the output terminal under control of the control unit Q node, and a low potential driving voltage Vss under control of the control unit QB node. And a pull-down transistor Fd output to the terminal.

The shift register according to the first embodiment of the present invention further includes a ripple down control unit 100 for synchronizing output terminals of two stages. The ripple down control unit 100 includes at least one ripple down transistor RDT. The ripple down transistor RDT has a source and a drain terminal connected to output stages of two stages, and a gate terminal is connected to a QB node of a lower stage. Connected. That is, the ripple down transistor RDT is turned on under the control of the lower stage QB node to synchronize the output signals Vg_out1 and Vg_out2 of the two stages to a low voltage.

The clock signals CLK1 to CLK4 are commonly supplied to the stages of the shift register according to the first embodiment of the present invention together with the high potential driving voltage Vdd and the low potential driving voltage Vss, and the start pulse is provided. (Vst) or the output signal of the previous stage and the output signal of the next stage are supplied. In response to these signals, the first to nth stages S1 to Sn sequentially generate scan pulses and supply the scan pulses to the respective gate lines, and the output signals of the first to nth-1 stages are output signals of the next stage. Due to the reset, and not shown in the figure, a dummy stage is further provided for resetting the n-th stage. The first to nth stages and the dummy stage have the same circuit configuration, and at least one clock signal having a different phase is supplied to the clock signal.

7 is a diagram illustrating an example of a circuit configuration of the first and second stages S1 and S2 among the shift registers according to the first embodiment of the present invention.

Referring to FIG. 7, the first stage S1 outputs a first clock signal CLK1 to the first gate line G1 under the control of the first node QA. And a first output buffer comprising a first pull-down transistor T7 for outputting the low potential driving voltage Vss to the first gate line G1 under the control of the second node QBA, The first control unit includes the first to fifth a transistors T1 to T5a for controlling the QA and the second node QBA.

The second stage S2 is the second pull-up transistor T16 and the fourth node QBB which output the second clock signal CLK2 to the second gate line G2 under the control of the third node QB. A second output buffer comprising a second pull-down transistor T17 for outputting the low potential driving voltage Vss to the second gate line G2 under the control of And a second controller configured of the eleventh through fifteena transistors T11 through T15a for controlling the node QBB.

In addition, the shift register according to the first embodiment of the present invention further includes a ripple down controller 100 for synchronizing the output signals Vg_out1 and Vg_out2 of the first and second stages S1 and S2. The ripple down control unit 100 includes a ripple down transistor RDT, and source and drain terminals of the ripple down transistor RDT are connected to output terminals of the first and second stages S1 and S2, respectively, and are gate terminals. Is connected to the fourth node QBB of the second stage S2. That is, the ripple-down transistor RDT is controlled to be turned on by the fourth node QBB of the second stage S2 so that the output signals Vg_out1 and Vg_out2 of the first and second stages S1 and S2 are low. Synchronize to voltage.

The first and second stages S1 and S2 are supplied with a high potential driving voltage Vdd, a low potential driving voltage Vss and a start pulse Vst, and clocks having different phases as shown in FIG. 8. The signals are supplied. Hereinafter, an operation process of the first and second stages will be described in detail with reference to the driving waveform shown in FIG. 8.

Referring to FIG. 8, first, in a period A, the first stage S1 is turned on by the high voltage of the start pulse Vst so that the high voltage is freed to the first node QA. -It is charged. The first pull-up transistor T6 is turned on by the high voltage pre-charged to the first node QA, so that the low voltage of the first clock signal CLK1 becomes the first output signal Vg_out1. It is supplied to the gate line G1. In this case, the second node QBA is driven by the fifth transistor T5 turned on according to the high voltage of the start pulse Vst and the fifth a transistor T5a turned on according to the high voltage of the first node QA. Becomes a low voltage state and the third transistor and the first pull-down transistors T3 and T7 are turned off.

In period A, the second stage S2 turns on the third transistor and the first pull-down transistors T3 and T7 in the previous period by the fourth node QBB, which is floated to the high voltage state, remains in the floating state. -Turn on. As a result, the third node QB is discharged to maintain the low voltage state, and the low voltage is supplied to the second gate line G2 as the second output signal Vg_out2.

The ripple down transistor RDT is turned on by the fourth node QBB in a high voltage state to suppress the occurrence of ripple by synchronizing the first and second output signals Vg_out1 and Vg_out2 to a low voltage. At this time, each of the output terminals of the first and second stages S1 and S2 acts as a load to each other to reduce the height of the output signal even if ripple occurs.

In period B, since the first transistor T1 is turned off by the low voltage of the start pulse Vst, the first node QA is floated to a high voltage state, and the first full- Up transistor T6 remains turned on. At this time, due to the high voltage of the first clock signal CLK1, the first node QA is bootstrapping under the influence of parasitic capacitance formed by overlapping the gate electrode and the drain electrode of the first pull-up transistor T6. Is charged to a voltage higher than the A period. Accordingly, the first pull-up transistor T6 is surely turned on so that the high voltage of the first clock signal CLK1 is quickly supplied to the first gate line G1 as the first output signal Vg_out1. Meanwhile, the low voltage state of the second node QBA discharged through the 5a transistor T5a turned on by the first node QA is maintained.

In the period B, the second stage S2 is turned on by the high voltage of the first output signal Vg_out1 and the high voltage is pre-charged to the third node QB. The second pull-up transistor T16 is turned on by the high voltage pre-charged to the third node QB so that the low voltage of the second clock signal CLK2 is the second output signal Vg_out1. It is supplied to the gate line G2. At this time, the fourth node (T15a) is turned on according to the high voltage of the first output signal Vg_out1 and the 15th transistor T15a is turned on according to the high voltage of the third node QB. QBB is in a low voltage state, and the thirteenth transistor and the second pull-down transistors T13 and T17 are turned off.

The ripple-down transistor RDT is turned off by the fourth node QBB in the low voltage state to synchronize the first output signal Vg_out1 in the high voltage state with the second output signal Vg_out2 in the low voltage state. Block it.

In the C period, the first output signal Vg_out1 maintains the high voltage of the first clock signal CLK1 by the first pull-up transistor T6 turned on in the B period, and then becomes the C period. The first pull-up transistor T6 is output at a low voltage by the first clock signal CLK1 inverted to a low voltage before the state of the first pull-up transistor T6 is changed.

Since the eleventh transistor is turned off by the first output signal Vg_ou1 which is in the low voltage state as described above, the second stage S2 is floated to the high voltage state, and the second pull The up-transistor T16 remains turned on. At this time, due to the high voltage of the second clock signal CLK2, the third node QB is bootstrapping under the influence of parasitic capacitance formed by overlapping the gate electrode and the drain electrode of the second pull-up transistor T16. Is charged to a voltage higher than the B period. Accordingly, the second pull-up transistor T16 is reliably turned on so that the high voltage of the second clock signal CLK2 is quickly supplied to the second gate line G2 as the second output signal Vg_out2. Meanwhile, the fourth node QBB discharged through the fifteenth transistor T15a turned on by the third node QB maintains a low voltage state.

In the first stage S1, the third transistor T3a is turned on by the high voltage of the second output signal Vg_out2, and the fourth transistor turned on by the high voltage of the second clock signal CLK2. The high potential driving voltage Vdd is supplied through T4 to turn the second node QBA into a high voltage state and turn on the third transistor T3 and the first pull-down transistor T7. The first node QA is quickly discharged by the turned-on third and third a transistors T3 and T3a, and a low voltage is applied to the first output signal Vg_out1 by the turned-on first pull-down transistor T7. ) Is supplied to the first gate line G1.

As in the B period, the ripple-down transistor RDT is turned off by the fourth node QBB in the low voltage state, so that the first output signal Vg_out1 in the low voltage state and the second output signal in the high voltage state ( Vg_out2) is blocked from synchronizing.

In the D period, the second output signal Vg_out2 maintains the high voltage of the second clock signal CLK1 by the second pull-up transistor T16 which was turned on in the C period, and then becomes the D period during the D period. Before the state of the second pull-up transistor T16 is changed, it is output at the low voltage by the second clock signal CLK2 inverted to the low voltage. In this case, since the thirteena transistor T13a is turned on by the high voltage third output signal Vg_out3 and the third node QB is discharged, the third node QB is connected to the gate electrode. The 15a transistor T15a is turned off to block the discharge path of the fourth node QBB. As such, the high potential driving voltage Vdd is supplied to the fourth node QBB where the discharge path is cut off through the 14th T14 transistor turned on by the high voltage of the third clock signal CLK3, thereby providing the fourth node QBB. QBB enters a high voltage state and turns on the thirteenth transistor T13 and the second pull-down transistor T7. The third node QB is quickly discharged by the turned-on thirteenth and thirteena transistors T13 and T13a, and a low voltage is applied to the second output signal Vg_out2 by the turned-on second pull-down transistor T17. ) Is supplied to the second gate line G2.

The first stage S1 turns on the third and pull-down transistors T3 and T7 by maintaining the floating state of the second node QBA, which is floated to the high voltage state, in the C period. As a result, the first node QA is discharged to maintain the low voltage state, and the low voltage is supplied to the first gate line G1 as the first output signal Vg_out1. The first output signal Vg_out1 of the low voltage maintains the low voltage state of the D period until the start pulse Vst is supplied in the next frame.

The ripple down transistor RDT is turned on by the fourth node QBB in a high voltage state to suppress the occurrence of ripple by synchronizing the first and second output signals Vg_out1 and Vg_out2 to a low voltage. And output terminals of the second stages S1 and S2 act as loads to each other to reduce the height of the ripple. As described above, the ripple-down transistor RDT remains turned on except when the first and second output signals Vg_out1 and Vg_out2 are high voltage.

9 is a diagram illustrating a shift register according to a second embodiment of the present invention.

Referring to FIG. 9, the shift register according to the second exemplary embodiment of the present invention may include first to first slaves connected to the start pulse Vst input line to sequentially supply scan pulses to the gate lines G1 to Gn. Nth stages S1 to Sn. Each of these stages S1 to Sn is connected to an output terminal and includes an output buffer for supplying an output signal and a controller for controlling the output buffer.

The control unit is an S terminal receiving the start pulse Vst or the output signal of the previous stage stage to start driving the stage, an R terminal receiving the output signal of the next stage stage as a reset signal to reset the stage output signal, a full- A Q node connected to the gate terminal of the up transistor Fu to control the pull-up transistor Fu, and a gate node of the first pull-down transistor F-dO connected to the first pull-down transistor F-. a QBO node controlling dO) and a QBE node connected to the gate terminal of the second pull-down transistor F-dE to control the second pull-down transistor F-dE.

The output buffer includes a pull-up transistor Fu that outputs one of the clock signals CLK1 to CLK4 to the output terminal under control of the control unit Q node, and a low potential driving voltage Vss for each odd frame under control of the control unit QBO node. ) And a second pull-down transistor (F-dO) for outputting to the output terminal and a second pull-down transistor (Vss) for outputting the low potential driving voltage (Vss) for each even frame under the control of the controller QBE node ( F-dE).

The shift register according to the second embodiment of the present invention further includes a ripple down control unit 200 for synchronizing output terminals of two stages. The ripple down controller 200 includes at least one first ripple down transistor RDTO and at least one second ripple down transistor RDTE. In the first ripple down transistor RDTO, source and drain terminals are connected to output stages of two stages, and a gate terminal is connected to a QBO node of a lower stage. In the second ripple down transistor RDTE, source and drain terminals are connected to output stages of two stages, and a gate terminal is connected to a QBE node of a lower stage. That is, the first and second ripple down transistors RDTO and RDTE are turned on by the control of the QBO node and the QBE node of the lower stage, respectively, to synchronize the output signals Vg_out1 and Vg_out2 of the two stages to a low voltage. .

Each stage of the shift register according to the second exemplary embodiment of the present invention includes the clock signals CLK1 to CLK4 and the odd frame high potential driving voltage VddO together with the high potential driving voltage Vdd and the low potential driving voltage Vss. ), The even frame high potential drive voltage VddE is commonly supplied, and the start pulse Vst or the output signal of the previous stage and the output signal of the next stage are supplied. In response to these signals, the first to nth stages S1 to Sn sequentially generate scan pulses and supply the scan pulses to the respective gate lines, and the output signals of the first to nth-1 stages are output signals of the next stage. Due to the reset, and not shown in the figure, a dummy stage is further provided for resetting the n-th stage. The first to nth stages and the dummy stage have the same circuit configuration, and at least one clock signal having a different phase is supplied to the clock signal.

FIG. 10 is a diagram illustrating an example of a circuit configuration of the first and second stages S1 and S2 of the shift register according to the second embodiment of the present invention.

Referring to FIG. 10, the first stage S1 outputs a first clock signal CLK1 to the first gate line G1 under the control of the first node QA. And the first and second pull-down transistors T7O, which alternately output the low potential driving voltage Vss to the first gate line G1 per frame under the control of the second and third nodes QBOA and QBEA. A first output buffer configured of T7E), and a first controller configured of first to fifth bO transistors T1 to T5bO for controlling the first node QA and the second and third nodes QBOA and QBEA. .

The second stage S2 is the second pull-up transistor T16 and the fifth and sixth transistors which output the second clock signal CLK2 to the second gate line G2 under the control of the fourth node QB. Second output configured by third and fourth pull-down transistors T17O and T17E which alternately output the low potential drive voltage Vss to the second gate line G2 per frame under control of the nodes QBOB and QBEB. A second control unit includes a buffer and eleventh through fifteenth transistors T11 through T15bO for controlling the fourth node QB and the fifth and sixth nodes QBOB and QBEB.

In addition, the shift register according to the second embodiment of the present invention further includes a ripple down control unit 200 for synchronizing output signals Vg_out1 and Vg_out2 of the first and second stages S1 and S2. The ripple down control unit 200 includes first and second ripple down transistors RDTO and RDTE. In this case, the source and drain terminals of the first ripple down transistor RDTO are connected to the output terminals of the first and second stages S1 and S2, respectively, and the gate terminal is the fifth node QBOB of the second stage S2. ) Is connected. The source and drain terminals of the second ripple down transistor RDTE are connected to output terminals of the first and second stages S1 and S2, respectively, and the gate terminal of the sixth node QBEB of the second stage S2 is provided. ) Is connected. That is, the first and second ripple-down transistors RDTO and RDTE are turned on by the fifth and sixth nodes QBOB and QBEB of the second stage S2 so that the first and second stages S1 are controlled. , Output signals Vg_out1 and Vg_out2 of S2 are synchronized to a low voltage.

The first and second stages S1 and S2 are supplied with a high potential driving voltage Vdd, a low potential driving voltage Vss, and a start pulse Vst, and have a phase as shown in FIGS. 11A and 11B. Different clock signals are supplied. Hereinafter, an operation process of the first and second stages will be described in detail with reference to the driving waveforms shown in FIGS. 11A and 11B.

FIG. 11A is a drive waveform showing the odd frame period of FIG. 10.

Referring to FIG. 11A, in the AO period, the first stage S1 is turned on by the high voltage of the high potential driving voltage Vdd and the start pulse Vst, thereby turning off the high voltage. It is pre-charged to one node QA. The first pull-up transistor T6 is turned on by the high voltage pre-charged to the first node QA, so that the low voltage of the first clock signal CLK1 becomes the first output signal Vg_out1. It is supplied to the gate line G1. At this time, the fifth and fifth E transistors T5O and T5E turned on according to the high voltage of the start pulse Vst are turned on by the fifth bE transistor T5bE and the high voltage turned on by the odd frame high potential driving voltage VddO. A low voltage is supplied to the second and third nodes QBOA and QBEA together with the 5aO and 5aE transistors T5aO and T5aE turned on by the pre-charged first node QA. That is, the second and third nodes QBOA and QBEA are quickly discharged to maintain a low voltage state, so that the third transistor, the third E transistor, the first pull-down transistor, and the second pull-down transistor T3O, T3E, and T7O. T7E is turned off to block the discharge path of the first node QA through the third and third E transistors T3O and T3E.

Meanwhile, the fourth transistor T4O is turned on by the odd frame high potential driving voltage VddO to supply a high voltage to the second node QBOA, but as described above, the fifth and fifth aO transistors T5O, As a discharge path of the second node QBOA is secured by T5aO, the second node QBOA maintains a low voltage state. The fourth and fifth bE transistors T4O and T5bE are continuously turned on during the odd frame period by the odd frame high potential driving voltage VddO. Thus, the fifth bE transistor T5bE maintains the low voltage state of the third node QBEA even if another discharge path is turned off after the AO period of the odd frame.

In the AO period, the 14O and 15BE transistors of the second stage S2 are turned on through the high voltage of the odd frame high potential driving voltage VddO. The fifth node QBOB keeps the high voltage state by the 14O transistor T14O to turn on the 13O transistor and the third pull-down transistors T13O and T17O, and to the 15bE transistor T5bE. As a result, the sixth node QBEB is discharged to maintain the low voltage state. At this time, the fourth node QB maintains a low voltage state through the thirteenth transistor T13O, and the low voltage is second gated to the second output signal Vg_out2 through the third pull-down transistor T17O. It is supplied to the line G2.

In the AO period, the first ripple down transistor RDTO is turned on by the fifth node QBOB in the high voltage state to generate the ripple by synchronizing the first and second output signals Vg_out1 and Vg_out2 to a low voltage. Suppress In addition, each of the output terminals of the first and second stages S1 and S2 acts as a load to each other to reduce the height of the output signal even if ripple occurs. At this time, as shown in FIG. 11A, since the sixth node QBEB maintains a low voltage state in the odd frame period, the second ripple down transistor RDTE is not turned on in the odd frame period.

In the BO period, since the first transistor T1 is turned off by the low voltage of the start pulse Vst, the first node QA is floated to a high voltage state, and the first pull- Up transistor T6 remains turned on. At this time, the first node QA is bootstrapping due to the parasitic capacitance formed by overlapping the gate electrode and the drain electrode of the first pull-up transistor T6 due to the high voltage of the first clock signal CLK1. Charge to a higher voltage than the AO period. Accordingly, the first pull-up transistor T6 is surely turned on so that the high voltage of the first clock signal CLK1 is quickly supplied to the first gate line G1 as the first output signal Vg_out1. Meanwhile, the second and third nodes QBOA and QBEA discharged through the 5aO and 5aE transistors T5aO and T5aE turned on by the first node QA maintain a low voltage state. In addition, as described above, the fifth bE transistor T5bE maintains a low voltage state of the third node QBEA together with the fifth aE transistor T5aE by maintaining the turn-on state to discharge the third node QBEA. .

In the BO period, the second stage S2 is turned on by the high voltage of the high potential driving voltage Vdd and the first output signal Vg_out1 so that the eleventh transistor T11 is turned on so that the high voltage becomes the fourth node QB. Pre-charged). The second pull-up transistor T16 is turned on by the high voltage pre-charged to the fourth node QB so that the low voltage of the second clock signal CLK2 becomes the second output signal Vg_out2. It is supplied to the gate line G2. In this case, the 15O and 15E transistors T15O and T15E turned on according to the high voltage of the first output signal Vg_out1 may be connected to the 15bE transistor T15bE turned on by the odd frame high potential driving voltage VddO. A low voltage is supplied to the fifth and sixth nodes QBOB and QBEB along with the 15aO and 15aE transistors T15aO and T15aE turned on by the fourth node QB pre-charged with the high voltage. That is, the fifth and sixth nodes QBOB and QBEB are quickly discharged to maintain a low voltage state, so that the thirteenth transistor, the thirteenth transistor, the third pull-down transistor, and the fourth pull-down transistor T13O, T13E, and T17O. T17E is turned off to block the discharge path of the fourth node QB through the thirteenth and thirteenth transistors T13O and T13E.

The 14O transistor T14O is turned on by the odd frame high potential driving voltage VddO to supply a high voltage to the fifth node QBOB, but as described above, the 15O and 15AO transistors T15O, As a discharge path of the fifth node QBOB is secured by T15aO, the fifth node QBOB maintains a low voltage state. The 14O and 15bE transistors T14O and T15bE are continuously turned on during the odd frame period by the odd frame high potential driving voltage VddO. For this reason, the fifteenth bE transistor T15bE maintains the low voltage state of the sixth node QBEB even if another discharge path is turned off after the BO period of the odd frame.

In the BO period, the first ripple-down transistor RDTO is turned off by the fifth node QBOB in the low voltage state so that the first output signal Vg_out1 in the high voltage state and the second output signal in the low voltage state ( Vg_out2) is blocked from synchronizing.

In the CO period, the first output signal Vg_out1 maintains the high voltage of the first clock signal CLK1 by the first pull-up transistor T6 turned on in the BO period, and then becomes the CO period during the CO period. The first pull-up transistor T6 is output at a low voltage by the first clock signal CLK1 inverted to a low voltage before the state of the first pull-up transistor T6 is changed.

As described above, since the eleventh transistor T11 is turned off by the first output signal Vg_out1 which is in the low voltage state as described above, the fourth node QB is floated to the high voltage state. The third pull-up transistor T16 maintains the turn-on state. In this case, due to the high voltage of the second clock signal CLK2, the fourth node QB may be bootstrapping under the influence of parasitic capacitance formed by overlapping the gate electrode and the drain electrode of the third pull-up transistor T16. Charge to a voltage higher than the BO period. Accordingly, the third pull-up transistor T16 is reliably turned on so that the high voltage of the second clock signal CLK2 is rapidly supplied to the second gate line G2 as the second output signal Vg_out2. Meanwhile, the fifth and sixth nodes QBOB and QBEB discharged through the fifth and fifth aO transistors T5aO and T5aE turned on by the fourth node QB maintain a low voltage state. In addition, as described above, the fifth bE transistor T5bE maintains a low voltage state of the sixth node QBEB together with the fifth aE transistor T5aE by maintaining the turn-on to discharge the sixth node QBEB. .

The first stage S1 supplies a low voltage to the first node QA, in which the third a transistor T3a is turned on by the high voltage of the second output signal Vg_out2 to maintain a high voltage state until the BO period. To discharge. In this case, the 5aO and 5aE transistors T5aO and T5aE having the gate electrode connected to the first node QA are turned off to cut off the discharge paths of the second and third nodes QBOA and QBEA. On the other hand, a high voltage is supplied to the second node QBOA through the fourth transistor T4O turned on by the odd frame high potential driving voltage VddO, and the fifth bE transistor T5bE is turned on as described above. ), The third node QBEA receives a low voltage and maintains a low voltage state. Accordingly, the third transistors and the first pull-down transistors T3O and T7O are turned on by the second node QBOA in the high voltage state, and the first node QA is turned on through the third transistor T3O. Discharged faster, a low voltage is supplied to the first gate line G1 as the first output signal Vg_out1 through the first pull-down transistor T7O.

In the CO period, like the BO period, the first ripple down transistor RDTO is turned off by the fifth node QBOB in the low voltage state, so that the first output signal Vg_out1 in the low voltage state and the first voltage in the high voltage state are reduced. 2 The output signal Vg_out2 is blocked from synchronizing.

In the DO period, the second output signal Vg_out2 maintains the high voltage of the second clock signal CLK2 by the second pull-up transistor T16 which was turned on in the CO period, and then becomes the DO period. Before the state of the second pull-up transistor T16 is changed, the second pull-up transistor T16 is inverted to a low voltage and is output to the low voltage by the second clock signal CLK2. At this time, since the 13th transistor T13a is turned on by the third output signal Vg_out3 of the high voltage and the fourth node QB is in a discharge state, the fourth electrode QB is connected to the gate electrode. The 15aO and 15aE transistors T15aO and T15aE are turned off to cut off discharge paths of the fifth and sixth nodes QBOB and QBEB. In this case, the sixth node QBEB may be discharged by the 15th bE transistor T5bE, and the fifth node QBOB may float at a high voltage because it does not secure another discharge path.

According to the second output signal Vg_out2 of the low voltage, the third a transistor T3a of the first stage S1 is turned off. As described above, the fourth and fifth bE transistors are turned on through the high voltage of the odd frame high potential driving voltage VddO. By the fourth transistor T4O, the second node QBOA keeps the high voltage state to turn on the third transistor and the first pull-down transistors T3O and T7O, and to the fifth bE transistor T5bE. The third node QBEA is discharged to maintain the low voltage state. At this time, the first node QA maintains a low voltage state through the third transistor T3O, and the first gate line becomes the first output signal Vg_out1 through the first pull-down transistor T7O. The first output signal Vg_out1 supplied to (G1) maintains a low voltage state for the remaining odd frame period.

In the DO period, the first ripple down transistor RDTO is turned on by the fifth node QBOB in the high voltage state to synchronize the first and second output signals Vg_out1 and Vg_out2 to a low voltage. Suppress occurrence. In addition, each of the output terminals of the first and second stages S1 and S2 acts as a load to each other to reduce the height of the output signal even if ripple occurs. At this time, as shown in FIG. 11A, since the sixth node QBEB maintains a low voltage state in the odd frame period, the second ripple down transistor RDTE is not turned on in the odd frame period. As described above, the first ripple down transistor RDTO is always turned on except when the first and second output signals Vg_out1 and Vg_out2 are high voltage.

FIG. 11B is a drive waveform illustrating the even frame period of FIG. 10.

Referring to FIG. 11B, in the AE period, the first stage S1 is turned on by the high voltage of the high potential driving voltage Vdd and the start pulse Vst, thereby turning off the high voltage. It is pre-charged to one node QA. The first pull-up transistor T6 is turned on by the high voltage pre-charged to the first node QA, so that the low voltage of the first clock signal CLK1 becomes the first output signal Vg_out1. It is supplied to the gate line G1. At this time, the fifth and fifth E transistors T5O and T5E turned on according to the high voltage of the start pulse Vst are turned on by the fifth bO transistor T5bO and the high voltage turned on by the even frame high potential driving voltage VddE. A low voltage is supplied to the second and third nodes QBOA and QBEA together with the 5aO and 5aE transistors T5aO and T5aE turned on by the pre-charged first node QA. That is, the second and third nodes QBOA and QBEA are quickly discharged to maintain a low voltage state, so that the third transistor, the third E transistor, the first pull-down transistor, and the second pull-down transistor T3O, T3E, and T7O. T7E is turned off to block the discharge path of the first node QA through the third and third E transistors T3O and T3E.

On the other hand, the fourth E transistor T4E is turned on by the even frame high potential driving voltage VddE to supply a high voltage to the third node QBEA, but as described above, the fifth E and fifth aE transistors T5E, The discharge path of the third node QBEA is secured by T5aE so that the third node QBEA maintains a low voltage state. The fourth and fifth bO transistors T4E and T5bO remain turned on during the even frame period by the even frame high potential driving voltage VddE. Thus, the fifth bO transistor T5bO maintains the low voltage state of the second node QBOA even if another discharge path is turned off after the AE period of the even frame.

In the AE period, the 14E and 15BO transistors of the second stage S2 are turned on through the high voltage of the even frame high potential driving voltage VddE. The sixth node QBEB continues to maintain the high voltage state by the 14E transistor T14E to turn on the 13E transistor and the fourth pull-down transistors T13E and T17E, and to the 15bO transistor T5bO. As a result, the fifth node QBOB is discharged to maintain the low voltage state. At this time, the fourth node QB maintains the low voltage state through the 13E transistor T13E, and the low gate voltage is the second gate line as the second output signal Vg_out2 through the fourth pull-down transistor T17E. It is supplied to (G2).

In the AE period, the second ripple down transistor RDTE is turned on by the sixth node QBEB in the high voltage state to generate the ripple by synchronizing the first and second output signals Vg_out1 and Vg_out2 to a low voltage. Suppress In addition, each of the output terminals of the first and second stages S1 and S2 acts as a load to each other to reduce the height of the output signal even if ripple occurs. In this case, as shown in FIG. 11B, since the fifth node QBOB maintains a low voltage state in the even frame period, the first ripple down transistor RDTO is not turned on in the even frame period.

In the BE period, since the first transistor T1 is turned off by the low voltage of the start pulse Vst, the first node QA is floated to a high voltage state, and the first pull- Up transistor T6 remains turned on. At this time, the first node QA is bootstrapping due to the parasitic capacitance formed by overlapping the gate electrode and the drain electrode of the first pull-up transistor T6 due to the high voltage of the first clock signal CLK1. Charge to a higher voltage than the AE period. Accordingly, the first pull-up transistor T6 is surely turned on so that the high voltage of the first clock signal CLK1 is quickly supplied to the first gate line G1 as the first output signal Vg_out1. Meanwhile, the second and third nodes QBOA and QBEA discharged through the 5aO and 5aE transistors T5aO and T5aE turned on by the first node QA maintain a low voltage state. In addition, as described above, the fifth bO transistor T5bO maintains a low voltage state of the second node QBOA together with the fifth aO transistor T5aO by maintaining the turn-on state to discharge the second node QBOA. .

In the BE period, the second stage S2 is turned on by the high voltage of the high potential driving voltage Vdd and the first output signal Vg_out1 so that the eleventh transistor T11 is turned on so that the high voltage becomes the fourth node QB. Pre-charged). The second pull-up transistor T16 is turned on by the high voltage pre-charged to the fourth node QB so that the low voltage of the second clock signal CLK2 is the second output signal Vg_out2. It is supplied to the gate line G2. In this case, the 15O and 15E transistors T15O and T15E turned on according to the high voltage of the first output signal Vg_out1 may be connected to the 15bO transistor T15bO turned on by the even frame high potential driving voltage VddE. A low voltage is supplied to the fifth and sixth nodes QBOB and QBEB along with the 15aO and 15aE transistors T15aO and T15aE turned on by the fourth node QB pre-charged with the high voltage. That is, the fifth and sixth nodes QBOB and QBEB are quickly discharged to maintain a low voltage state, so that the thirteenth transistor, the thirteenth transistor, the third pull-down transistor, and the fourth pull-down transistor T13O, T13E, and T17O. T17E is turned off to block the discharge path of the fourth node QB through the thirteenth and thirteenth transistors T13O and T13E.

On the other hand, the 14E transistor T14E is turned on by the even frame high potential driving voltage VddE and supplies a high voltage to the sixth node QBEB. However, as described above, the 15EE and 15AE transistors T15E, As a discharge path of the sixth node QBEB is secured by T15aE, the sixth node QBEB maintains a low voltage state. The 14E and 15BO transistors T14E and T15bO remain turned on during the even frame period by the even frame high potential driving voltage VddE. For this reason, the 15th bO transistor T15bO maintains the low voltage state of the fifth node QBOB even if another discharge path is turned off after the BE period of the even frame.

In the BE period, the second ripple down transistor RDTE is turned off by the sixth node QBEB in the low voltage state, so that the first output signal Vg_out1 in the high voltage state and the second output signal in the low voltage state ( Vg_out2) is blocked from synchronizing.

In the CE period, the first output signal Vg_out1 maintains the high voltage of the first clock signal CLK1 by the first pull-up transistor T6 turned on in the BE period, and then becomes the CE period during the CE period. The first pull-up transistor T6 is output at a low voltage by the first clock signal CLK1 inverted to a low voltage before the state of the first pull-up transistor T6 is changed.

As described above, since the eleventh transistor T11 is turned off by the first output signal Vg_out1 which is in the low voltage state as described above, the fourth node QB is floated to the high voltage state. The third pull-up transistor T16 maintains the turn-on state. In this case, due to the high voltage of the second clock signal CLK2, the fourth node QB may be bootstrapping under the influence of parasitic capacitance formed by overlapping the gate electrode and the drain electrode of the third pull-up transistor T16. Charge to a higher voltage than the BE period. Accordingly, the third pull-up transistor T16 is reliably turned on so that the high voltage of the second clock signal CLK2 is rapidly supplied to the second gate line G2 as the second output signal Vg_out2. Meanwhile, the fifth and sixth nodes QBOB and QBEB discharged through the fifth and fifth aO transistors T5aO and T5aE turned on by the fourth node QB maintain a low voltage state. In addition, as described above, the fifth bO transistor T5bO maintains a low voltage state of the fifth node QBOB together with the fifth aO transistor T5aO by maintaining the turn-on state to discharge the fifth node QBOB. .

The first stage S1 applies the low voltage to the first node QA, which has maintained the high voltage state until the BE period by turning on the third a transistor T3a by the high voltage of the second output signal Vg_out2. Supply and discharge. In this case, the 5aO and 5aE transistors T5aO and T5aE having the gate electrode connected to the first node QA are turned off to cut off the discharge paths of the second and third nodes QBOA and QBEA. On the other hand, a high voltage is supplied to the third node QBEA through the fourth E transistor T4E turned on by the even frame high potential driving voltage VddE, and the fifth bO transistor T5bO turned on as described above. The second node QBOA receives a low voltage to maintain a low voltage state. Accordingly, the third E transistor and the second pull-down transistors T3E and T7E are turned on by the third node QBEA in a high voltage state, and the first node QA is turned on through the third E transistor T3E. Discharged faster, a low voltage is supplied to the first gate line G1 as the first output signal Vg_out1 through the second pull-down transistor T7E.

In the CE period, the second ripple down transistor RDTE is turned off by the sixth node QBEB in the low voltage state, similarly to the BE period, so that the first output signal Vg_out1 in the low voltage state and the first in the high voltage state are removed. 2 The output signal Vg_out2 is blocked from synchronizing.

In the DE period, the second output signal Vg_out2 maintains the high voltage of the second clock signal CLK2 by the second pull-up transistor T16 turned on in the CE period, and then becomes the DE period during the DE period. Before the state of the second pull-up transistor T16 is changed, the second pull-up transistor T16 is inverted to a low voltage and is output to the low voltage by the second clock signal CLK2. At this time, since the 13th transistor T13a is turned on by the third output signal Vg_out3 of the high voltage and the fourth node QB is in a discharge state, the fourth electrode QB is connected to the gate electrode. The 15aO and 15aE transistors T15aO and T15aE are turned off to interrupt the discharge paths of the fifth and sixth nodes QBOB and QBEB. At this time, the fifth node QBOB may be discharged by the 15bO transistor T5bO, and the sixth node QBEB may float at a high voltage because it does not secure another discharge path.

According to the second output signal Vg_out2 of the low voltage, the third a transistor T3a of the first stage S1 is turned off. Meanwhile, as described above, the fourth and fifth bO transistors are turned on through the high voltage of the even frame high potential driving voltage VddE. The third node QBEA keeps the high voltage state by the fourth E transistor T4E to turn on the third E transistor and the second pull-down transistors T3E and T7E, and to the fifth bO transistor T5bE. The second node QBOA is discharged to maintain the low voltage state. At this time, the first node QA maintains the low voltage state through the third E transistor T3E, and the first gate line is the first gate line as the first output signal Vg_out1 through the second pull-down transistor T7E. The first output signal Vg_out1 supplied to (G1) maintains a low voltage state for the remaining even frame period.

In the DE period, the second ripple down transistor RDTE is turned on by the sixth node QBE in a high voltage state to generate the ripple by synchronizing the first and second output signals Vg_out1 and Vg_out2 to a low voltage. Suppress In addition, each of the output terminals of the first and second stages S1 and S2 acts as a load to each other to reduce the height of the output signal even if ripple occurs. In this case, as shown in FIG. 11B, since the fifth node QBOB maintains a low voltage state in the even frame period, the first ripple down transistor RDTO is not turned on in the even frame period. As described above, the second ripple down transistor RDTE is always turned on except when the first and second output signals Vg_out1 and Vg_out2 are high voltage.

12 is a view showing an output signal waveform of a shift register according to the present invention. Referring to FIG. 12, it can be seen that the ripple height generated when the output signal Vg_out is in a low voltage state is reduced compared to that of FIG. 5.

As described above, the shift register and the liquid crystal display using the same according to the present invention include a ripple down control unit for synchronizing two output signals when the output signals of both stages are in a low voltage state, so that both output signals are low voltage. The ripple is suppressed by the two output terminals acting as loads to each other while maintaining the state.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (14)

A first stage charging a first output terminal in response to a voltage of a first node and discharging the first output terminal in response to a voltage of a second node; A second stage for driving according to the voltage of the first output terminal and charging the second output terminal in response to the voltage of the third node and discharging the second output terminal in response to the voltage of the fourth node; And And a ripple down controller configured to connect the first output terminal and the second output terminal in response to the voltage of the fourth node. According to claim 1, And an output signal of the first output terminal and an output signal of the second output terminal are synchronized to a low voltage when the fourth node is at a high voltage. According to claim 1, The ripple down controller may include a ripple down transistor having a gate terminal connected to the fourth node and a source and drain terminal connected to the first and second output terminals, respectively. A first stage that charges a first output terminal in response to a voltage of a first node and discharges the first output terminal in response to voltages of a second and third node; A second stage driving according to the voltage of the first output terminal and charging the second output terminal in response to the voltage of the fourth node and discharging the second output terminal in response to the voltages of the fifth and sixth nodes; And And a ripple down controller configured to connect the first output terminal and the second output terminal in response to the voltage of the fourth node. The method of claim 4, wherein The second and fifth nodes discharge the first and fourth nodes during an odd frame period, And the third and sixth nodes discharge the first and fourth nodes during an even frame period. The method of claim 4, wherein And the output signal of the first output terminal and the output signal of the second output terminal are synchronized to a low voltage when the fifth and sixth nodes are at a high voltage. According to claim 1, The ripple down control unit, A first ripple down transistor having a gate terminal connected to the fifth node and a source and drain terminal connected to the first and second output terminals, respectively; And And a second ripple down transistor having a gate terminal connected to the sixth node and a source and drain terminal connected to the first and second output terminals, respectively. A liquid crystal display panel in which a plurality of gate lines and a plurality of data lines intersect and a plurality of liquid crystal cells are disposed; A first stage that charges a first output terminal in response to a voltage of a first node, discharges the first output terminal in response to a voltage of a second node, and drives according to a voltage of the first output terminal A second stage that charges a second output terminal in response to a voltage of the second output terminal, and discharges the second output terminal in response to a voltage of a fourth node; and the first output terminal and the response in response to a voltage of the fourth node. A gate driving circuit sequentially supplying scan pulses to the gate lines, including a shift register having a ripple down control unit connecting a second output terminal; And And a data driving circuit for supplying data voltages to the data lines. The method of claim 8, And an output signal of the first output terminal and an output signal of the second output terminal are synchronized to a low voltage when the fourth node is at a high voltage. The method of claim 8, The ripple down controller may include a ripple down transistor having a gate terminal connected to the fourth node and a source and drain terminal connected to the first and second output terminals, respectively. A liquid crystal display panel in which a plurality of gate lines and a plurality of data lines intersect and a plurality of liquid crystal cells are disposed; Charging a first output terminal in response to a voltage of a first node, driving a first stage to discharge the first output terminal in response to voltages of a second node and a third node, and driving according to a voltage of the first output terminal A second stage for charging the second output terminal in response to the voltage of the fourth node, discharging the second output terminal in response to the voltages of the fifth and sixth nodes, and in response to the voltage of the fourth node; A gate driving circuit sequentially supplying scan pulses to the gate lines, including a shift register having a ripple down control unit connecting a first output terminal to the second output terminal; And And a data driving circuit for supplying data voltages to the data lines. The method of claim 11, wherein The second and fifth nodes discharge the first and fourth nodes during an odd frame period, And the third and sixth nodes discharge the first and fourth nodes during an even frame period. The method of claim 11, wherein And an output signal of the first output terminal and an output signal of the second output terminal are synchronized to a low voltage when the fifth and sixth nodes are high voltage. The method of claim 11, wherein The ripple down control unit, A first ripple down transistor having a gate terminal connected to the fifth node and a source and drain terminal connected to the first and second output terminals, respectively; And And a second ripple down transistor having a gate terminal connected to the sixth node and a source and drain terminal connected to the first and second output terminals, respectively.

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