KR20080001208A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20080001208A
KR20080001208A KR1020060059381A KR20060059381A KR20080001208A KR 20080001208 A KR20080001208 A KR 20080001208A KR 1020060059381 A KR1020060059381 A KR 1020060059381A KR 20060059381 A KR20060059381 A KR 20060059381A KR 20080001208 A KR20080001208 A KR 20080001208A
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contact hole
ion implantation
semiconductor device
etching
forming
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KR1020060059381A
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Korean (ko)
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김규성
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주식회사 하이닉스반도체
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Priority to KR1020060059381A priority Critical patent/KR20080001208A/en
Publication of KR20080001208A publication Critical patent/KR20080001208A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to secure a contact area by forming a contact hole having a lower bending part. An interlayer dielectric(130) is formed on an upper part of a semiconductor substrate(100) including a gate pattern. A first contact hole is formed by etching the interlayer dielectric. An ion implantation region is formed on both sides of an edge part of a lower part of the first contact hole. A second contact hole having a bending part is formed by etching the first contact hole. A barrier layer is formed on the entire surface including the second contact hole. A bit line is formed to bury the second contact hole. The ion implantation region is formed by performing an ion implantation process.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도.2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 콘택홀 하부의 에지부 양측에 고농도의 이온 주입 영역을 형성하여 도핑 농도에 따른 식각 속도 차이를 이용한 식각 공정으로 하부에 굴곡부를 구비한 콘택홀을 형성함으로써, 콘택 면적을 확보하여 콘택 저항을 감소시키는 기술을 개시한다. The present invention relates to a method for manufacturing a semiconductor device, by forming a high concentration of ion implantation regions on both sides of the edge portion of the lower contact hole to form a contact hole having a bent portion at the bottom by an etching process using an etching rate difference according to the doping concentration. As a result, a technique of securing a contact area to reduce contact resistance is disclosed.

최근 반도체 소자의 크기가 작아짐에 따라 비트라인 콘택홀의 크기도 작아지게 되며, 이는 콘택 저항의 증가를 유발시킨다. Recently, as the size of a semiconductor device decreases, the size of a bit line contact hole also decreases, which causes an increase in contact resistance.

비트라인과 활성영역과의 콘택 저항은 배리어막을 형성하는 물질 또는 콘택홀의 크기에 따라 변하게 되는데, 트랜지스터에 흐르는 전류의 양을 충분히 확보하기 위해서는 콘택 저항이 낮아야 한다.The contact resistance between the bit line and the active region varies depending on the material of the barrier layer or the size of the contact hole. In order to sufficiently secure the amount of current flowing through the transistor, the contact resistance must be low.

이와 같이 콘택 저항을 낮추기 위해서는 저항이 작은 물질로 배리어막을 형성하거나 콘택 면적을 증가시키는 방법이 있는데, 콘택 면적을 증가시키는 방법은 디자인 룰에 따라 한계가 있다. In order to reduce the contact resistance as described above, there is a method of forming a barrier layer or increasing the contact area with a material having a small resistance, but the method of increasing the contact area has limitations according to design rules.

도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 것이다. 1A to 1D illustrate a method of manufacturing a semiconductor device according to the prior art.

도 1a를 참조하면, 게이트 전극(57)이 구비된 반도체 기판 상부에 제 1 층간 절연막(60) 및 제 2 층간 절연막(65)를 형성한다. Referring to FIG. 1A, a first interlayer insulating layer 60 and a second interlayer insulating layer 65 are formed on a semiconductor substrate provided with a gate electrode 57.

도 1b를 참조하면, 제 1 및 제 2 층간 절연막(60, 65)를 식각하여 비트라인 콘택홀(70)을 형성한다. Referring to FIG. 1B, bit line contact holes 70 may be formed by etching the first and second interlayer insulating layers 60 and 65.

여기서, 비트라인 콘택홀(70)의 선폭은 정해진 스펙에 따라 결정되므로 그 선폭을 임의로 증가시켜 콘택 면적을 확장시킬 수 없다.Since the line width of the bit line contact hole 70 is determined according to a predetermined specification, the line area may not be arbitrarily increased to extend the contact area.

도 1c를 참조하면, 비트라인 콘택홀(70)을 포함하는 전체 표면 상부에 일정두께의 배리어막(75)을 형성한다. Referring to FIG. 1C, a barrier layer 75 having a predetermined thickness is formed on an entire surface including the bit line contact hole 70.

이때, 배리어막(75)은 Ti 및 TiN의 적층구조로 형성하는 것이 바람직하다. At this time, the barrier film 75 is preferably formed of a stacked structure of Ti and TiN.

도 1d를 참조하면, 비트라인 콘택홀(70)을 매립하는 비트라인(80)을 형성한다. Referring to FIG. 1D, the bit line 80 filling the bit line contact hole 70 is formed.

여기서, 비트라인(80)은 텅스텐을 증착하여 형성한다. Here, the bit line 80 is formed by depositing tungsten.

상술한 종래 기술에 따른 반도체 소자의 제조 방법에서, 반도체 소자의 크기가 감소함에 따라 비트라인 콘택의 크기도 작아지게 되며, 이는 콘택 저항이 증가되는 문제점이 있다. In the above-described method for manufacturing a semiconductor device according to the related art, as the size of the semiconductor device decreases, the size of the bit line contact also decreases, which increases the contact resistance.

상기 문제점을 해결하기 위하여, 콘택홀 하부의 에지부 양측에 고농도의 이온 주입 영역을 형성하여 도핑 농도에 따른 식각 속도 차이를 이용한 식각 공정으로 하부에 굴곡부를 구비한 콘택홀을 형성함으로써, 콘택 면적을 확보하여 콘택 저항을 감소시키는 반도체 소자의 제조 방법을 제공하는 것을 목적으로 한다. In order to solve the above problems, by forming a high concentration of ion implantation regions on both sides of the lower edge of the contact hole to form a contact hole having a bent portion at the bottom by an etching process using an etching rate difference according to the doping concentration, It is an object of the present invention to provide a method for manufacturing a semiconductor device which secures and reduces contact resistance.

본 발명에 따른 반도체 소자의 제조 방법은 Method for manufacturing a semiconductor device according to the present invention

게이트 패턴이 구비된 반도체 기판 상부에 층간 절연막을 형성하고, 상기 층간 절연막을 식각하여 제 1 콘택홀을 형성하는 단계; 상기 제 1 콘택홀 하부의 에지부 양측에 이온 주입 영역을 형성하는 단계; 상기 제 1 콘택홀 하부를 더 식각하여 굴곡부가 구비된 제 2 콘택홀을 형성하는 단계; 상기 제 2 콘택홀을 포함한 전체 표면 상부에 배리어막을 형성한 후 상기 제 2 콘택홀을 매립하는 비트라인을 형성하는 단계를 포함하는 것을 특징으로 한다. Forming an interlayer insulating layer on the semiconductor substrate including the gate pattern, and etching the interlayer insulating layer to form a first contact hole; Forming ion implantation regions on both sides of an edge portion of the lower portion of the first contact hole; Further etching the lower portion of the first contact hole to form a second contact hole having a bent portion; And forming a bit line on the entire surface including the second contact hole, and then forming a bit line to fill the second contact hole.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도이다.2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

도 2a를 참조하면, 활성영역을 정의하는 소자분리막(105)이 구비된 반도체 기판(100) 상부에 폴리실리콘층(110), 게이트 금속층(115) 및 게이트 하드마스크층(120)의 적층구조를 형성하고, 상기 적층구조를 식각하여 게이트 패턴을 형성한 후 상기 게이트 패턴 측벽에 스페이서(125)를 형성한다. Referring to FIG. 2A, a stacked structure of a polysilicon layer 110, a gate metal layer 115, and a gate hard mask layer 120 is formed on a semiconductor substrate 100 having an isolation layer 105 defining an active region. After forming a gate pattern by etching the stacked structure, spacers 125 are formed on sidewalls of the gate pattern.

다음에, 전체 표면 상부에 층간 절연막(130)을 형성한다. Next, an interlayer insulating film 130 is formed over the entire surface.

도 2b를 참조하면, 층간 절연막(130)을 식각하여 비트라인 제 1 콘택홀(140a)를 형성한다. Referring to FIG. 2B, the interlayer insulating layer 130 is etched to form the bit line first contact hole 140a.

도 2c를 참조하면, 소정 각도를 가지는 경사 이온 주입 공정을 수행하여 제 1 콘택홀(140a) 하부 에지부 양측에 고농도 저에너지 이온 주입 영역(150)을 형성한다. Referring to FIG. 2C, a high concentration low energy ion implantation region 150 is formed on both sides of the lower edge portion of the first contact hole 140a by performing a gradient ion implantation process having a predetermined angle.

이때, 제 1 콘택홀(140a) 하부의 에지부 양측에 B, BF2, P,As, In, C, N, Sb, Ge 또는 이들의 조합 중 선택된 어느 하나를 사용한 이온 주입 공정으로 기판 내부에 도핑 농도를 변화시킨다.At this time, the doping inside the substrate by an ion implantation process using any one selected from B, BF2, P, As, In, C, N, Sb, Ge, or a combination thereof on both sides of the edge portion of the lower portion of the first contact hole 140a Change the concentration.

도 2d를 참조하면, 식각 또는 클리닝 공정을 수행하여 이온 주입 영역(150)을 제거하여 제 1 콘택홀(140a)보다 하부 면적이 확장된 제 2 콘택홀(140b)를 형성한다. Referring to FIG. 2D, the ion implantation region 150 is removed by etching or cleaning to form a second contact hole 140b having a lower area than the first contact hole 140a.

여기서, 고농도인 이온 주입 영역(150)과 저농도의 반도체 기판(100)의 농도 차이로 인해 식각 속도가 다르게 되므로 이온 주입 영역(150)에 따라 3차원 굴곡부가 형성되며, 이는 콘택홀 선폭의 변화없이 하부의 면적을 확장시킬 수 있다. Here, since the etching rate is different due to the difference in concentration between the high concentration of the ion implantation region 150 and the low concentration of the semiconductor substrate 100, a three-dimensional bent portion is formed according to the ion implantation region 150, without changing the contact hole line width. The area of the lower part can be expanded.

이때, 고농도의 이온 주입 영역(150)이 저농도의 반도체 기판(100)에 비해 더 많이 식각되며, 고농도 영역은 기판 표면으로부터 100 내지 200Å의 깊이로 식각된다. At this time, the high concentration of the ion implantation region 150 is etched more than the low concentration of the semiconductor substrate 100, the high concentration region is etched to a depth of 100 ~ 200Å from the substrate surface.

도 2e를 참조하면, 제 2 콘택홀(140b)을 포함한 전체 표면 상부에 일정 두께 의 배리어막(155)을 형성한다. Referring to FIG. 2E, a barrier layer 155 having a predetermined thickness is formed on the entire surface including the second contact hole 140b.

여기서, 배리어막(155)은 티타늄(Ti), 티나늄질화막(TiN), 코발트(Co) 또는 이들의 적층구조 중 선택된 어느 하나로 형성하는 것이 바람직하다. The barrier film 155 may be formed of any one selected from titanium (Ti), titanium nitride film (TiN), cobalt (Co), or a stacked structure thereof.

도 2f를 참조하면, 제 2 콘택홀(140b)를 매립하는 비트라인(160)을 형성한다. Referring to FIG. 2F, a bit line 160 filling the second contact hole 140b is formed.

여기서, 비트라인(160)은 텅스텐층으로 형성하는 것이 바람직하다. The bit line 160 may be formed of a tungsten layer.

본 발명에 따른 반도체 소자의 제조 방법은 콘택홀 하부의 에지부 양측에 고농도의 이온 주입 영역을 형성하여 도핑 농도에 따른 식각 속도 차이를 이용한 식각 공정으로 하부에 굴곡부를 구비한 콘택홀을 형성함으로써, 콘택 면적을 확보하여 콘택 저항을 감소시키는 효과가 있다. In the method of manufacturing a semiconductor device according to the present invention, a high concentration of ion implantation regions are formed on both sides of an edge portion of a lower portion of a contact hole, thereby forming a contact hole having a bent portion in the lower portion by an etching process using an etching rate difference according to a doping concentration. There is an effect of reducing the contact resistance by securing a contact area.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

게이트 패턴이 구비된 반도체 기판 상부에 층간 절연막을 형성하고, 상기 층간 절연막을 식각하여 제 1 콘택홀을 형성하는 단계;Forming an interlayer insulating layer on the semiconductor substrate including the gate pattern, and etching the interlayer insulating layer to form a first contact hole; 상기 제 1 콘택홀 하부의 에지부 양측에 이온 주입 영역을 형성하는 단계; Forming ion implantation regions on both sides of an edge portion of the lower portion of the first contact hole; 상기 제 1 콘택홀을 더 식각하여 굴곡부가 구비된 제 2 콘택홀을 형성하는 단계; 및Further etching the first contact hole to form a second contact hole with a bent portion; And 상기 제 2 콘택홀을 포함한 전체 표면 상부에 배리어막을 형성한 후 상기 제 2 콘택홀을 매립하는 비트라인을 형성하는 단계;Forming a bit line on the entire surface including the second contact hole and forming a bit line to fill the second contact hole; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법. Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 이온 주입 영역은 경사 이온 주입 공정을 수행하여 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The ion implantation region is formed by performing a gradient ion implantation process. 제 1 항에 있어서, The method of claim 1, 상기 제 2 콘택홀은 이온 주입 영역과 반도체 기판과의 식각 선택비 차이로 굴곡부를 가지도록 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.And the second contact hole is formed to have a bent portion due to a difference in etching selectivity between the ion implantation region and the semiconductor substrate. 제 1 항에 있어서, The method of claim 1, 상기 제 2 콘택홀은 기판 표면으로부터 100 내지 200Å의 깊이로 식각하여 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The second contact hole is a method of manufacturing a semiconductor device, characterized in that formed by etching to a depth of 100 ~ 200Å from the substrate surface. 제 1 항에 있어서, The method of claim 1, 상기 배리어막은 티타늄, 티타늄질화막, 코발트 또는 이들의 적층구조 중 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The barrier film is a semiconductor device manufacturing method, characterized in that formed of any one selected from titanium, titanium nitride film, cobalt or a laminated structure thereof. 제 1 항에 있어서, The method of claim 1, 상기 이온 주입 공정은 B, BF2, P,As, In, C, N, Sb, Ge 또는 이들의 조합 중 선택된 어느 하나를 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 제조 방법. The ion implantation process is performed using any one selected from B, BF 2 , P, As, In, C, N, Sb, Ge, or a combination thereof.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101019247B1 (en) * 2008-12-29 2011-03-04 주식회사 판금사 승진기업 Control box

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101019247B1 (en) * 2008-12-29 2011-03-04 주식회사 판금사 승진기업 Control box

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