KR20080000904A - Method of forming a word line in the semiconductor memory device - Google Patents

Method of forming a word line in the semiconductor memory device Download PDF

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KR20080000904A
KR20080000904A KR1020060058785A KR20060058785A KR20080000904A KR 20080000904 A KR20080000904 A KR 20080000904A KR 1020060058785 A KR1020060058785 A KR 1020060058785A KR 20060058785 A KR20060058785 A KR 20060058785A KR 20080000904 A KR20080000904 A KR 20080000904A
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pattern
word line
forming
hard mask
film
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KR1020060058785A
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KR100863421B1 (en
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홍영옥
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

A method of forming a word line in a semiconductor memory device is provided to reduce a size of a chip by enlarging a first or second selection transistor region pattern when patterning a photoresist. A tunnel oxide layer(102), a first conductive layer(103), a dielectric layer(104), a second conductive layer(105), and a hard mask(106) are sequentially deposited on a semiconductor substrate(101). A photoresist pattern(107) is formed on the hard mask, and then is patterned to form a hard mask pattern. A first insulating layer is formed on the hard mask pattern, and then is etched until the hard mask pattern is exposed, thereby forming an opening between patterns of a word line region. A second insulating layer is formed on the opening, and then the first insulating layer is removed to form a mask pattern for forming a word line.

Description

반도체 메모리 장치의 워드라인 형성 방법{Method of forming a word line in the semiconductor memory device}Method of forming a word line in the semiconductor memory device

도 1은 종래의 워드라인을 도시한 단면도이다.1 is a cross-sectional view showing a conventional word line.

도 2(a) 내지 도 2(e)는 본 발명에 따른 반도체 메모리 장치의 워드라인 형성 방법을 도시한 단면도이다.2 (a) to 2 (e) are cross-sectional views illustrating a word line forming method of a semiconductor memory device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

101 : 반도체 기판 102 : 터널 산화막101 semiconductor substrate 102 tunnel oxide film

103 : 제 1 도전막 104 : 유전체막103: first conductive film 104: dielectric film

105 : 제 2 도전막 106 : 하드마스크105: second conductive film 106: hard mask

107 : 포토 레지스트 108 : 제 1 절연막107 photoresist 108 first insulating film

109 : 제 2 절연막109: second insulating film

본 발명은 반도체 메모리 장치의 제조 방법에 관한 것으로 특히, 반도체 메 모리 장치의 워드라인 형성 방법에 관한 것이다. The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of forming a word line of a semiconductor memory device.

최근 개발되고 있는 반도체 메모리 장치의 크기가 줄어듦에 따라 반도체 메모리 장치는 종래의 사진(photo) 장비로 제작될 경우, 한번에 패턴(pattern)을 형성하기란 어렵다. 따라서, 두 번의 마스크(mask) 공정을 통한 형성 방법 또는 한번의 마스크 공정과 스페이스(space) 형성 및 식각 공정을 사용하여 패터닝(patterning)을 하게 된다. 이때, 한번의 마스크 공정과 스페이스 형성 및 식각을 통한 패턴형성 방식을 이중노광기술(double expose technique; 이하 DET로 칭함)이라고 한다. 하지만, N개 스트링의 게이트 마스크를 형성하였다면, 최종 형성되는 스트링은 스페이스 DET 공정을 통해 2N+1개의 패턴이 형성된다. As the size of a semiconductor memory device being developed has recently been reduced, it is difficult to form a pattern at a time when the semiconductor memory device is manufactured with conventional photo equipment. Therefore, patterning may be performed by using two mask processes, or one mask process and a space formation and etching process. At this time, the pattern formation method through one mask process, space formation and etching is referred to as a double exposure technique (hereinafter referred to as DET). However, if N gate masks are formed, 2N + 1 patterns are formed through the space DET process.

도 1은 종래의 워드라인을 도시한 단면도이다. 도 1(a)를 참조하면, 32개의 워드라인을 형성할 시에 더미 라인을 마스크 작업을 통하여 제거한 경우이다. 그러면 소스 선택 라인(SSL)과 제 1 워드라인(WL0)간의 스페이스(A)가 증가하여 저항을 많이 받게 된다. 도 1(b)를 참조하면, 32개의 워드라인을 형성할 시에 더미 라인(B)을 그대로 두는 경우의 도면이다. 그러면 필요한 32개의 워드라인 외에 불필요한 1개의 워드라인이 더미라인으로 존재하게 되어 칩의 면적을 차지하게 된다.1 is a cross-sectional view showing a conventional word line. Referring to FIG. 1A, when forming 32 word lines, a dummy line is removed through a mask operation. As a result, the space A between the source select line SSL and the first word line WL0 increases to receive a lot of resistance. Referring to FIG. 1B, the dummy line B is left as it is when forming 32 word lines. Then, one unnecessary word line exists as a dummy line in addition to the necessary 32 word lines, taking up the area of the chip.

이러한 방식으로 워드라인을 형성하게 되면 필요한 개수의 워드라인 외에 한 개의 워드라인이 더 형성되므로, 이는 더미 워드라인(dummy word line)이 되어서 셀(cell)의 구성이 복잡해지고 칩의 면적을 차지하게 된다. 또한, 불필요하게 형성된 워드라인을 마스크작업을 추가하여 제거할 경우에 선택 트랜지스터의 게이트와 인접한 워드라인 스페이스가 커지게 되어 그 사이의 저항을 받게 되므로 신뢰도가 낮아질 수 있다. If a word line is formed in this manner, one word line is formed in addition to the required number of word lines, which becomes a dummy word line, which complicates the composition of a cell and occupies a chip area. do. In addition, when the unnecessary word line is removed by adding a mask operation, the word line space adjacent to the gate of the selection transistor becomes large and receives resistance therebetween, thereby lowering reliability.

따라서, 본 발명이 이루고자 하는 기술적 과제는 감광막 패터닝시에 불필요한 워드라인이 형성되는 부분까지 마스크를 형성하여 스페이스를 줄여 선택 트랜지스터의 게이트와 인접한 워드라인 사이에 산화막이 형성되지 않도록 하는 데 있다. Accordingly, a technical problem of the present invention is to form a mask to a portion where unnecessary word lines are formed during photoresist patterning so that an oxide film is not formed between the gate of the selection transistor and an adjacent word line by forming a mask.

본 발명의 실시 예에 따른 반도체 메모리 장치의 워드라인 제조 방법은, 반도체 기판 상부에 터널 산화막, 플로팅 게이트용 제 1 도전막, 유전체막, 플로팅 게이트용 제 2 도전막, 하드 마스크막을 순차적으로 형성하는 단계, 하드 마스크막 상부에 포토 레지스트 패턴을 형성하는 단계, 하드 마스크막을 패터닝하여 하드 마스크막 패턴을 형성하는 단계, 하드 마스크막 패턴 상부에 제 1 절연막을 형성하는 단계, 하드 마스크막 패턴이 노출될 때까지 제 1 절연막을 식각하여 워드라인 영역의 패턴들 사이에 개구부가 형성되는 단계, 개구부에 제 2 절연막을 형성하는 단계 및 잔류된 제 1 절연막을 제거하여 워드라인 형성용 마스크 패턴을 형성하는 단계를 포함하는 반도체 메모리 장치의 워드라인 형성 방법을 포함한다.In the method of manufacturing a word line of a semiconductor memory device according to an embodiment of the present invention, a tunnel oxide film, a floating gate first conductive film, a dielectric film, a floating gate second conductive film, and a hard mask film are sequentially formed on a semiconductor substrate. Forming a photoresist pattern over the hard mask film, patterning the hard mask film to form a hard mask film pattern, forming a first insulating film over the hard mask film pattern, and exposing the hard mask film pattern Etching the first insulating film until the opening is formed between the patterns of the word line region, forming the second insulating film in the opening, and removing the remaining first insulating film to form the mask pattern for forming the word line It includes a word line forming method of a semiconductor memory device comprising a.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다 른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be embodied in various other forms, and only the present embodiments make the disclosure of the present invention complete and the scope of the invention to those skilled in the art. It is provided to inform you completely.

도 2(a) 내지 도 2(e)는 본 발명에 따른 반도체 메모리 장치의 워드라인 형성 방법을 도시한 단면도이다. 2 (a) to 2 (e) are cross-sectional views illustrating a word line forming method of a semiconductor memory device according to the present invention.

도 2(a)를 참조하면, 반도체 기판(101) 상부에 터널 산화막(102), 플로팅 게이트용 제 1 도전막(103), 유전체막(104), 컨트롤 게이트용 제 2 도전막(105), 하드 마스크막(106) 및 포토 레지스트(107)를 순차적으로 형성한다. 사진 및 식각 공정으로 포토 레지스트(107)를 패터닝 한다. 더미 라인이 형성되는 부분(C)까지 포토 레지스트(107)로 가리도록 하여 포토 레지스트 패턴(107)을 형성함으로써 스페이스를 줄이도록 한다. 이때, 워드라인 영역의 최외측 패턴과 선택 트랜지스터 영역의 패턴간의 간격이 워드라인 영역의 패턴간의 간격보다 좁아지도록 포토 레지스트 패턴(107)을 형성한다. 포토 레지스트 패터닝은 제 1 선택 트랜지스터 영역 또는 제 2 선택 트랜지스터 영역 중 어느 하나를 확장하여 패터닝 한다. Referring to FIG. 2A, a tunnel oxide film 102, a floating gate first conductive film 103, a dielectric film 104, and a control gate second conductive film 105 are disposed on a semiconductor substrate 101. The hard mask film 106 and the photoresist 107 are formed sequentially. The photoresist 107 is patterned by a photolithography and an etching process. The photoresist pattern 107 is formed by covering the photoresist 107 up to the portion C where the dummy line is formed, thereby reducing the space. At this time, the photoresist pattern 107 is formed such that the interval between the outermost pattern of the word line region and the pattern of the selection transistor region is smaller than the interval between the patterns of the word line region. Photoresist patterning extends and patternes either the first selection transistor region or the second selection transistor region.

도 2(b)를 참조하면, 포토 레지스트(107)를 마스크로 하여 노출된 하드마스크막(106)을 제거하여 하드 마스크막 패턴을 형성한다. 결과물 표면을 따라 제 1 절연막(108)으로 질화막을 형성한다. 제 1 절연막(108)은 하드 마스크막 패턴의 형상을 따라 형성되도록 하며, 하드 마스크막 패턴 사이가 넓은 지역은 제 1 절연막(108)에 의해 패턴 사이가 매립되지 않을 정도로 형성한다. Referring to FIG. 2B, the exposed hard mask film 106 is removed using the photoresist 107 as a mask to form a hard mask film pattern. A nitride film is formed from the first insulating film 108 along the resultant surface. The first insulating film 108 is formed in the shape of the hard mask film pattern, and a wide area between the hard mask film patterns is formed so that the pattern is not filled between the patterns by the first insulating film 108.

도 2(c)를 참조하면, 하드 마스크막(106) 패턴이 노출될 때까지 제 1 절연 막(108)을 식각하여 워드라인 영역의 패턴들 사이에 개구부(D)를 형성한다. 이때, 제 1 절연막(108) 상부(E, F)는 모두 식각되어 하드 마스크막(106) 및 제 2 도전막(105)의 일부가 드러나도록 한다. 워드라인 영역의 패턴들 사이의 개구부(D)를 매립하도록 제 2 절연막(109)으로 산화막을 형성한 후 평탄화 공정을 수행한다. 바람직하게는 산화막은 매립특성이 좋은 HDP 산화막을 사용하며, 평탄화 공정도 츠ㅖ를 사용한다.Referring to FIG. 2C, the first insulating layer 108 is etched until the hard mask layer 106 pattern is exposed to form openings D between the patterns of the word line region. In this case, the upper portions E and F of the first insulating layer 108 are etched to expose portions of the hard mask layer 106 and the second conductive layer 105. After the oxide film is formed with the second insulating film 109 to fill the opening D between the patterns of the word line region, the planarization process is performed. Preferably, the oxide film uses an HDP oxide film having good buried characteristics, and the planarization process uses Tsu-chan.

도 2(d)를 참조하면, 워드라인 영역에 잔류하는 제 1 절연막(108)을 제거하면 하드 마스크(106)와 제 2 절연막(109)은 워드라인 형성용 마스크 패턴이 된다. 워드라인 마스크 패턴을 식각 마스크로 이용하여 노출된 제 2 도전막(105)을 식각한다.Referring to FIG. 2D, when the first insulating layer 108 remaining in the word line region is removed, the hard mask 106 and the second insulating layer 109 become a mask pattern for forming a word line. The exposed second conductive layer 105 is etched using the word line mask pattern as an etch mask.

도 2(e)를 참조하면, 워드라인 마스크 패턴(106, 109)을 제거하여 짝수개의 워드라인을 형성한다.Referring to FIG. 2E, word line mask patterns 106 and 109 are removed to form even word lines.

상기에서 설명한 본 발명의 기술적 사상은 바람직한 실시예에서 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술적 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같이 본 발명에 의하면, 포토 레지스트 패터닝시에 제 1 또는 제 2 선택 트랜지스터 영역 패턴을 확장하여 형성함으로써 워드라인과 선택 트랜지스터 영역 패턴간의 스페이스를 줄임으로써 칩의 크기를 줄일 수 있고, 소자 동작의 단순화를 이룰 수 있다.As described above, according to the present invention, the size of the chip can be reduced by reducing the space between the word line and the selection transistor region pattern by extending the first or second selection transistor region pattern during photoresist patterning. Can be simplified.

Claims (6)

반도체 기판 상부에 터널 산화막, 제 1 도전막, 유전체막, 제 2 도전막, 하드 마스크막을 순차적으로 형성하는 단계;Sequentially forming a tunnel oxide film, a first conductive film, a dielectric film, a second conductive film, and a hard mask film on the semiconductor substrate; 상기 하드 마스크막 상부에 포토 레지스트 패턴을 형성하는 단계;Forming a photoresist pattern on the hard mask layer; 상기 하드 마스크막을 패터닝하여 상기 하드 마스크막 패턴을 형성하는 단계;Patterning the hard mask layer to form the hard mask layer pattern; 상기 하드 마스크막 패턴 상부에 제 1 절연막을 형성하는 단계;Forming a first insulating film on the hard mask film pattern; 상기 하드 마스크막 패턴이 노출될 때까지 상기 제 1 절연막을 식각하여 워드라인 영역의 패턴들 사이에 개구부가 형성되는 단계;Etching the first insulating layer until the hard mask layer pattern is exposed to form openings between the patterns in the word line region; 상기 개구부에 제 2 절연막을 형성하는 단계; 및Forming a second insulating film in the opening; And 상기 잔류된 제 1 절연막을 제거하여 워드라인 형성용 마스크 패턴을 형성하는 단계를 포함하는 반도체 메모리 장치의 워드라인 형성 방법.And removing the remaining first insulating layer to form a mask pattern for forming a word line. 제 1 항에 있어서,The method of claim 1, 상기 포토 레지스트 패턴은 워드라인 영역의 최외측 패턴과 선택 트랜지스터 영역의 패턴간의 간격이 워드라인 영역의 패턴간의 간격보다 좁아지도록 하는 반도체 메모리 장치의 워드라인 형성 방법.And the photoresist pattern is such that a gap between the outermost pattern of the word line region and the pattern of the selection transistor region is smaller than the gap between the patterns of the word line region. 제 1 항에 있어서, 상기 포토 레지스트 패턴은,The method of claim 1, wherein the photoresist pattern, 제 1 선택 트랜지스터 영역 또는 제 2 선택 트랜지스터 영역 중 어느 하나의 영역 또는 모두를 확장하여 상기 하드 마스크막을 패터닝하는 반도체 메모리 장치의 워드라인 형성 방법.A method of forming a word line in a semiconductor memory device, wherein the hard mask layer is patterned by extending one or both of a first selection transistor region and a second selection transistor region. 제 2 항에 있어서, The method of claim 2, 상기 확장된 포토 레지스트 패턴과 상기 워드라인 영역의 패턴간의 간격은 최종적으로 형성되는 워드라인간의 간격과 유사하도록 형성되는 반도체 메모리 장치의 워드라인 형성 방법.And a space between the extended photoresist pattern and the pattern of the word line region is similar to a space between the finally formed word lines. 제 1 항에 있어서, The method of claim 1, 상기 워드라인 형성용 마스크 패턴을 사용하여 상기 제 2 도전막을 식각하고 워드라인을 형성하는 반도체 메모리 장치의 워드라인 형성 방법.And etching the second conductive layer and forming word lines using the word line forming mask pattern. 제 1 항에 있어서,The method of claim 1, 상기 개구부는 상기 하드 마스크 패턴의 넓은 영역에만 형성되는 반도체 메 모리 장치의 워드라인 형성 방법.And the opening is formed only in a wide area of the hard mask pattern.
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