KR20080000198A - Display device and driving method of the same - Google Patents

Abstract

A display device and a driving method thereof are provided to display additional field images of black gray scale by outputting additional data signals of the black gray scale during the invalid data interval of a frame. A display device includes a display panel(100), a data driver, and a gate driver(130). The display panel, which includes gate and data lines, displays frame images having plural fields. The data driver outputs data signals to the data lines during a valid data interval and outputs additional data signals during an invalid data interval. The gate driver outputs gate signals to the gate lines corresponding to the frame during the valid data interval and outputs gate signals to the gate lines corresponding to the field during the invalid data interval.

Description

Display device and driving method thereof {DISPLAY DEVICE AND DRIVING METHOD OF THE SAME}

1 is a plan view of a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram of the driving unit shown in FIG. 1.

3 is a detailed block diagram of the data driver illustrated in FIG. 2.

FIG. 4 is a timing diagram for describing a driving method of the data driver illustrated in FIG. 3.

<Description of the symbols for the main parts of the drawings>

STV: vertical start signal STH: horizontal start signal

TP: load signal VA: valid data interval

INVA: Invalid data section BP: Back-poch section

FP: Front porch section MAIN_DATA: Main data signal

ADD_DATA: additional data signal S_OUTPUT: analog data signal

The present invention relates to a display device and a driving method thereof, and more particularly, to a display device for improving instantaneous afterimage and a driving method thereof.

In general, a liquid crystal display includes a display panel for displaying an image including a plurality of pixel portions formed by gate lines and data lines crossing the gate lines, and a driving device for driving the display panel. The display panel includes an array substrate in which a thin film transistor is formed in a matrix form as a switching element, an opposite substrate (for example, a color filter substrate) that is opposed to the array substrate at a predetermined interval, and a liquid crystal layer interposed between the array substrate and the opposite substrate.

Unlike the cathode ray tube which displays an image in an impulse manner, the liquid crystal display displays an image in a hold manner. For this reason, when displaying a high quality video and a high quality video, an afterimage phenomenon occurs.

For example, when an afterimage phenomenon displays a screen displaying a black gradation pattern on a desktop of white gradation, and displays a screen of white gradation in the next frame, the black color displayed in the previous frame on the screen of a white gradation is displayed. It is a phenomenon that the pattern of gradation is recognized as an afterimage.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display device for removing an afterimage.

Another object of the present invention is to provide a method of driving a display device for removing an afterimage.

A display device according to an exemplary embodiment for realizing the object of the present invention includes a display panel, a data driver, and a gate driver. In the display panel, gate lines and data lines crossing the gate lines are formed to display a frame image including a plurality of fields. The data driver outputs a data signal to the data lines in the valid data section and an additional data signal to the invalid data section. The gate driver outputs a gate signal to gate wires corresponding to the frame in the valid data period, and outputs a gate signal to gate wires corresponding to the field in the invalid data period.

According to an aspect of the present invention, there is provided a method of driving a display device, the method including: displaying a frame image corresponding to a data signal on the display panel in an effective data section; And displaying an additional field image corresponding to the additional data signal on the display panel in the invalid data section.

According to such a display device and a driving method thereof, an afterimage phenomenon may be eliminated by displaying an additional field image at a predetermined number of frame images.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel 100 and a driving circuit unit 300 for driving the display panel 100.

The display panel 100 includes an array substrate 110, an opposing substrate 120 (eg, a color filter substrate) coupled to the array substrate 110, and a liquid crystal layer between the array substrate 110 and the opposing substrate 120. (Not shown). The display panel 100 is divided into a display area DA displaying a frame image composed of a plurality of fields and a peripheral area PA surrounding the display area DA, and the peripheral area PA includes data wires ( The first peripheral area PA1 is positioned at one end of the DL1 to DLm, and the second peripheral area PA2 is positioned at one end of the gate lines GL1 to GLn.

The display area DA includes a plurality of gate lines GL1 to GLn formed in one direction and a plurality of data lines DL1 to DLm formed in a direction crossing the gate lines GL1 to GLn. Pixel portions are formed. Each pixel unit includes a thin film transistor TFT connected to the gate line GL and the data line DL, a liquid crystal capacitor CLC and a storage capacitor CST electrically connected to the thin film transistor TFT.

The driving circuit unit 300 includes a driving unit 200, a gate driving unit 130, and a flexible printed circuit board 140.

The driver 200 is formed as a single chip and is mounted in the first peripheral area PA1 to provide a gate control signal to the gate driver 130, and output a data signal to the data lines DL1 to DLm. . Here, the data signal output to the data lines DL1 to DLm includes a data signal corresponding to a raw data signal provided from an external device and an additional data signal generated by the driver 200. The additional data signal generated by the driver 200 is a data signal of black gray or gray gray.

The gate driver 130 is formed in the second peripheral area PA2 positioned at one end of the gate lines GL1 to GLn, and is connected to the data signal and the additional data signal output from the driver 200 to form the gate wiring. Outputs a gate signal to the fields GL1 to GLn. That is, the gate lines GL1 to GLn are activated in association with the output of the data signal and the additional data signal.

One end of the flexible printed circuit board 140 is attached to the first peripheral area PA1 to electrically connect the external device to the driving unit 200. That is, the flexible printed circuit board 140 transmits raw data signals and synchronization signals provided from an external device to the driver.

FIG. 2 is a detailed block diagram of the driving unit shown in FIG. 1.

1 and 2, the driver 200 includes a controller 210, a data driver 270, a gate controller 290, a memory 230, and a voltage generator 250. Meanwhile, the gate driver 310 is interlocked with the data driver 270 to output a gate signal.

The controller 210 receives the raw data signal 200a and the synchronization signals 200b from an external device, and the received synchronization signals 200b include the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the main clock. The signal MCLK and the data enable signal DE are included. The control unit 210 writes and reads the raw data signal 200a to the memory 230 based on the received synchronization signals 200b, and the data corresponding to the raw data signal 200a read from the memory 230. The signal 210a and the first control signal 210d are output to the data driver 270. The data signal 210a output from the controller 210 to the data driver 270 is a digital signal 210a.

In addition, the controller 210 outputs the second control signal 210b to the voltage generator 250 and outputs the third control signal 210c to the gate controller 290. The third control signal 210c includes a vertical start signal STV, a first clock signal CK1, and a second clock signal CK2 for controlling the operation of the gate driver 290, and the first clock signal CK1. ) And the second clock signal CK2 are signals of opposite phases to each other.

The memory 230 stores the raw data signal 200a provided from the controller 210 in a predetermined unit. For example, the memory 230 stores the raw data signal 200a in units of frames, fields, or lines.

The voltage generator 250 generates driving voltages including a gamma reference voltage 250a, a gate voltage 250b, and a common voltage 250c by using an external power source. Here, the generated gamma reference voltage 250a is applied to the data driver 270, the gate voltage 250b is applied to the gate controller 290 including the gate on voltage and the gate off voltage, and the common voltage 250c. Is applied to a common electrode (not shown) of the liquid crystal capacitor CLC.

The data driver 270 uses the digital data signal 210a as a gamma reference voltage 250a based on the first control signal 210d provided from the controller 210 to output an analog data signal (eg, a data voltage). ) Is output to the data lines DL1 to DLm.

In detail, the first control signal 210d provided to the data driver 270 includes a horizontal start signal STH, a load signal TP, and an inversion signal POL. The data driver 270 outputs a data signal 210a corresponding to each frame in the valid data period based on the first control signal 210d and outputs an additional data signal of black gradation generated by the data driver 270. Output to invalid data section.

The additional data signal of the black gray level is output in a j (j is a natural number) frame period, and the invalid data section includes a back porch section of a preceding frame and a front porch section of a subsequent frame. . In general, one frame section includes a front-porch section, a valid data section, and a back-porch section. The valid data section is a section in which an image is displayed on the display panel 100, and the front-porch and back-porch sections are defined as blanking sections in which an image is not displayed as an invalid data section.

For example, the data driver 270 converts the data signal 210a provided from the controller 210 into an analog form in the effective data section of each frame, and outputs the data signal to the data lines DL1 to DLm in the 120th frame. The black gray level additional data signal generated by the data driver 270 is output to the data lines DL1 to DLm in the back-porch section and the front-porch section of the 121th frame. Next, an additional data signal of black gradation is output to the data lines DL1 to DLm in the back-porch section of the 240th frame and the front-porch section of the 241th frame. As such, the data driver 270 independently outputs an additional data signal having a black gray level at 120 or 240 frame periods, thereby improving an afterimage phenomenon.

The gate controller 290 outputs the third control signal 210c provided from the controller 210 and the gate voltage 290b provided from the power generator 250 to the gate driver 310. Here, the third control signal 210c includes a vertical start signal STV and a first clock signal CK1 and a second clock signal CK2 that are out of phase with each other, and the gate voltage 290b is gated on. Voltage and gate-off voltage.

Meanwhile, the gate driver 310, which receives the third control signal 290a and the gate voltage 290b from the gate controller 290, is interlocked with the data driver 270 based on the third control signal 290a to connect the gate wirings. Gate signals are output to the fields GL1 to GLn.

In detail, the data driver 270 outputs the gate signal to the gate lines corresponding to the frame in the valid data section for outputting the data signal, thereby activating the gate lines corresponding to the frame. In addition, the data driver 270 outputs a gate signal to the gate lines corresponding to the field in the invalid data section for outputting the additional data signal of the black gray level, thereby activating the gate lines corresponding to the field, and outputting the additional data signal. The gate signal is output so that a plurality of fields constituting the frame are sequentially driven in a j frame period.

For example, when the frame image is composed of four fields, the gate driver 290 outputs a gate signal to the first to n-th gate lines GL1 to GLn corresponding to the frame in the valid data section of each frame. The gate signal is output to the first to nth / 4 gate lines GL1 to GLn / 4 which are the first field in the invalid data section including the back-porch section of the first frame and the front-porch section of the 121th frame. The second field n / 4 + 1 to n / 2 gate wirings GLn / 4 + 1 to GLn in the invalid data section including the back-porch section of the next 240 th frame and the front-porch section of the 241 th frame. / 2) outputs a gate signal. As such, the gate driver 290 outputs a gate signal such that a plurality of fields are sequentially driven at 120 or 240 frame periods.

3 is a detailed block diagram of the data driver illustrated in FIG. 2, and FIG. 4 is a timing diagram for describing a driving method of the data driver illustrated in FIG. 3.

2 and 3, the data driver 270 includes a latch unit 271, an additional data generator 272, an additional data controller 273, a digital / analog converter 274, and a buffer unit 275. It includes.

The latch unit 271 latches the data signal 210a provided by the controller 210 in units of lines, and outputs the latched line unit data signal 210a to the digital / analog converter 274.

The additional data generator 272 generates an additional data signal having a digital gray scale, and outputs the generated additional data signal to the digital / analog converter 274 under the control of the additional data controller 273.

The additional data controller 273 controls the additional data generator 272 to adjust an output period of the additional data signal. That is, the additional data generator 272 is controlled to output the digital data to the digital / analog converter 274 in the invalid data section in the j frame period.

The digital / analog converter 274 converts the digital data signal 210a and the additional data signal provided by the latch unit 271 by using the gamma reference voltage 250a to correspond to the analog data signal and the additional data signal. Are converted to the buffer unit 275 and output to the buffer unit 275.

The buffer unit 275 buffers an analog data signal and an additional data signal provided from the digital / analog converter 274 and outputs the buffered data to the data lines DL1 to DLm.

As described above, the driving method of the data driver 270 will be briefly described with reference to FIG. 4, and the data driver 270 may generate a data signal in the valid data section VA of each frame based on the first control signal 210d. (MAIN_DATA) is output, and the additional data signal ADD_DATA of black gradation is output in the invalid data section INVA in the j frame period.

Specifically, in each valid data section VA of the j th frame and the j + 1 th frame, the latch unit 271 performs digital / analog conversion of the digital data signal MAIN_DATA latched in response to the load signal TP. Output to the unit 274. The digital / analog converter 274 converts the input digital data signal MAIN_DATA into an analog form and outputs it to the buffer unit 275, and the buffer unit 275 receives the input analog data signal S_OUTPUT. Is buffered and output to the data lines DL1 to DLm.

In the invalid data section INVA between the j th frame and the j + 1 th frame, the additional data controller 273 converts the digital additional data signal ADD_DATA to the digital / analog converter based on the first control signal 210a. The additional data generator 272 is controlled to output to 274. Here, the invalid data section INVA between the j th frame and the j + 1 th frame includes a back-porch section BP of the j th frame and a front-porch section FP of the j + 1 th frame.

The digital / analog converter 274 converts the received additional data signal ADD_DATA into an analog form and outputs it to the buffer unit 275, and the buffer unit 275 outputs the analog additional data signal S_OUTPUT. Is buffered and output to the data lines DL1 to DLm. Here, the level of the additional data signal ADD_DATA is applied differently according to the operation mode of the display panel. For example, in the case of the normally black mode, the level of the additional data signal ADD_DATA is close to the common voltage level.

In the above-described data driver 270, the additional data generator 272 generates the additional data signal ADD_DATA in digital form, and converts the additional data signal ADD_DATA to the additional data signal S_OUTPUT in analog form in the digital / analog converter 274. Afterwards, a method of buffering and outputting the buffer 275 has been described. However, the additional data generator 272 generates the analog additional data signal S_OUTPUT and performs the buffer without passing through the digital / analog converter 274. It can also be formed by a method of directly outputting to the unit (275).

As such, the display panel sequentially displays additional field images having black gradations between the main frame images at j frame periods, thereby eliminating an afterimage phenomenon.

As described above, according to the present invention, an afterimage phenomenon may be eliminated by outputting a black gray additional data signal in an invalid data section of a frame at a predetermined frame period by the data driver. In addition, since the afterimage phenomenon may be removed only by changing the data driver, the design of the display device may be simplified.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (10)

A display panel on which gate lines and data lines intersecting the gate lines are formed to display a frame image including a plurality of fields; A data driver for outputting a data signal to the data lines in the valid data section and an additional data signal to the invalid data section; And And a gate driver configured to output a gate signal to gate lines corresponding to the frame in the valid data period, and to output a gate signal to gate lines corresponding to the field in the invalid data period. The display device of claim 1, wherein the additional data signal is a black gray data signal. The display device of claim 1, wherein the additional data signal is output in a j (j is a natural number) frame period. The display device of claim 1, wherein the gate driver outputs the gate signal such that the plurality of fields are sequentially driven at the j frame period. The data driver of claim 3, wherein the data driver An additional data generator for generating an additional data signal in a digital form; An additional data controller configured to control the additional data generator to output the digital data in the j frame period; A digital / analog converter for converting the digital data signal and the additional data signal into a corresponding analog form; And And a buffer unit configured to buffer and output the analog data signal and the additional data signal. The data driver of claim 3, wherein the data driver An additional data generator for generating an additional data signal in an analog form; An additional data controller configured to control the additional data generator to output the analog data signal in an invalid data section in the j frame period; And A digital / analog converter for converting a digital data signal into the analog data signal; And And a buffer unit configured to buffer and output the analog data signal and the additional data signal. The display device of claim 1, wherein the invalid data section comprises a back-porch section of a preceding frame and a front-porch section of a subsequent frame. A driving method of a display device having a display panel for displaying a frame image divided into a plurality of fields, the method comprising: Displaying a frame image corresponding to a data signal on the display panel in an effective data section; And And displaying an additional field image corresponding to an additional data signal on the display panel in an invalid data section. The method of claim 8, wherein the displaying of the additional field image is performed by displaying j (j is a natural number) frame images periodically. The method of claim 9, wherein displaying the additional field image comprises: And displaying additional field images corresponding to the plurality of fields sequentially at intervals of the j frame images.

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