KR20070121337A - Liquid crystal display and method of operating the same - Google Patents

Abstract

A liquid crystal display and a method for operating the same are provided to control a variable resistor with a timing controller by using a resistance stored in a memory device. A liquid crystal display panel(100) a plurality of gate lines, a plurality of data lines crossing the gate lines, a plurality of thin film transistors connected to the gate lines and the data lines, and a plurality of pixels having a plurality of capacitors connected to the thin film transistors. A driving circuit applies a gray scale voltage to the data lines according to an image signal and applies a driving voltage for driving the thin film transistors to the gate lines. The driving circuit controls the driving voltage according to pixels and applies the controlled driving voltage. The driving circuit includes a driving voltage control unit for controlling the driving voltage.

Description

Liquid crystal display and method of driving the same {Liquid crystal display and method of operating the same}

1 is a characteristic graph of a thin film transistor used to explain a problem of a conventional liquid crystal display.

2 is an equivalent circuit diagram of a thin film transistor for applying the principles of the present invention.

3 is a characteristic graph of a thin film transistor for explaining the principle to which the present invention is applied;

4 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a circuit diagram of a gate-on voltage generator of a liquid crystal display according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: liquid crystal panel 200: gate driver

300: data driver 400: timing controller

500: driving voltage generator 600: memory element

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly, to a liquid crystal display and a driving method thereof capable of controlling a gate-on voltage of a thin film transistor (TFT).

In a liquid crystal display device using a thin film transistor as a switching element, a display that obtains a desired image signal by applying an electric field to a liquid crystal material injected between two substrates, and controlling the amount of light transmitted through the substrate by adjusting the intensity of the electric field. Device.

Such TFT-LCDs generally include a plurality of gate lines that transmit scan signals and data lines that cross the gate lines and transmit image data, and are formed in regions surrounded by these gate lines and data lines, respectively. It includes a plurality of pixels in the form of a matrix connected through a gate line and a data line and a thin film transistor. In addition, one pixel is connected to the gate line and the source line, respectively, and includes a thin film transistor, a liquid crystal capacitor, and a storage capacitor. The gate of the thin film transistor is connected to the gate driver through a gate line, and the source is connected to the source driver through a source line.

When the thin film transistor is turned on in response to a signal input from the gate driver, the data voltage input from the data driver through the source line is charged to the liquid crystal capacitor and the storage capacitor. Then, when the thin film transistor is turned off, the charges charged in the liquid crystal capacitor and the storage capacitor are maintained for one frame. The storage capacitor serves to store the charge by assisting the liquid crystal capacitor because it is difficult to maintain the charged charge for one frame alone.

As described above, in the TFT-LCD, the turn-on / turn-off of the thin film transistor is repeated, and a desired applied voltage is transmitted to the liquid crystal capacitor and the storage capacitor to express a color image.

However, referring to FIG. 1, which shows the characteristics of the drain current Id according to the gate voltage Vg as a characteristic graph of the thin film transistor, even if the same gate voltage Vg is applied, the drain current Id according to the region of the panel is shown. There may be different areas. That is, among the plurality of thin film transistors constituting the panel, there may be a thin film transistor having a different drain current Id. The difference in the drain current Id indicates that the drain voltage Vd is different. This is because there is a variation depending on the region due to the characteristics of the manufacturing process of the thin film transistor, the liquid crystal capacitor and the storage capacitor. As a result, the filling rate of the liquid crystal capacitor or the storage capacitor is different for each region. Since the filling rate is different depending on the area of the panel as described above, the image quality is degraded, such as staining on the screen.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a method of driving the same, which can solve a problem such as unevenness caused because the filling rate of the capacitor is different depending on the area of the panel.

Another object of the present invention is to provide a liquid crystal display and a method of driving the same, by adjusting the gate-on voltage of the thin film transistor to increase the drain current of the thin film transistor and thereby increase the charge rate of the capacitor.

The liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of gate lines and a plurality of data lines crossing each other, a plurality of thin film transistors connected to the plurality of gate lines and the plurality of data lines, and a plurality of capacitors connected thereto. A liquid crystal panel comprising a plurality of pixels having; And a driving circuit generating and applying a gray voltage according to an image signal to the data line, and generating and applying a driving voltage for driving the thin film transistor to the gate line, wherein the driving voltage is adjusted and applied according to the pixel. It includes.

The driving circuit includes a driving voltage adjusting means, and the driving voltage is adjusted by the driving voltage adjusting means.

The driving circuit may include a driving voltage generator configured to generate the driving voltage and include driving voltage adjusting means and to adjust and output the driving voltage by the driving voltage adjusting means; A timing controller for determining an output timing of the image signal and controlling the driving voltage generator and the driving voltage adjusting means to adjust the driving voltage; And a memory element for storing modifiable adjustment information of the driving voltage adjusting means.

The driving voltage generator includes a power supply unit for generating and supplying a power voltage according to an input voltage; Pumping means for pumping the power supply voltage; Delivery means for delivering said pumping voltage to an output terminal; And driving voltage adjusting means for adjusting the pumping voltage to output the driving voltage.

The adjustment information of the driving voltage adjusting means is stored in the memory element in an I 2 C manner from a host.

The driving voltage adjusting means includes a variable resistor.

In addition, the driving method of the liquid crystal display according to an exemplary embodiment of the present invention may include: (a) displaying an image on the liquid crystal panel by applying a predetermined driving voltage and a predetermined gray scale voltage; (b) detecting pixels in which the spot is visible in the liquid crystal panel; And (c) removing the spot by adjusting and applying the driving voltage to the gate line of the pixel where the spot is visible.

Step (c) includes adjusting and storing a resistance value; Adjusting the variable resistance of the driving voltage generator by using the adjusted resistance value, thereby adjusting the driving voltage; And applying the adjusted driving voltage to the gate line of the pixel in which the spot is visible.

The adjusted resistance value is stored in the memory device in I2C manner from the host.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is an equivalent circuit diagram of a thin film transistor for explaining the principle of the present invention. Here, the drain voltage Vd is a value obtained by subtracting the product of the resistor Rd and the drain current Id from the power supply voltage VDD. That is, the drain voltage Vd is calculated as Vd = V _DD- (Id x Rd). Accordingly, the drain current Id is calculated as Id = (V _DD- Vd) / Rd.

When the drain current Id is applied to a characteristic curve showing the relationship between the drain voltage and the drain current according to the gate voltage of the thin film transistor of FIG. 3, the drain voltage and the drain current are A, B and C depending on the area of the panel. They become different as points. To make them the same, the gate voltage Vg must be raised. In other words, when the gate voltage is increased, the drain current at point A or point B rises to point C. In this way, when the gate voltage of the thin film transistor is increased, the drain voltage and the drain current can be increased, so that the charge rate of the capacitor can be kept constant, thereby preventing the occurrence of spots.

In the present invention, by using this principle to detect the spotted pixels after the manufacturing process, and to increase the gate voltage of the thin film transistor selectively to the spotted pixels to improve the charge rate of the capacitor to heal the spots before the package .

In order to increase the gate voltage of the thin film transistor, it is necessary to adjust the gate-on voltage. An embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a configuration diagram of a liquid crystal display including a liquid crystal panel and a driving circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the liquid crystal display according to the exemplary embodiment may include a liquid crystal panel 100, a gate driver 200, a data driver 300, a timing controller 400, a driving voltage generator 500, and the like. Memory device 600.

The liquid crystal panel 100 is formed in a row and column direction, respectively, and includes a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm, a plurality of gate lines G1 to Gn, and a plurality of gate lines. A thin film transistor T connected to the data lines D1 to Dm and a plurality of pixels connected to the plurality of thin film transistors T are included. The plurality of pixels may use one pixel or three pixels corresponding to R (Red), G (Green), and B (Blue), respectively. Each pixel includes a thin film transistor T, a pixel electrode (not shown), a liquid crystal capacitor Clc, and a storage capacitor connected to a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm. Cst). The plurality of gate lines G1 to Gn formed in the row direction transmit a gate signal to the thin film transistor T, and the plurality of data lines D1 to Dm formed in the column direction are connected to the thin film transistor T. The gray voltage corresponding to the data signal is transmitted. In addition, the gate terminal of the thin film transistor T is connected to the gate lines G1 to Gn, the source terminal is connected to the data lines D1 to Dm, and the drain terminal is connected to the pixel electrode (not shown). have. The liquid crystal capacitor Clc is formed by a liquid crystal formed between a pixel electrode (not shown) and a common electrode (not shown) connected to the drain terminal of the thin film transistor T, and the storage capacitor Cst is formed of the thin film transistor T. The gate electrode may be formed between the storage electrode formed on the other end of the substrate and the common electrode (independent wiring method) or may be formed between the storage electrode and the gate lines G1 to Gn directly above (shear gate method).

The gate driver 200 is connected to a plurality of gate lines G1 to Gn, and the timing controller 400 controls the gate on voltage Von and the gate off voltage Voff provided from the driving voltage generator 500. A plurality of gate lines G1 to Gn are provided according to a control signal from the same.

The data driver 300 is connected to a plurality of data lines D1 to Dm, and generates corresponding gray voltages according to the image signals R, G, and B provided from the timing controller 400, respectively. It is provided by the lines D1-Dm.

The timing controller 400 inputs external image signals R, G, and B from an external host to determine the output timing of the image signals R, G, and B, and supplies them to the data driver 300. do. The timing controller 400 inputs a plurality of control signals for controlling the driving of the gate driver 200 to the gate driver 200, for example, a first control signal for enabling the gate driver 200. The gate driver 200 supplies a second control signal lamp for sequentially applying the gate-on voltage Von to each gate line. In addition, the timing controller 400 provides a plurality of control signals for controlling the output of the gate on voltage Von and the gate off voltage Voff to the driving voltage generator 500. In particular, the timing controller 400 inputs a control signal for adjusting the variable resistor included in the driving voltage generator 500 to the driving voltage generator 500 by using the resistance data stored in the memory device 600.

The driving voltage generator 500 generates a gate on voltage Von and a gate off voltage Voff. To this end, the driving voltage generator may include a power supply for generating a predetermined voltage, a gate-on voltage generator for generating a gate-on voltage using a voltage supplied from the power supply, and a gate-off voltage using a voltage supplied from the power supply. It comprises a gate off voltage generator for generating a. However, since the present invention relates to the generation of the gate-on voltage Von, only the gate-on voltage generation unit will be discussed. The driving voltage generator 500 includes a means for adjusting the gate-on voltage to adjust and output the gate-on voltage Von according to the control signal of the timing controller 400, which is preferably a variable resistor. It is configured using. That is, the driving voltage generator 500 includes a variable resistor, and the resistance thereof is adjusted according to a control signal from the timing controller 400 to change and output the gate-on voltage Von.

The memory device 600 stores various information of the LCD panel 100 and stores resistance data input from the outside through the serial data bus SDA in an I2C manner. By using such a memory device 600, the contents of the memory device 600 can be easily changed or replaced, and even if the liquid crystal panel is changed, it is possible to respond to panel changes by storing or changing information on the changed liquid crystal panel. Here, various memory storage devices may be used as the memory device 450. For example, a memory storage element such as a ROM or an electric erasable and programmable read-only memory (EEPROM) may be used as the memory element 450.

In the liquid crystal display according to the exemplary embodiment configured as described above, the timing controller 400 adjusts the variable resistance of the driving voltage generator 500 according to the resistance data stored in the memory device 600 so that the gate-on voltage ( Von) to be adjusted. For example, when a stain occurs due to a difference in charge rate in a predetermined pixel, the gate-on voltage Von must be increased to be applied. To this end, the resistance data is modified and stored in the memory device 600, and the timing controller 400 adjusts the variable resistance of the driving voltage generator 500 according to the modified resistance data. As a result, the gate-on voltage Von is increased to be applied to the thin film transistor of the pixel in which the spot is generated through the gate driver 200 to heal spots.

5 is a partial circuit diagram of a gate-on voltage generator of a driving voltage generator of a liquid crystal display according to an exemplary embodiment of the present invention. The driving voltage generator includes a power supply, a gate-on voltage generator, and a gate-off voltage generator. Here, only the gate-on voltage generator will be described.

Referring to FIG. 5, a first resistor R21, a first diode and a second diode between an analog power supply AVDD terminal and an emitter terminal of a bipolar junction transistor T21 (for convenience, referred to as a first node Q21). D21 and D22 are connected in series. Here, the analog power source AVDD is a power source having a predetermined voltage by boosting a predetermined input voltage Vin by a power supply unit (not shown). A first capacitor C21 charged by a clock LX generated from a power supply unit (not shown) is connected between the first and second diodes D21 and D22. The third capacitor C23 is connected between the first node Q21 and the ground terminal, and the second capacitor C22 and the second terminal are connected between the first node Q21 and the base terminal of the bipolar junction transistor T21. The resistor R22 is connected in parallel. In addition, a control signal DRVP for driving the bipolar junction transistor T21 is input from a power supply unit (not shown) to the base terminal of the bipolar junction transistor T21.

The third and fourth resistors R23 and R24 are connected in series between the collector terminal of the bipolar junction transistor T21 (referred to as the second node Q22) and the ground terminal, and the third and fourth resistors R23 are connected in series. And a voltage between R24 is input to a feedback terminal FBP of a power supply unit (not shown). In addition, the third and fourth resistors R23 and R24 are constituted by variable resistors and, as described above, are adjusted by the timing controller according to values stored in the memory device.

The fifth resistor R25 is connected in series between the second node Q22 and the output terminal at which the gate-on voltage Von is output, and the fourth and fifth capacitors C24 are connected between the second node Q22 and the ground terminal. And C25) and the fifth resistor R25 are connected in parallel.

Referring to the driving method of the gate-on voltage generator according to an embodiment of the present invention configured as described above are as follows.

While the analog power supply voltage AVDD is supplied to the first node Q21, the first capacitor C21 is charged by the clock signal LX. Therefore, the first node Q21 is charged with the analog power supply voltage AVDD and the first power supply. The pumping voltage obtained by adding up the voltage charged to one capacitor C21 is supplied. In addition, the second capacitor C22 is charged while the bipolar junction transistor T21 is turned on according to the control signal DRVP. Therefore, the second node Q22 is supplied with a pumping voltage obtained by adding the analog power supply voltage AVDD and the voltages charged to the first and second capacitors C21 and C22 from the first node Q21.

However, the voltage supplied to the second node Q22 is distributed by the third and fourth resistors R23 and R24 and output to the output terminal Von. Therefore, the voltage output to the output terminal Von may be adjusted according to the resistance values of the third and fourth resistors R23 and R24. On the other hand, the voltage between the third and fourth resistors R23 and R24 is input to the feedback terminal FBP of the power supply unit (not shown) and used when generating power of the power supply unit (not shown).

[Table 1] shows the amount of spots that are visible in the panel when the gate-on voltage Von is changed and applied, and the higher the gate-on voltage Von, the less the amount of spots that are visible.

Von #One #2 # 3 #4 # 5 20 V 250 201 209 251 215 25 V 188 75 125 157 116 30 V 40 36 51 82 105

As described above, according to the present invention, a variable resistor is installed to adjust the gate-on voltage of the driving voltage generator, and the variable resistor is adjusted by the timing controller using the resistance value stored in the memory device in the I2C method. This makes it possible to detect the spotted pixels after the manufacturing process and to selectively increase the gate voltage of the thin film transistor with respect to the spotted pixels, thereby improving the charge rate of the capacitor, thereby preventing the spots from occurring before the package.

Claims (9)

A liquid crystal panel including a plurality of pixels having a plurality of gate lines and a plurality of data lines crossing each other, a plurality of thin film transistors connected to the plurality of gate lines and the plurality of data lines, and a plurality of capacitors connected thereto; And A driving circuit for generating and applying a gray voltage according to an image signal to the data line, and generating and applying a driving voltage for driving the thin film transistor to the gate line, and adjusting and applying the driving voltage according to the pixel. Liquid crystal display device comprising. The liquid crystal display of claim 1, wherein the driving circuit comprises driving voltage adjusting means, and the driving voltage is adjusted by the driving voltage adjusting means. The method of claim 1, wherein the driving circuit, A driving voltage generating unit configured to generate the driving voltage and include driving voltage adjusting means, and to adjust and output the driving voltage by the driving voltage adjusting means; A timing controller for determining an output timing of the image signal and controlling the driving voltage generator and the driving voltage adjusting means to adjust the driving voltage; And And a memory element for storing modifiable adjustment information of the driving voltage adjusting means. The method of claim 3, wherein the driving voltage generator, A power supply unit for generating and supplying a power supply voltage according to an input voltage; Pumping means for pumping the power supply voltage; Delivery means for delivering said pumping voltage to an output terminal; And And a driving voltage adjusting means for adjusting the pumping voltage to output the driving voltage. The liquid crystal display device according to claim 2, 3 or 4, wherein the adjustment information of the driving voltage adjusting means is stored in the memory element in an I2C manner from a host. The liquid crystal display device according to claim 2, wherein the driving voltage adjusting means comprises a variable resistor. In the driving method of a liquid crystal display device, (a) displaying an image on the liquid crystal panel by applying a predetermined driving voltage and a predetermined gray scale voltage; (b) detecting pixels in which the spot is visible in the liquid crystal panel; And and (c) removing the spot by adjusting and applying the driving voltage to the gate line of the pixel where the spot is visible. The method of claim 7, wherein step (c) is Adjusting and storing the resistance value; Adjusting the variable resistance of the driving voltage generator by using the adjusted resistance value, thereby adjusting the driving voltage; And And applying the adjusted driving voltage to a gate line of the pixel where the spot is visible. The method of claim 8, wherein the adjusted resistance value is stored in a memory device in an I 2 C manner from a host.

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