KR20070111667A - Method of manufacturing the semiconductor memory device using asymmetric junction ion implantation - Google Patents

Abstract

A method for fabricating a semiconductor memory device using asymmetrical junction ion implantation is provided to improve a refresh characteristic by increasing asymmetry with a storage node junction. An ion implantation process for adjusting a threshold voltage is performed on a semiconductor substrate(100) by using impurity ions of a first conductivity type. A gate stack(150) is formed on the resultant semiconductor substrate to define a storage node junction region(122) and a bitline junction region(123). An asymmetrical junction ion implantation process is performed by using impurity ions of a second conductivity type by using a mask layer pattern(170) which covers the bitline junction region and exposes the storage node junction region. A gate spacer layer is formed on the lateral surface of the gate stack. By using the gate stack and the gate spacer layer as an ion implantation mask layer, impurity ions of the second conductivity type are implanted to form a storage node junction and a bitline junction that have different impurity densities and junction depths. The asymmetrical junction ion implantation process can be performed after the gate spacer layer is formed.

Description

Method of manufacturing the semiconductor memory device using asymmetric junction ion implantation}

1 to 3 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the present invention.

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a semiconductor memory device using asymmetric junction ion implantation.

In recent years, as the degree of integration of semiconductor devices increases rapidly, the channel length of the transistors constituting the devices also decreases rapidly. As the channel length is shortened, various problems caused by the short channel effect are deteriorating the operation characteristics of the device. As an example, as the channel length becomes shorter, the strength of the electric field near the drain region is increased, and hot carriers are generated by the increased electric field, resulting in poor operation characteristics and stability of the device. As another example, in the case of a semiconductor memory device such as a dynamic random access memory (DRAM), a leakage current occurs as an electric field intensity increases in a cell region, and the leakage current causes a refresh of the device. ) Make the characteristics poor.

Recently, in order to suppress such a short channel effect, techniques for increasing the effective channel length without reducing the density of devices have been proposed. As an example, there are a recess channel structure and a step gate asymmetric recess structure. . In the case of the recess channel structure, after forming a trench in the substrate, a gate stack is formed by filling the trench with a gate conductive film. In this recess channel structure, channels are formed along the trench circumference, thereby increasing the effective channel length. In addition, in the case of the step gate asymmetric recess structure, a stepped profile is formed in the substrate, and a gate stack is formed in the stepped profile so that both sides of the gate stack are asymmetrically disposed. Even in this step-gate asymmetric recess structure, the channel is formed along the stepped profile, thereby increasing the effective channel length.

In parallel with the adoption of such a three-dimensional cell structure, attempts have been made to improve the refresh characteristics by varying the impurity concentrations of the storage node junction region and the bit line junction region. That is, after the gate stack is formed, an asymmetric threshold voltage ion is implanted into the bit line contact region using a mask layer pattern exposing only the bit line contact region to implant the p-type impurity ion. After the mask layer pattern is removed, a gate spacer layer is formed, and then source / drain junction ion implantation is performed using a conventional method, and the impurity concentration in the channel region near the storage node junction region is near the bit line junction region. It is lower than the impurity concentration in the channel region of the, thereby reducing the leakage current can improve the refresh characteristics of the device.

However, as attempts for high integration of less than 100nm have been made, more refresh characteristics have to be secured, and data retention time is also required. However, current asymmetric threshold voltage implantation alone has shown a limit in meeting such demands.

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a semiconductor memory device capable of causing an asymmetric concentration difference between a storage node junction region and a bit line junction region to improve refresh characteristics and extend data retention time. To provide.

In order to achieve the above technical problem, a method of manufacturing a semiconductor memory device according to the present invention comprises the steps of: performing ion implantation for adjusting the threshold voltage to the impurity ion of the first conductivity type on the semiconductor substrate; Forming a gate stack on the ion implanted semiconductor substrate to define a storage node junction region and a bit line junction region; Performing asymmetric junction ion implantation with impurity ions of a second conductivity type using a mask layer pattern covering the bit line junction region and exposing the storage node junction region; Forming a gate spacer layer on a side of the gate stack; And forming a storage node junction and a bit line junction having different impurity concentrations and junction depths by implanting impurity ions of a second conductivity type into the gate stack and the gate spacer layer using an ion implantation mask layer. do.

It is preferable that it is p type of a said 1st conductivity type, and said 2nd conductivity type is n type.

The asymmetric junction ion implantation may be performed after the gate spacer layer is formed.

The asymmetric junction ion implantation may be performed such that ion implantation is performed at a dose of 10-30% of the final concentration of the storage node junction.

Injecting the impurity ions of the second conductivity type for forming the storage node junction and the bit line junction may include implanting the impurity ions at a concentration of 90-70% of the final impurity concentration of the bit line junction and the storage node junction. It is preferable to carry out.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

1 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the present invention.

First, referring to FIG. 1, an isolation layer 110 is formed on a semiconductor substrate 100 to define an active region 120. Although not shown in the drawing, a trench for a recess channel may be formed in the active region 120. Alternatively, the surface of the active region 120 may have a stepped profile. Next, a buffer insulating layer 130 is formed as an oxide layer on the semiconductor substrate 100 where the active region 120 is defined. Subsequently, as shown by arrows in the figure, channel threshold voltage ion implantation is performed on the front surface. In this embodiment, a case having an n-type channel is taken as an example. Therefore, p-type impurity ions are implanted into the upper portion of the semiconductor substrate 100 by channel threshold voltage implantation. The concentration of the implanted p-type impurity ions is 100% of the total channel concentration.

Next, referring to FIG. 2, a gate stack 150 is formed on the semiconductor substrate 100 through the gate insulating layer 140. Although not shown in the drawing, when there is a trench for the recess channel, the gate stack 150 is formed to fill the recess channel trench. And if there is a stepped profile, the gate stack 150 is formed to overlap the stepped profile. The gate stack 150 is generally formed in a structure in which a polysilicon film, a tungsten silicide film, and a nitride film are sequentially stacked, but is not necessarily limited thereto. As the gate insulating layer 140 and the gate stack 150 are formed, the active region 120 of the semiconductor substrate 100 includes the channel region 121 overlapping the gate insulating layer 140 and the storage node junction region 122. ) And the bit line junction region 123.

Next, after forming the liner oxide film 160 on the entire surface, a mask film pattern 170 for asymmetric junction ion implantation is formed. The mask film pattern 170 may be formed of a photoresist film, and may have an opening 171 covering the bit line junction region 123 and exposing only the storage node junction region 122. Next, as indicated by an arrow in the figure, an asymmetric junction ion implantation using the mask layer pattern 170 as an ion implantation mask is performed to implant n-type impurity ions into the storage node junction region 122. The concentration of the implanted n-type impurity ion is about 10-30% of the final concentration of the storage node junction region 122.

Next, referring to FIG. 3, the asymmetric threshold voltage ion implantation for the existing bit line junction region 123 is omitted, and the mask layer pattern 170 of FIG. 2 is removed. The gate spacer layer 180 is formed on the sidewall of the gate stack 140. The gate spacer film 180 may be formed of a nitride film. Next, as indicated by arrows in the drawing, junction formation ion implantation using the gate stack 140 and the gate spacer layer 180 as an ion implantation mask is performed to implant n-type impurity ions into the semiconductor substrate 100. As the n-type impurity ion, phosphorus (P), arsenide (As), antimony (Sb), bismuth (Bi) and the like can be used. The concentration of the implanted n-type impurity ions is about 90-70% of the final concentration of the storage node junction region 122 and the bit line junction region 123. By the junction formation ion implantation, the storage node junction 191 and the bit line junction 192 are formed in the semiconductor substrate 100. Here, the total channel concentration gradient of the storage node junction 191 is 100%, and the total junction concentration gradient is also 100%. On the other hand, the overall channel concentration gradient of the bit line junction 192 is 100%, but the overall junction concentration gradient is 90-70%.

Meanwhile, before forming the gate spacer layer 180, a relatively low concentration of n-type impurity ions may be implanted to form a lightly doped drain (LDD) structure. Asymmetric channel ion implantation of p-type impurity ions and asymmetric junction ion implantation of n-type impurity ions may be continuously performed using a mask layer pattern exposing only the storage node junction region 122 after the gate spacer layer 180 is formed. have.

As described so far, according to the method of manufacturing a semiconductor memory device using the asymmetric junction ion implantation according to the present invention, the electric field applied by forming the concentration of the bit line junction to about 90-70% compared with the conventional case is formed. In addition, the refresh characteristics can be improved by increasing asymmetry with the storage node junction. Furthermore, since there is no change in the concentration of the storage node junction, the refresh characteristics can be further improved by improving the breakdown voltage of the storage node junction while adjusting the threshold voltage at the same time as the read. As an example, when the breakdown voltage of the storage node junction is improved by about 0.2V, the refresh is improved by about 40-50mV, and thus an additional refresh characteristic of about 10% can be obtained.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (5)

Performing ion implantation of a threshold voltage into the semiconductor substrate with impurity ions of a first conductivity type; Forming a gate stack on the ion implanted semiconductor substrate to define a storage node junction region and a bit line junction region; Performing asymmetric junction ion implantation with impurity ions of a second conductivity type using a mask layer pattern covering the bit line junction region and exposing the storage node junction region; Forming a gate spacer layer on a side of the gate stack; And Implanting impurity ions of a second conductivity type into the gate stack and gate spacer layers into an ion implantation mask layer to form storage node junctions and bit line junctions having different impurity concentrations and junction depths; Method of manufacturing a memory device. The method of claim 1, And p-type of the first conductivity type and n-type of the second conductivity type. The method of claim 1, And performing the asymmetric junction ion implantation after the gate spacer film is formed. The method of claim 1, The performing of the asymmetric junction ion implantation is performed such that ion implantation is performed at a dose of 10-30% of the final concentration of the storage node junction. The method of claim 1, Injecting the impurity ions of the second conductivity type for forming the storage node junction and the bit line junction may include implanting the impurity ions at a concentration of 90-70% of the final impurity concentration of the bit line junction and the storage node junction. Method of manufacturing a semiconductor memory device, characterized in that performed.

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