KR20070069748A - Method of manufacturing mosfet device - Google Patents

Abstract

A method for manufacturing a MOSFET device is provided to prevent the trapping effect of a hot carrier to a gate oxide layer by forming thickly a sidewall of a gate oxide layer. A gate oxide layer(30), a conductive layer(40), and a hard mask layer(50) are sequentially formed on a semiconductor substrate(10). A gate(60) is formed by etching the hard mask layer, the conductive layer, and the gate oxide layer. An LDD region(70) is formed on the semiconductor substrate of both sides of the gate by performing a low-density ion implantation process. A halo region(80) is formed in the inside of the LDD region by performing a halo ion implantation process. A bird's beak is formed on a sidewall of the gate oxide layer by performing a local oxidation process. Asymmetric source/drain regions(90b.90a) are formed within the substrate of both sides of the gate by implanting obliquely high-density ions.

Description

Method of manufacturing MOSFET device

1 is a cross-sectional view for explaining a method for manufacturing a conventional MOSFET device.

Figure 2a to 2d is a cross-sectional view for each process for explaining the manufacturing method of the MOSFET device according to the present invention.

Figure 3a to 3e is another cross-sectional view for each process for explaining the manufacturing method of the MOSFET device according to the present invention.

Explanation of symbols on the main parts of the drawings

10,100: semiconductor substrate 20,120: device isolation film

30,130: gate oxide film 40,140: conductive film

50,150: hard mask layer 60,160: gate

70, 170: LDD area 80, 180: halo area

90a, 190a: drain region 90b, 190b: source region

A: 1st ion implantation mask B: 2nd ion implantation mask

200: spacer

The present invention relates to a method for manufacturing a MOSFET device, and more particularly, to a method for manufacturing a MOSFET device that can improve the data retention characteristics and hot carrier characteristics.

Dynamic Random Access Memory (DRAM) is a type of memory device that stores data and can be read out when needed. One MOS transistor and a charge, ie, data ) Is a set of DRAM cells consisting of one capacitor (Capacitor) that stores the.

However, as the design rules of the recently developed MOSFET devices become smaller, there may be a change in the characteristics of the lower Peri transistor during thermal budget tunneling for the cap configuration. It is also disadvantageous on the side. Therefore, recently, Tr of '1Tr + Bulk' has been used as a way to overcome this problem.

Referring to FIG. 1, a floating bulk structure wrapped with a buried N layer under bulk is used. On the other hand, in the case of writing data, an electron hole pair (hereinafter referred to as EHP) is generated to use a bulk voltage rise. That is, at this time, holes in the generated EHP flow toward the bulk to generate a positive voltage rise. As a result, a significant difference in read current is sensed to recognize high or low data.

However, Tr of '1Tr + Bulk' has the following problems. As the gap between the source and drain regions decreases, hot carriers generated by the electrons applied in the source region are rapidly accelerated by the high electric field near the edge of the drain region trap near the interface of the gate oxide layer. As a result, the hot carrier characteristic is deteriorated, resulting in a problem of reduced life time, and as a result, the data retention characteristic becomes unstable.

Accordingly, the present invention has been made to solve the above problems, and relates to a method of manufacturing a MOSFET device that can improve data retention hot carrier characteristics.

In order to achieve the above object, the present invention comprises the steps of sequentially forming a gate oxide film, a conductive film and a hard mask film on a semiconductor substrate; Etching the hard mask layer, the conductive layer, and the gate oxide layer to form a gate; Performing a low concentration ion implantation on the substrate product on which the gate is formed to form an LDD region in the substrate surface on both sides of the gate; Forming a halo region inside the LDD region by performing halo ion implantation on a substrate product on which the LDD region is formed; Performing a local oxidation process on the substrate resultant to form a buzz-big on the sidewall of the gate oxide film; And forming asymmetric source / drain regions in the substrate surface on both sides of the gate by inclining the substrate resultant to perform high concentration ion implantation.

The local oxidation process may be performed such that the gate oxide film sidewall thickness is 1.5 to 3 times the thickness of the other gate oxide film.

The high concentration ion implantation may be performed by giving an inclination of 5 to 45 °.

In addition, the present invention comprises the steps of sequentially forming a gate oxide film, a conductive film and a hard mask film on a semiconductor substrate; Etching the hard mask layer, the conductive layer, and the gate oxide layer to form a gate; Performing a low concentration ion implantation on the substrate product on which the gate is formed to form an LDD region in the substrate surface on both sides of the gate; Forming a halo region inside the LDD region by performing halo ion implantation on a substrate product on which the LDD region is formed; Performing a local oxidation process on the substrate resultant to form a buzz-big on the sidewall of the gate oxide film; Forming a first ion implantation mask exposing a drain predetermined region on the substrate resultant; Performing a high concentration ion implantation on the substrate resultant on which the first ion implantation mask is formed to form a drain region in the exposed substrate surface; Removing the first ion implantation mask; Forming spacers on both sidewalls of the gate; Forming a second ion implantation mask selectively exposing a source predetermined region on a substrate resultant having the spacer formed thereon; Forming a source region by performing high concentration ion implantation on the substrate resultant on which the second ion implantation mask is formed; It provides a method for manufacturing a MOSFET device comprising a; and removing the second ion implantation.

Here, the local oxidation process is characterized in that the gate oxide film sidewall thickness is 1.5 to 3 times the thickness of the other gate oxide film thickness.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention, the present invention relates to a method of manufacturing a MOSFET device, by performing a local oxidation process on the gate formed substrate to form a bird's-beak on the sidewall of the gate oxide film do.

In addition, ion implantation is performed by applying a tilt to the source / drain region to form a non-lightly doped drain (NLD) structure in the drain region.

In this case, the local oxidation process may be convex to form a sidewall buzz-big shape of the gate oxide layer, thereby preventing hot carriers from being trapped by the gate oxide layer.

In addition, by performing ion implantation on the source / drain regions at an inclination, the drain region has a non-LDD structure, thereby improving data retention characteristics.

In detail, FIGS. 2A to 2D are diagrams for describing a method of manufacturing a MOSFET device according to the present invention.

Referring to FIG. 2A, a pad oxide film (not shown) and a pad nitride film (not shown) are sequentially formed on a semiconductor substrate 10 having an active region and a device isolation region, and then a device isolation region is formed on the pad nitride layer. A photosensitive film pattern (not shown) to be exposed is formed. Thereafter, the pad nitride layer is etched using the photoresist pattern as an etch mask, and the pad oxide layer is etched using the pad nitride layer as an etch mask, and the exposed substrate is etched to form a trench.

Subsequently, an insulating film for device isolation is deposited on a substrate resultant to fill the trench in a state where the photoresist pattern is removed, and then the insulating film for device isolation is subjected to CMP (Chamical Mechanical Polishing) until the pad nitride film is exposed. Thereafter, the pad nitride layer and the pad oxide layer are removed to form the device isolation layer 20.

Subsequently, after forming a buffer oxide film (not shown) on the substrate product on which the device isolation film 20 is formed, P-type or N-type impurities are implanted into the substrate to form a P or N-well in the substrate. ). Then, ion implantation for channel formation is performed on the substrate on which the well is formed. Next, the buffer oxide film is removed.

Referring to FIG. 2B, a gate oxide layer 30, a conductive layer 40, and a hard mask layer 50 are deposited on a substrate on which the wells and channels are formed, and then etched to form a gate 60. ). Then, low concentration ion implantation is performed on the substrate product on which the gate 60 is formed to form a lightly doped drain (LDD) region 70 in the substrate surface on both sides of the gate. Next, halo ion implantation is performed on the substrate product on which the LDD region 70 is formed to form a halo region 80 inside the LDD region 70.

Referring to FIG. 2C, a local oxidation process is performed on the substrate resultant to form a bird's-beak on the sidewall of the gate oxide layer 30. In this case, the local oxidation process is performed such that the gate oxide sidewall thickness is 1.5 to 3 times the thickness of the other gate oxide layer.

Here, the present invention increases the thickness of the gate oxide film sidewalls by performing a local oxidation process, thereby preventing electrons along with holes from being trapped near the interface of the gate oxide film. Can be.

Referring to FIG. 2D, a high concentration of ion implantation is performed by tilting the substrate resultant to form an asymmetery source / drain regions 90b and 90a in the substrate surface on both sides of the gate 60. At this time, the high concentration ion implantation is performed by giving an inclination of 5 ~ 45 °.

Here, the present invention forms an asymmetric junction region by inclining the source / drain region to perform ion implantation. Therefore, by forming the non-LDD structure in the drain region, data retention characteristics can be improved.

(Other embodiment)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3E are diagrams for describing a method of manufacturing a MOSFET device according to another exemplary embodiment of the present invention.

Referring to FIG. 3A, a pad oxide film (not shown) and a pad nitride film (not shown) are sequentially formed on a semiconductor substrate 110 including an active region and a device isolation region, and then a device isolation region is formed on the pad nitride layer. A photosensitive film pattern (not shown) to be exposed is formed. Thereafter, the pad nitride layer is etched using the photoresist pattern as an etch mask, and the pad oxide layer is etched using the pad nitride layer as an etch mask, and the exposed substrate is etched to form a trench.

Subsequently, an insulating film for device isolation is deposited on a substrate resultant to fill the trench in a state where the photoresist pattern is removed, and then the insulating film for device isolation is subjected to CMP (Chamical Mechanical Polishing) until the pad nitride film is exposed. Thereafter, the pad nitride layer and the pad oxide layer are removed to form the device isolation layer 120.

Subsequently, after forming a buffer oxide film on the substrate product on which the device isolation film 120 is formed, P or N-type impurities are implanted into the substrate to form P or N-well in the substrate. . Then, ion implantation for channel formation is performed on the substrate on which the well is formed. Next, the buffer oxide film is removed.

Referring to FIG. 3B, after the gate oxide layer 130, the conductive layer 140, and the hard mask layer 150 are deposited on the substrate on which the wells and the channels are formed, the gates 160 are formed by etching the gate oxide layer 130. Thereafter, low concentration ion implantation is performed on the substrate product on which the gate 160 is formed to form the LDD region 170 in the substrate surface on both sides of the gate 160. Next, halo ion implantation is performed on the substrate product on which the LDD region 170 is formed to form a halo region 180 inside the LDD region 170.

Referring to FIG. 3C, a local oxidation process is performed on the substrate resultant to form a bird's-beak on the sidewall of the gate oxide layer 130. In this case, the local oxidation process is performed such that the thickness of the sidewall thickness of the gate oxide film 130 is 1.5 to 3 times the thickness of the other gate oxide film.

Here, the present invention increases the thickness of the gate oxide film sidewalls by performing a local oxidation process, thereby preventing electrons along with holes from being trapped near the interface of the gate oxide film. Can be.

Referring to FIG. 3D, after forming a first ion implantation mask A exposing a drain predetermined region on the substrate resultant, high concentration ion implantation is performed on the substrate resultant on which the first ion implantation mask A is formed. Thus, the drain region 190a is formed in the exposed substrate surface.

Referring to FIG. 3E, in a state in which the first ion implantation mask is removed, an insulating film for a spacer is deposited on the entire surface of the substrate including the gate, and then etched back to the gate 130. The spacers 200 are formed on both side walls. Next, a second ion implantation mask B is formed on the substrate product on which the spacer 200 is formed to selectively expose the source predetermined region. Next, the source region 190b is formed by performing high concentration ion implantation on the substrate resultant on which the second ion implantation mask B is formed.

In the present invention, the drain region is formed before forming the spacer, and the source region is formed after forming the spacer, thereby forming a junction region having an asymmetery structure. Therefore, the drain region may be formed in a non-LDD structure to improve data retention characteristics.

Subsequently, although not shown, a MOSFET device according to the present invention is manufactured by removing the second ion implantation mask.

As described above, the present invention has an effect of forming a thick sidewall of the gate oxide film to prevent a hot carrier from being trapped by the gate oxide film, thereby enabling high-speed operation of the device. The device can be manufactured.

In addition, the present invention can see the effect of improving the data retention characteristics (data retention) by forming the drain region in a non-LDD structure.

 As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

Claims (5)

Sequentially forming a gate oxide film, a conductive film, and a hard mask film on the semiconductor substrate; Etching the hard mask layer, the conductive layer, and the gate oxide layer to form a gate; Performing a low concentration ion implantation on the resultant substrate on which the gate is formed to form an LDD region in the substrate surface on both sides of the gate; Forming a halo region inside the LDD region by performing halo ion implantation on a substrate product on which the LDD region is formed; Performing a local oxidation process on the substrate resultant to form a buzz-big on the sidewall of the gate oxide film; And And forming asymmetric source / drain regions in the substrate surface on both sides of the gate by inclining the substrate resultant to perform high concentration ion implantation. The method of claim 1, Wherein the local oxidation process is performed such that the gate oxide sidewall thickness is 1.5 to 3 times the thickness of the other gate oxide layer. The method of claim 1, The high concentration ion implantation method of the MOSFET device characterized in that performed by giving an inclination of 5 to 45 °. Sequentially forming a gate oxide film, a conductive film, and a hard mask film on the semiconductor substrate; Etching the hard mask layer, the conductive layer, and the gate oxide layer to form a gate; Performing a low concentration ion implantation on the substrate product on which the gate is formed to form an LDD region in the substrate surface on both sides of the gate; Forming a halo region inside the LDD region by performing halo ion implantation on a substrate product on which the LDD region is formed; Performing a local oxidation process on the substrate resultant to form a buzz-big on the sidewall of the gate oxide film; Forming a first ion implantation mask exposing a drain predetermined region on the substrate resultant; Performing a high concentration ion implantation on the substrate resultant on which the first ion implantation mask is formed to form a drain region in the exposed substrate surface; Removing the first ion implantation mask; Forming spacers on both sidewalls of the gate; Forming a second ion implantation mask selectively exposing a source predetermined region on a substrate resultant having the spacer formed thereon; Forming a source region by performing high concentration ion implantation on the substrate resultant on which the second ion implantation mask is formed; And Removing the second ion implantation; and manufacturing the MOSFET device. The method of claim 4, wherein Wherein the local oxidation process is performed such that the gate oxide sidewall thickness is 1.5 to 3 times the thickness of the other gate oxide layer.

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