KR20070109277A - Liquid crystal display device and fabricating method of the same - Google Patents

Abstract

An LCD and a fabrication method thereof are provided to omit a passivation-layer forming process to reduce a fabrication cost and maximize productivity. A gate line(102) is formed on a substrate(100). A common line is formed at a predetermined interval with the gate line. A data line(165) and the gate line intersect. The data line defines a pixel area. A thin film transistor is formed at the pixel area, and includes a channel passivation layer(130b) interposed between a portion of an ohmic contact layer(152) and an active layer(120a). A plurality of pixel electrodes(164) is formed integrally with a drain electrode(163) of the thin film transistor. A common electrode(105) is connected to the common line and is disposed alternately with the pixel electrode.

Description

Liquid crystal display device and method for manufacturing the same {liquid crystal display device and fabricating method of the same}

1A and 1B are diagrams for describing a liquid crystal display according to an exemplary embodiment of the present invention.

2A to 2G are flowcharts illustrating a manufacturing process of a liquid crystal display according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

 100: substrate 102: gate wiring

 103: gate electrode 104: common wiring

 105: common electrode 106: gate pad

 107: data pad 108: common voltage pad

 109 data link wiring 110 gate insulating film

 120a: active layer 130b: channel protective film

 152: ohmic contact layer 162: source electrode

 163: drain electrode 164: pixel electrode

 165 data wiring

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing the same which can reduce the number of processes.

Today, the liquid crystal display device has not only researched to realize high quality such as high resolution and low power consumption, but also has made a lot of efforts to increase price competitiveness by simplifying the process and maximizing productivity.

In the liquid crystal display device, the thin film transistor array substrate and the color filter array substrate are spaced apart from each other by a predetermined interval, and liquid crystal is injected between the two substrates. Here, electrodes are formed on the inner surfaces of the two substrates, and the voltage is applied to the two electrodes to drive the liquid crystal, thereby controlling the transmittance of the light passing through the liquid crystal to represent an image.

The liquid crystal display may be manufactured by forming the thin film transistor array substrate and the color filter array substrate, and then bonding the two substrates and injecting liquid crystal. In this case, in order to form the thin film transistor array substrate and the color filter array substrate, the thin film transistor array may be manufactured by repeatedly performing a process including a thin film deposition process, a cleaning process, a photolithography process, and an etching process.

As the liquid crystal display is manufactured by performing such a process several times, the process time and the process cost are increased, thereby reducing productivity and increasing the probability of defects.

Conventionally, in order to simplify the process, the source electrode / drain electrode and the active layer are formed in one mask process. In this process, there is a problem in that the screen quality is deteriorated because an active layer that is wider than the data wiring width exists inevitably under the data wiring. There is.

This may be accompanied by a defect of wave noise due to a tail defect along the data line when the liquid crystal display is driven. In addition, impurities may be injected into the active layer under the data line in a subsequent process, or may have electrical conductivity due to an external environment, especially a temperature, thereby causing image quality defects such as high temperature vertical cross talk. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a method for manufacturing the same, which can reduce the number of steps by removing the protective film forming step.

Another object of the present invention is to provide a liquid crystal display and a method of manufacturing the same, which prevent the degradation of image quality due to wave noise and high temperature vertical crosstalk, and reduce the number of processes.

Further, another object of the present invention is to provide a liquid crystal display and a method of manufacturing the same, which can prevent the contamination of the channel region due to the absence of the protective film, thereby preventing the characteristics of the thin film transistor from deteriorating.

In order to achieve the above technical problem, an aspect of the present invention provides a liquid crystal display device. The liquid crystal display device includes a substrate; A gate wiring formed on the substrate; A common wiring formed at a predetermined distance from the gate wiring; A data line formed to intersect the gate line to define a pixel area; A thin film transistor formed in the pixel region and having a channel passivation layer interposed between a portion of the ohmic contact layer and an active layer; A pixel electrode formed integrally with the drain electrode of the thin film transistor and branched into a plurality; And a common electrode connected to the common wiring and alternately arranged with the pixel electrode.

In order to achieve the above technical problem, another aspect of the present invention provides a method of manufacturing a liquid crystal display device. A method of manufacturing the liquid crystal display device includes forming a gate electrode, a gate wiring, a common wiring, and a common electrode on a substrate using the same mask; Forming a gate insulating film on the first gate electrode; Forming a channel protective film and an active layer on the gate insulating film using the same mask; Forming a pixel electrode integral with the channel protection layer, the ohmic contact layer, the source / drain electrode, the data line, and the drain electrode.

Hereinafter, with reference to the drawings of the liquid crystal display according to the present invention will be described in detail. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like numbers refer to like elements throughout.

1A and 1B are diagrams for describing a liquid crystal display device according to a first embodiment of the present invention. Here, FIG. 1A is a plan view showing one unit pixel of the liquid crystal display in a limited manner, and FIG. 1B is a cross-sectional view of FIG. 1A taken along lines II ′ and II ′.

Referring to FIGS. 1A and 1B, the liquid crystal display is uniform with the gate wiring 102, the data wiring 165, and the gate wiring 102 crossing each other on the substrate 100 to define a pixel area. It includes a common wiring 104 spaced apart and arranged in parallel. The liquid crystal display device is integrally formed with the thin film transistor Tr and the drain electrode 163 of the thin film transistor Tr formed in the pixel region defined by the gate line 102 and the data line 165. And a common electrode 105 formed in a plurality of pixel electrodes 164 and connected to the common wiring 104 and alternately arranged with the pixel electrodes 164.

The liquid crystal display further includes a pad positioned at an outer portion of the substrate 100 and connected to an external circuit. The pad may include a gate pad 106 formed by extending the gate lines 102, a data pad 107 electrically connected to one end of each of the data lines 165, and each of the common lines 104. And may include a common voltage pad 108. In this case, although not shown in the drawings, the pads may be electrically connected to each other by a printed circuit board (PCB), which is an external circuit unit, and a tape automated bonding (TAB) method using a tape carrier package (TCP). have.

The thin film transistor Tr includes a channel protection layer 130b interposed between a portion of the ohmic contact layer 152 and the active layer 120a to prevent the channel region b from being contaminated. The channel protection layer 130b not only protects the channel region, but also acts as an etch stop layer to prevent the active layer 120a from being etched in the process of manufacturing the thin film transistor Tr.

 In addition, a pad exposed to the outside, that is, the gate pad 106, the data pad 107, and the common voltage pad 108 may be formed of the same conductive material as that of the gate wiring 102, but the gate wiring 102 may be formed of a first material. The conductive film 101a and the second conductive film 102 are formed of a double film sequentially stacked. In this case, the first conductive film 101a is formed of a low resistance conductive material, and the second conductive film 101b is formed of a conductive material having corrosion resistance. As a result, the gate pad 106, the data pad 107, and the common voltage pad 108 are exposed by the first, second, and third contact holes P1, P2, and P3 formed in the gate insulating layer, respectively. Since the second conductive layer 101b formed of the corrosion resistant conductive material is exposed to the outside, the pad of the completed liquid crystal display device may be prevented from corroding and deteriorating reliability.

In detail, in the liquid crystal display, the substrate 100 is first positioned. A gate wiring 102 having one direction on the substrate 100, a gate electrode 103 formed by branching the gate wiring 102, and the gate wiring 102 extending to one side of the substrate 100. The gate pad 106 is formed.

The common wiring 104 disposed in parallel with the gate wiring 102, the common voltage pad 108 formed by extending the common wiring 104, and the common wiring 104 are integrally formed with each other. The divided common electrode 105 is positioned. Here, the common electrode 105 may be formed in various forms in the group consisting of a stripe shape, a part bent shape and a zigzag shape, but is not limited in the embodiment of the present invention.

The data link wiring 109 formed on the other side of the substrate 100 and formed on the same layer as the gate wiring 102 and the data pad 107 formed by extending the data link wiring 109 are positioned.

The gate wiring 102 is formed by stacking a first conductive film 101a and a second conductive film 102b. The first conductive film 101a is a low resistance conductive material and is formed including at least one selected from the group consisting of Al, Mo, Cu, MoW, MoTa, MoNb, Cr, W, and AlNd. The second conductive film 101b is a corrosion resistant conductive material and is formed of ITO or IZO. In this case, the common electrode 105, the gate pad 106, the data pad 107, and the common voltage pad 108 are formed of the same conductive material as the gate wire 102.

The gate insulating layer 110 is positioned over the entire surface of the substrate including the gate wiring 102. The gate insulating layer 110 may include first, second, and third contact holes P1, P2, and P3 exposing the gate pad 106, the data pad 107, and the common voltage pad 108, respectively. ). In addition, a fourth contact hole P4 may be further provided to expose a portion of the data link line 109 so as to connect the data link line 109 to the data line 165 formed on another layer. have.

The semiconductor layer 155 on which the active layer 120a and the ohmic contact layer 152 are sequentially disposed is disposed on the gate insulating layer 110 corresponding to the gate electrode 103.

The semiconductor layer 155 may be defined as a source region (a), a channel region (b), and a drain region (c), and source electrodes on the source region (a) and the drain region (c), respectively. 162 and the drain electrode 163 are positioned. In this case, an ohmic contact layer 152 is interposed between the active layer 120a and the source electrode 162 and between the active layer 120a and the drain electrode 163, respectively. The active layer 120a and the ohmic contact layer 152 are stacked in the source region a and the drain region c. The channel region b of the semiconductor layer 155 is formed of the active layer 120a.

Here, the channel region b may be exposed to the outside to contaminate the active layer 120a of the channel region b in a subsequent process, thereby reducing the characteristics of the thin film transistor Tr. In particular, when the protective film is not formed as in the present invention, the contamination of the active layer 120a may occur more excessively.

As a result, a channel passivation layer 130b for protecting the active layer 120a positioned on the channel region b is positioned. The channel passivation layer 130b is interposed between the active layer 120a and the ohmic contact layer 152. The channel passivation layer 130b and the ohmic contact layer 152 partially overlap each other. The passivation layer 130b is formed to be smaller than the width of the active layer 120a and is formed to expose both ends of the active layer 120a. This is to contact the source electrode 162 and the drain electrode 163 with the ohmic contact layer 150a.

In this case, the channel protection layer 130b may serve as an etch stop layer to prevent the active layer 120a from being etched when the source electrode 162 and the drain electrode 163 are formed. Accordingly, the channel protection layer 130b may be formed of an insulating layer having an etching selectivity different from that of the active layer 120a. The channel protection film 130b may be formed of an inorganic insulating film, an organic insulating film, or a stacked film thereof. The inorganic insulating film may be a silicon oxide film or a silicon nitride film. The organic insulating layer may be at least one selected from the group consisting of polyimide resin, acrylic resin, benzocyclobutene (BCB), and perfluorocyclobutene resin (PFCB).

The data line 165 is disposed on the gate insulating layer 110 to cross the gate line 102. One end of the data line 165 is formed to be connected to the data link line 109 exposed by the fourth contact hole P4. Thus, the data line 165 and the data pads 107 formed on different layers may be electrically connected to each other.

In addition, the source electrode 162 is formed to branch off the data line 165.

In the exemplary embodiment of the present invention, a U-shaped thin film transistor capable of improving the characteristics of the thin film transistor Tr by increasing the corresponding width of the source electrode 162 and the drain electrode 163 is illustrated and illustrated in the drawings. However, embodiments of the present invention may be applied to various types of thin film transistors, but are not limited thereto.

The pixel electrode 164 is positioned integrally with the drain electrode 163 in the pixel area defined by the gate line 102 and the data line 165. Here, the pixel electrode 164 is formed by dividing into a plurality, and each of the divided pixel electrodes 164 is alternately disposed with the common electrode 105. Accordingly, when a high voltage is applied to the common electrode 105 and a low voltage is applied to the pixel electrode 164, a horizontal electric field is formed between the common electrode 105 and the pixel electrode 164. In addition, vertical electric fields are formed on the common electrode 105 and the pixel electrode 164, and horizontal and vertical electric fields are formed in the corner portions of each of the common electrode 105 and the pixel electrode 164. The liquid crystal molecules are arranged in various directions by the same electric field, so that the viewing angle at each position can be improved.

In addition, the pixel electrode 164 may be formed to partially overlap the common wiring 104 to form a capacitor Cp.

In addition, an ohmic contact layer 152 may be disposed under the data line 165 and the pixel electrode 164, respectively. The source electrode 162, the drain electrode 163, the data line 165, the pixel electrode 164, and the ohmic contact layer 152 are formed using the same mask in order to reduce the number of processes in the process. Because. At this time, since the active layer is formed using the same mask as the channel passivation layer 130b, the process is not further added. Thus, in order to reduce the number of masks in the related art, as the data line, the active layer, and the ohmic cone layer are formed through the same mask, a problem of deterioration in image quality caused by an active layer having a wider width than the data line is disposed below the data line. I can solve it.

As a result, the liquid crystal display selectively protects the channel region b in order to prevent contamination of the channel region b, and at the same time serves as an etch stop layer, thereby eliminating the need for forming a protective layer. In addition, the gate pad, the data pad, and the common voltage pad exposed to the outside may form a second conductive film having corrosion resistance thereon, thereby preventing a defect due to corrosion.

Although not shown in the drawing, the substrate may further include a color filter array substrate disposed on the substrate 100 at a predetermined interval and a liquid crystal layer formed between the two substrates.

2A to 2G are flowcharts illustrating the manufacturing process of the liquid crystal display of the present invention. 2A to 2G are cross-sectional views of FIG. 1A taken as I-I 'and II-II'.

Referring to FIG. 2A, a substrate is first provided. The substrate 100 may be glass, quartz, or plastic.

After depositing a conductive material on the substrate 100, through the exposure and development process, the gate wiring 102, the gate electrode 103, the common wiring 104, the common electrode 105, the gate pad 106, The data pad 107 and the common voltage pad 108 are formed at the same time. Here, the data link wiring 109 extending with the data pad 107 may be further formed.

In detail, the first conductive film 101a and the second conductive film 101b are sequentially deposited on the substrate 100 by sputtering or vacuum deposition. In this case, the first conductive film 101a may be formed of at least one selected from the group consisting of Al, Mo, Cu, MoW, MoTa, MoNb, Cr, W, and AlNd as a low resistance conductive material. In addition, the second conductive film 101b is a conductive material having corrosion resistance and may be formed of ITO or IZO.

Subsequently, after the photosensitive film is formed on the second conductive film 101b, the photosensitive film is subjected to an exposure and development process to form a first photosensitive film pattern (not shown). Subsequently, after the second conductive film 101b and the first conductive film 101a are etched according to the first photosensitive film pattern, the first photosensitive film pattern is removed to remove the gate wiring 102. The gate electrode 103, the common wiring 104, the common electrode 105, the gate pad 106, the data pad 107, and the common voltage pad 108 may be formed.

The gate wiring 102, the gate electrode 103, and the gate pad 106 may be integrally formed. In addition, the common wiring 104, the common electrode 105, and the common voltage pad 108 may be integrally formed, and the common electrode 105 may be divided into a plurality of pixel regions. In addition, the data pad 107 and the data link wiring 109 may be integrally formed.

2B, the gate wiring 102, the gate electrode 103, the common wiring 104, the common electrode 105, the gate pad 106, the data pad 107, and the common circuit. The gate insulating film 110, the first semiconductor layer 120, the insulating film 130, and the second photosensitive film pattern 140a are sequentially formed over the entire surface of the substrate including the voltage pad 108. The gate insulating layer 110 and the first semiconductor layer 120 may be formed by chemical vapor deposition. The gate insulating layer 110 may be a silicon nitride film or a silicon oxide film. In addition, the first semiconductor layer 120 may be amorphous silicon.

The insulating layer 130 may be formed of an inorganic insulating layer or an organic insulating layer. In detail, the inorganic insulating film may be a silicon oxide film or a silicon nitride film. The organic insulating layer may be at least one selected from the group consisting of polyimide resin, acrylic resin, benzocyclobutene (BCB), and perfluorocyclobutene resin (PFCB).

Here, when the insulating film 130 is an inorganic insulating film, it can be formed by chemical vapor deposition. When the insulating film 130 is an organic insulating film, spin coating, dip coating, roll coating, bar coating, screen printing, or ink jet Can be formed in any way during printing

The second photosensitive pattern 140a may be formed through an exposure and development process after forming a photosensitive film on the insulating layer 130, aligning the mask 200 on the photosensitive film. The photosensitive film is formed by any one of spin coating, dip coating, roll coating, bar coating, screen printing or inkjet printing at least one selected from the group consisting of an acrylic resin, a polyimide resin, a polyamide resin, and a benzocyclobutene resin. can do

The mask 200 may be a diffraction mask that can adjust the intensity of light irradiated to the photosensitive layer for each part. That is, the mask includes a transmissive area 200a, a transflective area 200b, and a blocking area 200c, and includes a plurality of slits in the transflective area 200b to adjust the intensity of transmitted light. Here, unlike the drawing, the mask 200 may be a halftone mask that can adjust the intensity of light by using a light blocking material that can partially block light in the transflective area 200b.

When the photosensitive layer is formed of a positive photosensitive resin, the transmission region 200a of the mask 200 may expose a first gate pad 104, the data pad 107, and the common voltage pad 108. And the second and third contact holes P1, P2, and P3 to correspond to the formation regions, and the blocking region 200c of the mask 200 corresponds to the formation region of the active layer to be described later. The semi-transmissive region 200b of the mask 200 corresponds to the remaining region of the substrate. Here, when the photosensitive film is formed of a negative photosensitive resin, unlike the drawing, the mask 200 may be disposed such that the blocking area 200c and the transmission area 200a correspond to each other.

Subsequently, when the exposure and development processes are performed using the mask 200, the photosensitive film corresponding to the transmissive region 200a is completely removed, and the photosensitive film corresponding to the transflective region 200b is the blocking region 200c. The second photosensitive film pattern 140a remaining smaller than the thickness of the photosensitive film corresponding to) may be formed.

The insulating layer 130, the first semiconductor layer 120, and the gate insulating layer 110 are etched according to the second photosensitive layer pattern 140a to form the gate pad 106, the data pad 107, and the common layer. First, second, and third contact holes P1, P2, and P3 exposing portions of the voltage pad 108 are formed. At the same time, a fourth contact hole P4 exposing a portion of the data link wiring 109 may be formed.

An ashing process is performed on the second photosensitive film pattern 140a to form a third photosensitive film pattern 140b as shown in FIG. 2C. Here, the ashing process is performed until the photosensitive film corresponding to the transflective region 200b of the mask 200 in FIG. 2B is removed. In this case, the thickness of the photosensitive film corresponding to the blocking region 200c of the mask 200 is reduced by the thickness of the removed photosensitive film.

Dry etching the insulating film 130 and the first semiconductor layer 120 according to the third photosensitive film pattern 140b, and is located on the active layer 120a and the active layer 120a as shown in FIG. The insulating film pattern 130a is formed.

Thereafter, an ashing process is performed until both sides of the third photosensitive film pattern 140b are partially removed, thereby forming the fourth photosensitive film pattern 140c as illustrated in FIG. 2E.

The channel protection layer 130b is formed by patterning the insulating layer pattern 130a according to the fourth photosensitive layer pattern 140c.

In this case, when the channel protective layer 130b is formed of the photosensitive organic layer of the organic insulating layer, the second photosensitive pattern 140a is not formed on the insulating layer 130 (in FIG. 2B). After the mask (200 in FIG. 2B) is aligned, the insulating layer 130 is etched through an exposure and development process, and the first, second, third and fourth contact holes P1, P2, P3, P4), the active layer 120a and the channel passivation layer 130b may be formed.

Thereafter, after peeling the fourth photosensitive film pattern 140c as shown in FIG. 2F, the second semiconductor layer 150, the first conductive film 160, and the entire surface of the substrate including the channel protection film 130b and The fifth photosensitive film pattern 170 is sequentially formed. The second semiconductor layer 150 may be formed through chemical vapor deposition, and the first conductive layer 160 may be formed through vacuum deposition or sputtering. In this case, the second semiconductor layer 150 may be formed of amorphous silicon doped with impurities. In addition, the third conductive layer 160 may be formed of at least one selected from the group consisting of Mo, Ti, Ta, MoTa, MoW, and MoNb. The fifth photosensitive film pattern 170 may be formed through an exposure and development process after forming the photosensitive film.

According to the fifth photosensitive film pattern 170, the third conductive film 161 and the second semiconductor layer 151 are collectively etched, and as shown in FIG. 2G, the source electrode 162 and the drain electrode. 163, the pixel electrode 164, the data line 165, and the ohmic contact layer 152 are formed.

In this case, the second semiconductor layer 150 is etched until the channel protection layer 130b is completely exposed. The channel protection layer 130b may be etched in the etching process until the second semiconductor layer 150 positioned on the channel region of the active layer 120a is completely removed. It can act as an anti-etching film. This is because if the second semiconductor layer 150 remains on the channel region, the on / off current value characteristic of the thin film transistor may be degraded.

At this time, only the ohmic contact layer 152 is positioned below the data line 165. Here, the ohmic contact layer 152 is formed by isotropic dry etching at the time of formation of the data line 163, so that the width of the ohmic contact layer 152 and the width of the data line 165 are Is formed identically. Thus, the active layer 120a, the ohmic contact layer 152, the source electrode 162, the drain electrode 163, and the data line 165 are conventionally formed in the same mask in a 4 mask process, thereby forming the data line. The problem of deterioration in image quality caused by the formation of an active layer having a wider width than that of the data line 165 can be solved.

Subsequently, although not shown in the drawings, an alignment layer for alignment of the liquid crystal layer may be further formed. In addition, the liquid crystal display may be manufactured by providing a color filter array substrate on the substrate and then performing a bonding and liquid crystal forming process.

Thus, the contamination of the channel region due to the absence of the protective film can be solved by forming the channel protective film 130b. In this case, the channel passivation layer 130b serves as an etch stop layer of the active layer, thereby improving the characteristics of the thin film transistor. In this case, the channel protective layer 130b is formed using a mask for forming the active layer 120a and the first, second, and third contact holes P1, P2, and P3. To form, no further mask process is added. In addition, the data line 165 and the ohmic contact layer 152 may be formed using the same mask, but only the ohmic contact layer 152 may be positioned under the data line 165 to prevent the image quality from being lowered. Can be. Thereby, the number of processes can be reduced while preventing the defect that image quality deteriorates.

In addition, the channel protective film 130b may perform a role of a conventional protective film, thereby reducing the protective film forming process.

In addition, the gate pad 106, the data pad 107, and the common voltage pad 108 exposed to the outside may be formed as a double layer, and the upper portion may be formed as a second conductive layer having corrosion resistance. It is possible to prevent the degradation of the reliability of the completed liquid crystal display device. In this case, the gate pad 106, the data pad 107, and the common voltage pad 108 are formed in the same manner as the gate wiring 102, and the data pad 107 and the data wiring 165 are removed. By connecting through 4 contact holes, no process is added.

As described above, according to the liquid crystal display device and the manufacturing method thereof according to the present invention, by removing the protective film forming process, the process can be simplified to maximize the productivity.

In addition, by removing the protective film forming process, it is possible to reduce the production cost, thereby securing a price competitiveness.

In addition, the contamination of the channel region and the corrosion of the wiring due to the absence of the protective film can be solved.

In addition, it is possible to manufacture a liquid crystal display device thinner than the conventional due to the member of the protective film.

In addition, the gate pad, the data pad, and the common voltage pad exposed to the outside may be formed as a double layer, and an upper portion thereof may be formed of a conductive material having corrosion resistance, thereby improving reliability of the completed liquid crystal display device.

In addition, it was possible to improve the image quality degradation problem caused by simplifying the process.

Although described above with reference to embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that.

Claims (20)

Board; A gate wiring formed on the substrate; A common wiring formed at a predetermined distance from the gate wiring; A data line formed to intersect the gate line to define a pixel area; A thin film transistor formed in the pixel region and having a channel passivation layer interposed between a portion of the ohmic contact layer and an active layer; A pixel electrode formed integrally with the drain electrode of the thin film transistor and branched into a plurality; And And a common electrode connected to the common wiring and alternately arranged with the pixel electrode. The method of claim 1, And the channel protective film is formed of any one of an inorganic insulating film, an organic insulating film, and a laminated film thereof. The method of claim 1, And the channel passivation layer serves as an etch stopper of the active layer. The method of claim 1, The gate line is formed by stacking a first conductive layer and a second conductive layer. The method of claim 4, wherein The first conductive layer is formed of a low resistance conductive material. The method of claim 4, wherein The first conductive layer is formed of at least one selected from the group consisting of Al, Mo, Cu, MoW, MoTa, MoNb, Cr, W and AlNd. The method of claim 4, wherein And the second conductive layer is formed of a conductive material having corrosion resistance. The method of claim 4, wherein And the second conductive layer is formed of any one of ITO and IZO. The method of claim 1, A gate pad formed by extending the gate line; A data pad positioned at one end of the data line and formed of the same conductive material on the same layer as the gate line; A common voltage pad formed by extending the common wiring; And And a data link wiring formed by extending the data pad. The method of claim 9, And a gate insulating layer having first, second, and third contact holes exposing the gate pad, the data pad, and the common voltage pad, respectively. The method of claim 1, And an ohmic contact layer formed under the data line and the pixel electrode. Forming a gate electrode, a gate wiring, a common wiring, and a common electrode on the substrate using the same mask; Forming a gate insulating film on the first gate electrode; Forming a channel protective film and an active layer on the gate insulating film using the same mask; And a pixel electrode integrally formed with the ohmic contact layer, the source / drain electrode, the data line, and the drain electrode partially overlapping the channel passivation layer. The method of claim 12, The gate line is formed by sequentially stacking and patterning a first conductive layer and a second conductive layer. The method of claim 13, The first conductive film is formed of at least one selected from the group consisting of Al, Mo, Cu, MoW, MoTa, MoNb, Cr, W and AlNd. The method of claim 13, The second conductive film is formed of either ITO or IZO. The method of claim 12, And the channel protective film is formed of any one of an organic insulating film, an inorganic insulating film or a laminated film thereof. The method of claim 12, The channel protective layer is formed by any one method selected from the group consisting of chemical vapor deposition, spin coating, dip coating, roll coating, bar coating, screen printing and inkjet printing. The method of claim 12, A gate pad, a data link wiring, a data pad, and a common voltage pad are further formed. The method of claim 12, And the mask is formed using either a halftone mask or a diffraction mask. The method of claim 18, The first, second, third, and fourth contact holes exposing the gate pad, the data pad, the common voltage pad, and the data link wiring are further formed when the channel passivation layer and the active layer are formed. The manufacturing method of the liquid crystal display device characterized by the above-mentioned.

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