KR101960052B1 - Aarray substrate for fringe field switching mode liquid crystal display device and method of fabricating the same - Google Patents

Abstract

Layered structure of a transparent conductive material and a low-resistance metal material, and a gate electrode of a double-layer structure connected to the gate wiring in each pixel region are formed on a substrate on which a pixel region is defined, Forming a pixel electrode having a single layer structure made of the transparent conductive material within the region; Selectively forming a gate insulating film on the gate wiring and the gate electrode; Forming a source electrode and a drain electrode spaced apart from the semiconductor layer in sequence on the gate insulating film in correspondence to the gate electrode, and forming a pixel region which is connected to the source electrode on the substrate and crosses the gate wiring, Forming a data line; Forming a protective layer over the source and drain electrodes and the data line; Forming a drain pixel contact hole exposing the pixel electrode at one end of the drain electrode and one end of the drain electrode by patterning the passivation layer and the gate insulating layer; A common electrode having a plurality of openings spaced apart from each other in the form of a bar corresponding to each of the pixel electrodes and a hole having a larger area than the drain pixel contact hole corresponding to the drain pixel contact hole are formed on the protective layer, Forming a pixel drain connection pattern in the hole, the pixel drain connection pattern being in contact with one end of the drain electrode and the pixel electrode at the same time and spaced apart from the common electrode, and a method of fabricating the array substrate for a fringe field switching mode liquid crystal display The present invention also provides an array substrate for a fringe field switching mode liquid crystal display manufactured through the method.

Description

[0001] The present invention relates to an array substrate for a fringe field switching mode liquid crystal display device and a manufacturing method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device capable of reducing the number of mask processes and reducing power consumption by improving transmittance, And a manufacturing method thereof.

In general, a liquid crystal display device is driven by using optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

At present, an active matrix liquid crystal display (AM-LCD: hereinafter referred to as liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and video realization capability, It is attracting attention.

The liquid crystal display device includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display device, The liquid crystal is driven to have excellent properties such as transmittance and aperture ratio.

However, liquid crystal driving by an electric field that is applied up and down has a drawback that the viewing angle characteristic is not excellent.

Therefore, a transverse electric field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown in the figure, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, are spaced apart from each other and face each other. A liquid crystal layer 11 is interposed between the upper and lower substrates 9, .

The common electrode 17 and the pixel electrode 30 are formed on the same plane on the lower substrate 10 and the liquid crystal layer 11 is formed by the common electrode 17 and the pixel electrode 30 And is operated by the horizontal electric field (L).

2A and 2B are cross-sectional views respectively showing the on and off states of a general transverse electric field type liquid crystal display device.

2A showing the alignment state of the liquid crystal in the ON state to which the voltage is applied, the phase of the liquid crystal 11a at the position corresponding to the common electrode 17 and the pixel electrode 30 is The liquid crystal 11b located between the common electrode 17 and the pixel electrode 30 is formed by a horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, And arranged in the same direction as the horizontal electric field (L). That is, since the liquid crystal is moved by the horizontal electric field in the transverse electric field type liquid crystal display device, the viewing angle becomes wide.

Therefore, when viewed from the front, the transverse electric-field-type liquid-crystal display device can be visually observed in the direction of about 80 to 85 degrees in the up / down / left / right direction without reversal.

Next, referring to FIG. 2B, a horizontal electric field is not formed between the common electrode and the pixel electrode since the liquid crystal display device is in an off state in which no voltage is applied, so that the alignment state of the liquid crystal layer 11 is not changed.

However, the transverse electric-field-type liquid crystal display device having such a configuration has an advantage of improving the viewing angle, but has a disadvantage in that the aperture ratio and the transmissivity are low.

Accordingly, a fringe field switching mode LCD has been proposed in which a liquid crystal is operated by a fringe field in order to realize a disadvantage of such a lateral electric field type liquid crystal display device.

3 is a cross-sectional view of a portion of a conventional fringe field switching mode liquid crystal display device substrate cut through a central portion of one pixel region.

As shown in the drawing, a conventional fringe field switching mode liquid crystal display device array substrate 41 has a plurality of pixel regions P defined by intersections of the lower and upper portions thereof with a gate insulating film 45 interposed therebetween, And a data line 47 are formed in each pixel region (not shown), and a thin film transistor Tr is formed in the pixel region (not shown) to be connected to the gate and data lines (not shown).

In addition, a plate-shaped pixel electrode 55 is formed in each pixel region (not shown) above the gate insulating film 45 in contact with the drain electrode 51 of the thin film transistor. The pixel electrode 55 is formed on the same layer as the data line 47, that is, on the gate insulating layer 45, and the data line 47 ) And a predetermined distance from each other.

A protective layer 60 is formed as an inorganic insulating material on the front surface of the data line 47 and the pixel electrode 55. A protective layer 60 is formed on the entire surface of the protective layer 60 to correspond to each pixel region A common electrode 65 having a plurality of openings oa spaced apart from each other and having a bar shape is formed.

The array substrate 41 for a conventional fringe field switching mode liquid crystal display having the above-described configuration has been completed through a total of five mask processes. That is, the array substrate 41 for a conventional fringe field switching mode liquid crystal display has the steps of forming the gate wiring (not shown) and the gate electrodes 108 and 43, the step of forming the active layer 46a and the A step of forming a semiconductor layer 46 composed of an ohmic contact layer 46b, a data line 47 and source and drain electrodes 49 and 51, a step of forming a pixel electrode 55, a step of forming a contact hole (not shown) And forming a common electrode 65 having a plurality of openings oa. The present invention has been accomplished on the basis of these findings.

The term " mask process " means a photolithography process. After a material layer for patterning is formed on a substrate, a photoresist layer having photosensitivity is formed on the substrate, an exposure mask having a light- Exposure to light, development of exposed photoresist layer, etching of the material layer using the remaining photoresist pattern, strip of photoresist pattern, and the like.

Therefore, in order to carry out one mask process, unit process equipments for each unit process and material for proceeding each unit process are required, and each process time is required through each unit process equipments.

Since the mask process has to process a plurality of unit processes as described above, the manufacturing cost and the time are increased. Therefore, each manufacturer of the liquid crystal display device can reduce the manufacturing cost of the array substrate and reduce the mask process We are making efforts for.

SUMMARY OF THE INVENTION The present invention has been conceived to solve the problems described above, and it is an object of the present invention to provide a fabrication method capable of manufacturing an array substrate for a fringe field switching mode liquid crystal display device by progressing a four mask process, thereby reducing manufacturing cost and improving productivity per unit time For that purpose.

According to another aspect of the present invention, there is provided a method of fabricating an array substrate for a fringe field switching mode liquid crystal display, including: forming a pixel region on a substrate having a transparent conductive material and a low- Layer gate electrode connected to the gate line in each of the pixel regions and forming a pixel electrode having a single layer structure made of the transparent conductive material in the pixel region; Selectively forming a gate insulating film on the gate wiring and the gate electrode; Forming a source electrode and a drain electrode spaced apart from the semiconductor layer in sequence on the gate insulating film in correspondence to the gate electrode, and forming a pixel region which is connected to the source electrode on the substrate and crosses the gate wiring, Forming a data line; Forming a protective layer over the source and drain electrodes and the data line; Forming a drain pixel contact hole exposing the pixel electrode at one end of the drain electrode and one end of the drain electrode by patterning the passivation layer and the gate insulating layer; A common electrode having a plurality of openings spaced apart from each other in the form of a bar corresponding to each of the pixel electrodes and a hole having a larger area than the drain pixel contact hole corresponding to the drain pixel contact hole are formed on the protective layer, And forming a pixel drain connection pattern that contacts the one end of the drain electrode and the pixel electrode at the same time and is spaced apart from the common electrode.

The forming of the gate wiring and the gate electrode of the double layer structure and the pixel electrode of the single layer structure may include sequentially forming a first transparent conductive material layer and a first metal layer on the substrate; Forming a first photoresist pattern of a first thickness over the first metal layer and a second photoresist pattern of a second thickness thinner than the first thickness; The gate wiring and the gate electrode having a bilayer structure are formed by removing the first metal layer exposed outside the first and second photoresist patterns and the first transparent conductive material layer below the first metal layer, Forming a dummy metal pattern thereon; Exposing the dummy metal pattern by ashing and removing the second photoresist pattern; Forming the pixel electrode of the single layer structure by removing the exposed dummy metal pattern; And removing the first photoresist pattern.

The step of selectively forming the gate insulating film on the gate wiring and the gate electrode includes the steps of forming a gate insulating material layer by applying a solubile material having positive photosensitivity over the gate wiring and the gate electrode, ; Performing back exposure to irradiate the back surface of the substrate on which the gate insulating material layer is formed with UV light without an exposure mask; Wherein the solubile material having the positive photosensitivity includes at least one of silicon oxide (SiO ₂ ), referred to as photo acryl or TRX, and silicon oxide And is a mixture of carbonate (SiC) and tetraethylene orthosilicate (TEOS).

The gate insulating film may be formed on the gate insulating film by heat treatment in a state where the gate insulating film is formed before the source and drain electrodes are formed on the gate insulating film to reflow the gate insulating film to cover the side surfaces including the gate wiring and the gate electrode. .

 A source electrode and a drain electrode are sequentially formed on the gate insulating film so as to be spaced apart from the semiconductor layer. The source electrode and the drain electrode are connected to the source electrode on the substrate and intersect the gate wiring, Forming a pure amorphous silicon layer, an impurity amorphous silicon layer and a second metal layer sequentially on the entire surface of the substrate over the gate insulating film; Forming a first photoresist pattern of a first thickness over the second metal layer and a second photoresist pattern of a second thickness thinner than the first thickness; The second metal layer exposed to the outside of the first and second photoresist patterns and the impurity and the pure amorphous silicon layer located under the second metal layer are removed to form the data line and the source drain pattern connected thereto, Forming an impurity amorphous silicon pattern and a pure amorphous silicon pattern under the pattern; Removing the second photoresist pattern by ashing to expose a central portion of the source drain pattern; Forming a source electrode and a drain electrode spaced apart from each other by removing the impurity amorphous silicon pattern located at a central portion and a lower portion of the exposed source drain pattern, and simultaneously forming the source electrode and the drain electrode spaced apart from the active layer of pure amorphous silicon Forming the semiconductor layer composed of the ohmic contact layer made of impurity amorphous silicon; And then performing a strip or ashing to remove the first photoresist pattern.

One end of the drain electrode overlaps with the pixel electrode.

The pixel drain connection pattern is formed to have a larger area than the drain pixel contact hole.

The plurality of openings and the data lines are formed symmetrically with respect to an imaginary line parallel to the gate lines at the central portion of the pixel region.

The array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention includes a gate wiring having a double layer structure of a transparent conductive material and a low resistance metal material formed on a substrate on which a pixel region is defined, A pixel electrode of a single layer structure made of the transparent conductive material formed on each pixel region on the substrate; A gate insulating film selectively formed on the gate wiring and the gate electrode; A source electrode and a drain electrode spaced apart from the semiconductor layer sequentially stacked on the gate insulating film in correspondence with the gate electrode; A data line formed on the substrate and defining the pixel region so as to intersect the gate line; And a drain pixel contact hole formed on the source and drain electrodes, the data line, and the pixel electrode, the drain pixel contact hole exposing the pixel electrode located at one end of the drain electrode and the periphery thereof; A common electrode formed to have a plurality of openings spaced apart in a bar shape and corresponding to the drain pixel contact hole and having a hole area larger than that of the drain pixel contact hole; And a pixel drain connection pattern formed in the hole and being in contact with one end of the drain electrode and the pixel electrode and spaced apart from the common electrode, and a protective layer is provided only between the pixel electrode and the common electrode to be.

In addition, a dummy semiconductor pattern made of the same material as the semiconductor layer is provided under the data line.

The gate insulating film is formed to cover the gate wiring and the upper and side surfaces of the gate electrode.

The material having the positive photosensitivity may be silicon oxide (SiO ₂ ), which is referred to as photo acryl or TRX, and silicon oxide (SiC) and tetraethylene orthosilicate (TEOS).

The array substrate for the fringe field switching mode liquid crystal display according to the present invention is completed by performing the mask process four times in total, thereby improving the productivity per unit time due to the reduction in the process number, further reducing material investment and unit process equipment investment, .

Further, since the pixel electrode is formed on the same layer on which the gate wiring is formed, the gate insulating film is omitted above the pixel electrode, so that only the protective layer is formed between the pixel electrode and the common electrode. Therefore, The field strength is relatively improved, so that it is possible to drive low power consumption, and further, the transmittance is improved.

In addition, the plurality of bar-shaped openings provided in each pixel region are symmetrically bent with respect to the center of each pixel region, so that each pixel region forms a double domain, There is an effect of providing a fringe field switching mode liquid crystal display device having a better display quality by suppressing the occurrence of an inversion phenomenon.

1 is a cross-sectional view schematically showing a part of a general transverse electric field type liquid crystal display device.
FIGS. 2A and 2B are cross-sectional views respectively showing the on and off states of a general transverse electric field liquid crystal display device;
3 is a cross-sectional view of a portion cut through a central portion of one pixel region of a conventional array substrate for a fringe field switching mode liquid crystal display.
FIGS. 4A through 4O are cross-sectional views illustrating a process for manufacturing a pixel region of an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention, in which a portion where a gate line and a data line cross each other is cut.
FIGS. 5A to 5C are cross-sectional views of a fabrication step for a portion where a pixel region, a portion where a gate wiring and a data wiring intersect each other, in an array substrate for a fringe field switching mode liquid crystal display according to a modification of the embodiment of the present invention After the formation of the gate wiring, the step of heat-treating the gate insulating film and the step of forming the data wiring over the gate insulating film.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIGS. 4A to 4O are cross-sectional views of a pixel region of the array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention, where a gate line and a data line cross each other. For convenience of description, a portion where the thin film transistor Tr as a switching element is formed in each pixel region P is defined as a switching region TrA.

4A, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on a transparent substrate 101 to form a first transparent conductive material layer A first metal material having a low resistance property such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), a copper alloy, or a metal alloy is formed on the first transparent conductive material layer 103, The first metal layer 105 is formed by depositing any one of molybdenum (Mo), molybdenum alloy (MoTi), copper (Cu), and copper alloy.

Next, a photoresist is coated on the first metal layer 105 to form a first photoresist layer (not shown).

Thereafter, an exposure mask (not shown) having a light transmission region, a semi-transmission region and a blocking region is placed on the first photoresist layer (not shown).

Next, the first photoresist layer (not shown) is exposed through the exposure mask (not shown) and then developed to form a region where the gate wiring (107 in Fig. 4B) and the gate electrode (108 in Fig. 4B) A first photoresist pattern 191a having a first thickness is formed for the pixel electrode (112 of FIG. 4B), and a second photoresist pattern 191a having a second thickness thinner than the first thickness 191b.

At this time, in the region other than the region where the gate wiring (107 of FIG. 4B), the gate electrode 108 (108 of FIG. 4B) and the pixel electrode (112 of FIG. 4B) Is removed to expose the first metal layer 105.

Next, as shown in FIG. 4B, the first metal layer (105 in FIG. 4A) exposed to the outside of the first and second photoresist patterns 191a and 191b and the first transparent conductive material (105 in FIG. 4A) and the underlying first transparent conductive material layer (105 in FIG. 4A) using an integrated etchant that reacts to both layers (103 and 105 in FIG. 4A) 103 in FIG. 4A) are simultaneously removed by etching.

As a result of such a process, a lower layer 107a (not shown) extending in one direction corresponding to the boundary of each pixel region P and the switching region TrA is formed under the first and second photoresist patterns 191a and 191b, A gate wiring 107 and a gate electrode 108 of a double-layer structure composed of upper and lower layers 107a and 108a and upper layers 107b and 108b made of a low-resistance metal material are formed.

The pixel region P is formed with a transparent conductive material having a plate shape spaced apart from the gate wiring 107 and the gate electrode 108 under the first and second photoresist patterns 191a and 191b, A dummy metal pattern 106 made of the low resistance metal material is formed on the electrode 112 and on the electrode 112.

As shown in FIG. 4C, ashing is performed to remove the second photoresist pattern (191b in FIG. 4B) located on the dummy metal pattern 106, so that the dummy metal pattern 106 is removed, Lt; / RTI > At this time, the first photoresist pattern 191a is also reduced in thickness by the ashing, but is still left on the gate wiring 107 and the gate electrode 108.

Next, as shown in FIG. 4D, the first photoresist pattern 191a is allowed to react with and etch the low resistance metal material while remaining on the gate wiring 107 and the gate electrode 108 The dummy metal pattern (106 in Fig. 4C) formed in each pixel region P is removed by exposing the dummy metal pattern (106 in Fig. 4C) to the etchant. The pixel electrode 112 is exposed by removing the dummy metal pattern 106 (FIG. 4C) by this series of processes.

4E, a strip or ashing is performed on the substrate 101 on which the pixel electrode 112 is formed, and the gate electrode 107 is formed on the gate electrode 107 and the gate electrode 108 The gate wiring line 107 and the gate electrode 108 are exposed by removing the remaining first photoresist pattern (191a in FIG. 4D).

Next, as shown in FIG. 4F, a material having a characteristic that a positive photosensitive property, that is, a light receiving portion is removed on development, over the gate wiring 107 and the gate electrode 108 and the pixel electrode 112 A solution state material in which silicon oxide (SiO ₂ ), silicon carbonate (SiC), and tetraethylene orthosilicate (TEOS) are appropriately mixed with a material called photo acryl or TRX having solubility characteristics A gate insulating material layer 114 is formed on the entire surface of the substrate 101. [ The gate insulating material layer 114 may be formed by a method such as spin coating or slit coating in view of characteristics of a material having solubility characteristics.

4G, a substrate 101 having a gate insulating material layer 114 formed on the entire surface of the substrate 101 over the gate line 107, the gate electrode 108 and the pixel electrode 112 Back exposure is performed by irradiating the entire surface of the substrate 101 with UV light on the back side without an exposure mask.

When the entire surface of the substrate 101 is exposed on the rear surface of the substrate 101, the gate wiring 107 and the gate electrode 108 having the upper layers 107b and 108b made of a low resistance metal material, which is opaque, The upper layers 107b and 108b block the UV light so that the UV light is not irradiated to the gate insulating material layer 114 located above the gate wiring 107 and the gate electrode 108 .

On the other hand, a portion where the pixel electrode 112 from which a dummy metal pattern (106 in FIG. 4C) is removed and a portion where the first transparent conductive material layer 103 (FIG. 4A) The UV light is transmitted through the gap between the gate wiring 107 and the pixel electrode 112 to reach the gate insulating material layer 114 located above the gate wiring 107 and the pixel electrode 112 do.

Next, as shown in FIG. 4H, a development process for exposing the layer of the gate insulating material (114 in FIG. 4G) made of an organic material having a positive photosensitive property exposed to the back without an exposure mask to the developer is performed.

Since the gate insulating material layer (114 in FIG. 4G) is made of an organic material having a positive photosensitive characteristic in view of the present invention, when the UV light is irradiated, the chain of adjacent molecules in the inside of the gate insulating material layer When exposed to the developing solution by this action, it dissolves in the developing solution and is removed. In the portion not irradiated with UV light, neighboring molecules keep the chains in a state of weaving, thereby not reacting with the developing solution. It does not melt.

4G) corresponding to a region other than the portion where the UV light is irradiated, that is, the portion where the gate wiring 107 and the gate electrode 108 are formed by the progress of the development process, So that the gate insulating film 115 is formed on the gate wiring 107 and the upper portion of the gate electrode 108. The gate insulating film 115 is formed on the pixel electrode 112 formed in each pixel region P, The gate insulating layer 115 is exposed.

 Next, as shown in FIG. 4I, pure amorphous silicon and impurity amorphous silicon are continuously deposited by replacing only the reaction gas using a CVD apparatus (not shown) on the gate insulating film 115 and the pixel electrode 112 Whereby a pure amorphous silicon layer 116 and an impurity amorphous silicon layer 117 are formed.

A second metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), a copper alloy, molybdenum (Mo), etc. is formed on the impurity amorphous silicon layer 117 using a sputtering device , Molybdenum alloy (MoTi), and chromium (Cr) is deposited to form a second metal layer (124). In this case, the second metal layer 124 has a single layer structure as an example.

Next, as shown in FIG. 4J, a photoresist is applied onto the second metal layer (124 of FIG. 4i) to form a second photoresist layer (not shown), and then a light transmission region and a semi- A third photoresist pattern 193a having a third thickness is formed by exposing and developing the second photoresist layer (not shown) through an exposure mask (not shown) having a blocking region, A fourth photoresist pattern 193b having a fourth thickness thinner than the third thickness is formed.

Thereafter, the second metal layer (124 in FIG. 4I) exposed at the outside of the third and fourth photoresist patterns 193a and 193b and the impurity amorphous silicon layer (117 in FIG. 4I) and the pure amorphous silicon layer A source drain pattern 125 is formed on the gate insulating film 115 in correspondence to the gate electrode 108 in the switching region TrA where a thin film transistor (Tr in FIG. 4O) And an impurity amorphous silicon pattern 119 and an active layer 120a of pure amorphous silicon are formed thereunder.

At the same time, a data line 130 is formed on the substrate 101 so as to intersect the gate line 107 to define the pixel region P. In this case, the first and second dummy patterns 121a and 121a are formed between the data line 130 and the substrate 101, respectively, and are completely overlapped with the data line 130, And a semiconductor dummy pattern 121 having a two-layer structure of the semiconductor layers 121a and 121b.

Such a double-layered semiconductor dummy pattern 121 plays an important role in the array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention.

That is, the gate insulating film 115 is formed only on the gate wiring 107 and the gate electrode 108. In this case, the side surface of the gate wiring 107 is electrically connected to the gate insulating film 115 As shown in FIG.

When the data line 130 is formed on the substrate 101 in this state, a portion where the gate line 107 intersects the data line 130 is electrically connected to the data line 130 And thus a short circuit may occur.

However, in the embodiment of the present invention, a semiconductor dummy pattern 121 made of the same material as the semiconductor layer 120 is formed under the data line 130 due to the characteristics of the manufacturing method. Since it plays a role of suppressing a short circuit between the gate wiring 107 and the data wiring 130 on the side of the gate wiring 107 and the data wiring 130.

Therefore, the semiconductor dummy pattern 121 located under the data line 130 will be a very important component due to manufacturing characteristics according to the embodiment of the present invention.

5A to 5C (a modification of the embodiment of the present invention), one pixel region, a gate line, and a data line in the array substrate for a fringe field switching mode liquid crystal display Referring to FIG. 5, there is shown a cross-sectional view of a portion where an intersecting portion is cut, showing only a step of heat treating a gate insulating film after forming a gate wiring and a step of forming a data wiring on the gate insulating film. Before the amorphous silicon layer 116 and the impurity amorphous silicon layer 117 and the second metal layer 124 are formed using the characteristic of the insulating film 115, the gate insulating film 115 is etched to a predetermined temperature atmosphere, for example, The gate insulating film 115 is reflowed by performing a heat treatment to expose the gate insulating film 115 to a temperature atmosphere of 80 DEG C to 120 DEG C, The step of covering the side surfaces of the gate wiring 107 and the gate electrode 108 may be further carried out.

When heat treatment is performed on the gate insulating film 115 in this way, melting due to the characteristic of the organic material occurs and the top surface of the gate wiring 107 and the gate electrode 108 is completely covered The second metal layer 124 may be formed and patterned to form the data line 130. The gate line may be formed under the data line 130 regardless of whether the semiconductor dummy pattern 121 is formed or not. A short circuit between the gate wiring 107 and the data wiring 130 on the side of the gate electrode 107 can be prevented originally.

Next, as shown in FIG. 4K, the center portion of the source drain pattern 125 is exposed by removing the fourth photoresist pattern (193b in FIG. 4J) having the fourth thickness by performing ashing. At this time, the third photoresist pattern 193a is also reduced in thickness by the ashing, but is still left on the substrate 101.

Next, as shown in FIG. 4L, the source / drain pattern (also shown in FIG. 4A) exposed to the outside of the third photoresist pattern 193a is dry-etched by using the third photoresist pattern 193a as an etching mask, The source and drain electrodes 133 and 136 are spaced apart from each other by removing the impurity amorphous silicon pattern (119 in FIG. 4k) The ohmic contact layer 120b of the impurity amorphous silicon having the same pattern shape is formed. At this time, the ohmic contact layer 120b, which is spaced apart from the active layer 120a, forms the semiconductor layer 120.

The drain electrode 136 is formed so that one end of the drain electrode 136 overlaps the pixel electrode 112 and the semiconductor layer 120 with each other therebetween.

The gate electrode 108 and the gate insulating film 115 sequentially stacked in the switching region TrA in each pixel region P and the semiconductor layer made of the active layer 120a and the ohmic contact layer 120b spaced apart from each other And the source and drain electrodes 133 and 136, which are spaced apart from each other, constitute a thin film transistor Tr which is a switching element.

Next, as shown in FIG. 4M, the third photoresist pattern (193a in FIG. 4L) remaining on the data line 130 and the source and drain electrodes 133 and 136 is transferred through a strip Thereby exposing the data line 130 and the source and drain electrodes 133 and 136.

Next, as shown in FIG. 4n, the thin film transistor (Tr) and the data line 130 to the top insulation to the front arms, for materials for example, depositing a silicon oxide (SiO ₂₎ or silicon nitride (SiNx), or an organic A protective layer 140 is formed by applying an insulating material such as benzocyclobutene (BCB) or photo acryl.

A drain pixel contact hole 143 exposing a portion of the pixel electrode 112 located around the drain electrode 136 and the drain electrode 136 by patterning the passivation layer 140 by a mask process, .

4O, the protective layer 140 having the drain pixel contact hole 143 exposing the pixel electrode 112 located at one end of the drain electrode 136 and the periphery of the drain electrode 136, A second transparent conductive material layer (not shown) is formed by depositing a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

Thereafter, the second transparent conductive material layer (not shown) is patterned through a mask process to form a plurality of openings oa spaced in a bar shape within each pixel region P and a plurality of openings oa spaced apart from the drain pixel contact holes A common electrode 160 having a hole h1 having a larger area than the drain pixel contact hole 143 corresponding to the common electrode 160 and the common electrode 160, The pixel electrode 112 is formed in the hole hl to have a larger area than the drain pixel contact hole 143 and smaller than the hole hl in correspondence to the hole 143, To form the pixel drain connection pattern 167 which is in contact with the pixel electrode 160. The fringe field switching mode liquid crystal display array substrate 101 according to the present invention is completed.

The array substrate 101 for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of data lines 130 and a plurality of common electrodes 160 provided in the common electrode 160, Although it is shown that the bar-shaped opening oa is formed in a straight line shape, a plurality of bar-shaped openings provided in each pixel region P, not shown in another modification, It may be formed symmetrically with respect to an imaginary line parallel to the gate wiring 107 across the central portion of the region P. [ In this case, the data line 130 is also symmetrically bent with respect to the center of each pixel region P, so that the entire display region can be formed in a zigzag shape.

The reason why the plurality of openings oa are symmetrically bent with respect to the center of each pixel region P is that each pixel region P has a double domain structure. In the case where each pixel region P has a dual domain, occurrence of a color reversal phenomenon is suppressed in accordance with a change in azimuth angle of the liquid crystal display device including the array substrate 101, Since the fringe field switching mode liquid crystal display device having the fringe field can be provided.

The array substrate 101 for a fringe field switching mode liquid crystal display manufactured by the manufacturing method according to the embodiment of the present invention as described above has the gate wiring 107, the data wiring 130, and the pixel electrode The gate wiring 107 and the data wiring 130 are formed on the substrate 101 in order to prevent a short circuit at a portion where the gate wiring 107 and the data wiring 130 intersect with each other. A gate insulating film 115 is provided between the wirings 130 and a semiconductor dummy pattern 121 is provided under the data wiring 130 in order to further prevent a short circuit. The gate insulating film (115 in FIG. 5C) provided on the gate wiring (107 in FIG. 5C) covers the side surface of the gate wiring 107. In this case, With this characteristic configuration, even if both the gate wiring (107 in Fig. 5C) and the data wiring (130 in Fig. 5C) are formed on the substrate (101 in Fig. 5C), short defects can be originally suppressed.

The array substrate 101 for the fringe field switching mode liquid crystal display manufactured by the manufacturing method according to the embodiment and the modification of the present invention is manufactured through a total of four mask processes. Thereby, the number of mask processes is reduced as compared with the array substrate (40 of FIG. 3) for a fringe field switching mode liquid crystal display manufactured through a conventional 5 or 6 mask process.

The array substrate 101 for the fringe field switching mode liquid crystal display manufactured by the manufacturing method according to the embodiment of the present invention is characterized in that the pixel electrode 112 is formed on the same substrate 101 as the gate wiring 107 A gate insulating layer 115 is formed on the gate line 107 while a gate insulating layer 115 is omitted on the pixel electrode 112.

Therefore, since only the passivation layer 140 is provided between the pixel electrode 112 and the common electrode 160 having a plurality of openings oa, a distance between the pixel electrode 112 and the common electrode 160 is reduced, The fringe field strength is improved and the low power consumption can be driven by such a structure.

Further, in the array substrate 101 for a fringe field switching mode liquid crystal display manufactured by the manufacturing method according to the embodiment and the modification of the present invention, the gate insulating film 115 is removed on the pixel electrode 112, .

The present invention is not limited to the above-described embodiments and modifications, and various changes and modifications can be made without departing from the spirit of the present invention.

101: (array) substrate 107: gate wiring
107a and 107b: a lower layer (of the gate wiring)
108: gate electrode
108a, 108b: a lower layer (of the gate electrode)
112: pixel electrode 115: gate insulating film
120: semiconductor layer 120a: active layer
120b: Ohmic contact layer 121: Semiconductor dummy pattern
121a: first dummy pattern 121b: second dummy pattern
130: data line 133: source electrode
136: drain electrode 140: protective layer
143: drain pixel contact hole 160: common electrode
167: pixel drain connection pattern hl: hole
oa: opening P: pixel area
Tr: thin film transistor TrA: switching region

Claims (15)

Layer structure of a transparent conductive material and a low-resistance metal material on a substrate on which a pixel region is defined, and a gate electrode of a double-layer structure connected to the gate wiring in each pixel region, Forming a pixel electrode having a single layer structure made of a transparent conductive material;
Selectively forming a gate insulating film on the gate wiring and the gate electrode;
Forming a source electrode and a drain electrode spaced apart from the semiconductor layer in sequence on the gate insulating film in correspondence to the gate electrode, and forming a pixel region which is connected to the source electrode on the substrate and crosses the gate wiring, Forming a data line;
Forming a protective layer over the source and drain electrodes and the data line;
Forming a drain pixel contact hole exposing the pixel electrode at one end of the drain electrode and one end of the drain electrode by patterning the passivation layer and the gate insulating layer;
A common electrode having a plurality of openings spaced apart from each other in the form of a bar corresponding to each of the pixel electrodes and a hole having a larger area than the drain pixel contact hole corresponding to the drain pixel contact hole are formed on the protective layer, Forming a pixel drain connection pattern in contact with one end of the drain electrode and the pixel electrode in the hole and spaced apart from the common electrode,
And a plurality of fringe field switching mode liquid crystal display devices.
The method according to claim 1,
Forming the gate wiring and the gate electrode of the double layer structure and the pixel electrode of the single layer structure,
Sequentially forming a first transparent conductive material layer and a first metal layer on the substrate;
Forming a first photoresist pattern of a first thickness over the first metal layer and a second photoresist pattern of a second thickness thinner than the first thickness;
The gate wiring and the gate electrode having a bilayer structure are formed by removing the first metal layer exposed outside the first and second photoresist patterns and the first transparent conductive material layer below the first metal layer, Forming a dummy metal pattern thereon;
Exposing the dummy metal pattern by ashing and removing the second photoresist pattern;
Forming the pixel electrode of the single layer structure by removing the exposed dummy metal pattern;
Removing the first photoresist pattern
And a plurality of fringe field switching mode liquid crystal display devices.
The method according to claim 1,
Wherein the step of selectively forming the gate insulating film on the gate wiring and the gate electrode comprises:
Applying a solubile material having a positive photosensitive property over the gate wiring and the gate electrode to form a gate insulating material layer;
Performing back exposure to irradiate the back surface of the substrate on which the gate insulating material layer is formed with UV light without an exposure mask;
Developing the back exposed layer of gate insulator material
And a plurality of fringe field switching mode liquid crystal display devices.
The method of claim 3,
The solubile material having the positive photosensitivity property may be,
Wherein the substrate is a material in which silicon oxide (SiO ₂ ), photo acryl or TRX, is mixed with silicon carbonate (SiC) and tetraethylene-ethylene orthosilicate (TEOS) Gt;
The method according to claim 1,
A step of performing heat treatment in a state in which the gate insulating film is formed before the source and drain electrodes are formed on the gate insulating film to reflow the gate insulating film to cover the side surfaces including the top surfaces of the gate wirings and the gate electrode Wherein the first and second fringe field switching mode liquid crystal display devices are arranged in a matrix.
The method according to claim 1,
Forming a source electrode and a drain electrode spaced apart from the semiconductor layer sequentially on the gate insulating film and forming the data line that is connected to the source electrode on the substrate and crosses the gate line to define the pixel region Lt; / RTI >
Forming a pure amorphous silicon layer, an impurity amorphous silicon layer and a second metal layer sequentially on the entire surface of the substrate over the gate insulating film;
Forming a first photoresist pattern of a first thickness over the second metal layer and a second photoresist pattern of a second thickness thinner than the first thickness;
The second metal layer exposed to the outside of the first and second photoresist patterns and the impurity and the pure amorphous silicon layer located under the second metal layer are removed to form the data line and the source drain pattern connected thereto, Forming an impurity amorphous silicon pattern and a pure amorphous silicon pattern under the pattern;
Removing the second photoresist pattern by ashing to expose a central portion of the source drain pattern;
Forming a source electrode and a drain electrode spaced apart from each other by removing the impurity amorphous silicon pattern located at a central portion and a lower portion of the exposed source drain pattern, and forming an active layer of pure amorphous silicon and an impurity Forming an ohmic contact layer of amorphous silicon on the semiconductor layer;
Removing the first photoresist pattern by conducting a strip or ashing,
And a plurality of fringe field switching mode liquid crystal display devices.
The method according to claim 1,
And one end of the drain electrode overlaps with the pixel electrode. The method of claim 1, wherein the drain electrode is formed to overlap with the pixel electrode.
The method according to claim 1,
Wherein the pixel drain connection pattern is formed to have a larger area than the drain pixel contact hole.
The method according to claim 1,
Wherein the plurality of openings and the data lines are formed so as to be symmetrically bent with respect to an imaginary line parallel to the gate lines at a central portion of the pixel region. The method of manufacturing an array substrate for a fringe field switching mode liquid crystal display .
A gate wiring having a double layer structure of a transparent conductive material and a low resistance metal material formed on a substrate on which a pixel region is defined, and a gate electrode connected to the gate wiring;
A pixel electrode of a single layer structure made of the transparent conductive material formed on each pixel region on the substrate;
A gate insulating film selectively formed on the gate wiring and the gate electrode;
A source electrode and a drain electrode spaced apart from the semiconductor layer sequentially stacked on the gate insulating film in correspondence with the gate electrode;
A data line formed on the substrate and defining the pixel region so as to intersect the gate line;
And a drain pixel contact hole formed on the source and drain electrodes, the data line, and the pixel electrode and exposing the pixel electrode located at one end of the drain electrode and the periphery of the drain electrode,
A common electrode formed on the passivation layer and having a plurality of openings spaced apart in a bar shape corresponding to the pixel electrodes and a hole having a larger area than the drain pixel contact hole corresponding to the drain pixel contact hole;
And a pixel drain connection pattern formed in the hole and being in contact with one end of the drain electrode and the pixel electrode,
And a protective layer is provided between the pixel electrode and the common electrode.
11. The method of claim 10,
And the dummy semiconductor pattern is in contact with a side surface of the gate wiring, wherein the dummy semiconductor pattern is made of the same material as the semiconductor layer under the data line.
11. The method of claim 10,
Wherein the gate insulating layer covers an upper portion and a side surface of the gate line and the gate electrode.
11. The method of claim 10,
Wherein the gate insulating layer is made of a material having a positive photosensitive property.
14. The method of claim 13,
The material having the positive photosensitivity may be,
Wherein the substrate is a material in which silicon oxide (SiO ₂ ), which is called photo acryl or TRX, is mixed with silicon carbonate (SiC) and tetraethylene ortho silicate (TEOS).
The method according to claim 1,
Forming a source electrode and a drain electrode spaced apart from the semiconductor layer sequentially on the gate insulating film and forming the data line that is connected to the source electrode on the substrate and crosses the gate line to define the pixel region Lt; / RTI >
And forming a dummy semiconductor pattern made of the same material as the semiconductor layer under the data line,
Wherein the dummy semiconductor pattern is in contact with a side surface of the gate wiring.

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