KR20070106885A - Apparatus for driving plasma display panel - Google Patents

Abstract

An apparatus for driving a plasma display panel is provided to design small capacitance by suppressing excessive stress in resistors using capacitors in a Y driving circuit. An apparatus for driving a plasma display panel includes first and second switches(M1,M2), a second capacitor(C2), a first resistor(R1), a first capacitor(C1) and a third switch(M3). The first and second switches are parallel-connected to scan electrodes of the plasma display panel. The second capacitor is parallel-connected between the other end of the first switch and the other end of the second switch. One end of the first resistor is connected to the other end of the switch and the other end thereof is connected to a fifth voltage stage. One end of the first capacitor is connected to the other end of the resistor and the other end thereof is connected to the other end of the second switch. One end of the third switch is connected to the other end of the first capacitor and the other end thereof is connected to a sixth voltage stage.

Description

Apparatus for driving plasma display panel

1 is a view schematically showing an electrode arrangement of a plasma display panel having a driving apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a driving apparatus of the plasma display panel having the electrode arrangement shown in FIG.

3 is a timing diagram illustrating an example of a driving signal applied to each electrode of the plasma display panel illustrated in FIG. 1.

4 is a circuit diagram illustrating a problem of a conventional driving device of a plasma display panel.

FIG. 5 is a circuit diagram showing a driving apparatus of the plasma display panel having the electrode arrangement shown in FIG.

The present invention relates to a driving apparatus for a plasma display panel, and more particularly, to a driving apparatus for a plasma display panel for inserting a capacitor into the driving circuit to improve circuit stability.

In recent years, the plasma display panel, which is attracting attention as a replacement of the conventional cathode ray tube display device, is discharged after a discharge gas is filled between two substrates on which a plurality of electrodes are formed. A phosphor formed in a pattern of is excited to emit visible light, thereby obtaining a desired image.

The apparatus for driving such a plasma display panel generally includes an image processor, a logic controller, an address driver, an X driver and a Y driver.

The image processor receives an external image signal and processes the image to output an internal image signal. The logic controller receives the internal image signal and outputs driving control signals for controlling driving signals applied to the address electrode lines, the scan electrode lines, and the sustain electrode lines. The address driver receives and processes an address signal from among driving control signals to generate a display data signal, and applies the generated display data signal to the address electrode lines. The X driving unit receives an X driving control signal from among the driving control signals, processes the X driving control signal, and applies it to the sustain electrode lines. The Y driving unit receives and processes the Y driving control signal from among the driving control signals and applies it to the scan electrode lines.

The Y driving unit includes a plurality of resistors, capacitors, diodes, and switches, and applies various signals to the scan electrode lines for operating the plasma display panel by switching operations of the plurality of switches. In this process, there is a problem that the Y driving unit can not perform a stable operation due to excessive stress on some resistance during the switching operation of the switch.

The present invention provides a driving apparatus of a plasma display panel which improves the stability of a circuit by inserting a capacitor into the Y driving circuit to reduce excessive stress caused by some resistance.

The present invention provides a driving device of a plasma display panel that outputs a driving signal for driving a plasma display panel, the first and second ends of which are connected in parallel to a scan electrode (first end of Cp) of the plasma display panel. switch; A second capacitor connected in parallel to the other end of the first switch and the other end of the second switch; A first resistor having one end connected to the other end of the first switch and the other end connected to the fifth voltage terminal Vsch; A first capacitor having one end connected to the other end of the first resistor and the other end connected to the other end of the second switch; And a third switch having one end connected to the other end of the first capacitor and the other end connected to the sixth voltage terminal Vscl.

In an embodiment, the fourth switch may be connected to an address electrode (second end of Cp) and a seventh voltage end (Va) of the plasma display panel. And a fifth switch connected to the address electrode Cp of the plasma display panel and the ground voltage terminal Vg.

In the present invention, a first current path including the fourth switch, the plasma display panel, the first switch, the first resistor, and the third switch may be formed in the address period.

In the present invention, a second current path including the first capacitor, the first resistor, the second capacitor, the first switch, the plasma display panel, and the fifth switch may be formed in the address period. have.

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the embodiments shown in the accompanying drawings.

1 is a view schematically showing an electrode arrangement of a plasma display panel having a driving apparatus according to an embodiment of the present invention.

Referring to FIG. 1, an electrode structure of a plasma display panel includes scan electrode lines and sustain electrode lines disposed in parallel to a horizontal direction of the panel, and perpendicularly cross the scan electrode lines and sustain electrode lines. There are address electrode lines arranged. A portion where the scan electrode line, the sustain electrode line, and the address electrode line cross each other defines a discharge cell Ce, and the discharge cell Ce serves as a pixel of the plasma display panel. In the space of the discharge cell Ce, there are R, G, and B phosphors and a plasma forming gas, and wall charges are discharged inside the discharge cell Ce by the voltage applied to each of the scan electrode, the sustain electrode, and the address electrode. Is generated. Plasma is formed from the plasma forming gas by the wall charge, and phosphors of the discharge cells Ce are excited by ultraviolet radiation from the plasma to generate light.

Between the front and rear glass substrates of a conventional plasma display panel, address electrode lines A1, A2, ..., Am, dielectric layer, scan electrode lines Y1, ..., Yn, sustain electrode line (X1, ..., Xn), a fluorescent layer, a partition, and a magnesium monoxide (MgO) protective layer are provided.

The address electrode lines A1, A2, ..., Am are formed in a predetermined pattern on the front side of the rear glass substrate. The lower dielectric layer is applied in front of the address electrode lines A1, A2, ..., Am. In front of the lower dielectric layer, barrier ribs are formed in a direction parallel to the address electrode lines A1, A2, ..., Am. These partitions partition the discharge area of each display cell and serve to prevent optical interference between each display cell. The fluorescent layer is applied in front of the dielectric layer on the address electrode lines A1, A2, ..., Am between the partition walls, and the red light emitting fluorescent layer, the green light emitting fluorescent layer, and the blue light emitting fluorescent layer are sequentially disposed.

The sustain electrode lines X1, ..., Xn and the scan electrode lines Y1, ..., Yn are formed so as to be orthogonal to the address electrode lines A1, A2, ..., Am. It is formed in a constant pattern on the back. Each intersection sets a corresponding display cell. Each sustain electrode line (X1, ..., Xn) and each scan electrode line (Y1, ..., Yn) have conductivity and transparent electrode line (Xna, Yna) of transparent conductive material such as ITO (Indium Tin Oxide) Metal electrode lines (Xnb, Ynb) to increase the can be formed by combining. The front dielectric layer is formed by applying the entire surface to the back of the sustain electrode lines X1, ..., Xn and the scan electrode lines Y1, ..., Yn. A protective layer for protecting the panel from strong electric fields, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface behind the front dielectric layer. The plasma forming gas is sealed in the discharge space.

The driving method generally applied to the plasma display panel is a method in which the reset, address and sustain discharge steps are sequentially performed in the unit sub-field. In the reset step, the charge states of the display cells to be driven are made uniform. In the address step, the charge state of display cells to be selected and the charge state of display cells not to be selected are set. In the sustain discharge step, display discharge is performed in the display cells to be selected. At this time, a plasma is formed from the plasma forming gas of the display cells which perform the display discharge, and the fluorescent layers of the display cells are excited by ultraviolet radiation from the plasma to generate light.

It should be noted that the method of driving the plasma display panel according to the present invention is not limited to the plasma display panel having the above structure, and can be applied to all plasma display panels having the three-electrode structure.

FIG. 2 is a block diagram showing a driving apparatus of the plasma display panel having the electrode arrangement shown in FIG.

Referring to FIGS. 1 and 2, a driving device for driving a plasma display panel includes an image processor 200, a logic controller 202, an address driver 206, an X driver 208, and a Y driver 204. It includes.

The image processor 200 receives an external image signal and performs image processing to output an internal image signal. The internal image signals include 8-bit red (R), green (G), and blue (B) image data, clock signals, and vertical and horizontal sync signals, respectively.

The logic controller 202 receives the internal image signal from the image processor 200 and undergoes gamma correction, automatic power control (APC), and the like, and scans the address electrode lines A1, A2,. Outputs drive control signals SA, SY, and SX for controlling drive signals applied to each of the electrode lines Y1, ..., Yn and sustain electrode lines X1, ..., Xn. .

The address driver 206 receives and processes the address signal SA from the driving control signals SA, SY, and SX from the logic controller 202 to generate a display data signal, and generates the display data signal. It is applied to the electrode lines A1, A2, ..., Am.

The X driver 208 receives and processes the X driving control signal SX from the driving control signals SA, SY, and SX from the logic controller 202 to process the sustain electrode lines X1,..., Xn. To apply.

The Y driver 204 receives and processes the Y driving control signal SY from the driving control signals SA, SY, and SX from the logic controller 302 to scan electrode lines Y1,..., Yn. To apply.

3 is a timing diagram illustrating an example of a driving signal applied to each electrode of the plasma display panel illustrated in FIG. 1.

Referring to FIG. 3, one subfield has a reset period PR, an address period PA, and a sustain discharge period PS, and address electrode lines A1, A2, ..., Am, and sustain electrode. The driving signal is applied to the lines X1, X2, ..., Xn and the scan electrode lines Y1, ..., Yn, respectively.

First, in the reset period PR, reset pulses are applied to all of the scan electrode lines Y1,..., And Yn to forcibly perform a write discharge, thereby initializing the wall charge states of all the cells. The reset period PR is performed before entering the address period PR, which is carried out over the entire screen, thus making it possible to create a wall distribution of wall charges with a fairly even and desired distribution. The cells initialized by the reset period PR have similar wall charge conditions inside the cells.

For this purpose, in the reset period PR, the ground voltage Vg is first applied to the scan electrode lines Y1, ..., Yn. Next, the sustain discharge voltage Vs, which is the first voltage, is rapidly applied at a time t1, and a rising ramp signal is applied from the time t1 to t2 so that the rising voltage Vset is a second voltage than the first voltage Vs. It increases and reaches the 3rd voltage, the highest rising voltage (Vset + Vs). Next, a first voltage Vs is applied at time t2, and a falling ramp signal is applied at time t2 to t3 to reach the fourth falling voltage, Vnf. The erase pulse is applied to the sustain electrode lines X1, ..., Xn until time t1, and then the ground voltage Vg is applied from time t1 to t2, and the bias voltage is an eighth voltage from time t2 to t3. (Vb) is applied. The ground voltage Vg is applied to the address electrode lines A1, A2, ..., Am during the reset period PR.

In order to select a cell to be turned on during the address period PA, that is, from time t3 to time t4, the scan high voltage Vsch is first applied to the scan electrode lines Y1, ..., Yn. After being applied, a scan pulse having a scan low voltage Vscl, which is a sixth voltage, is sequentially applied to each scan electrode line. A display data signal having an address voltage Va, which is a seventh voltage, is applied to the address electrode lines A1, A2, ..., Am in accordance with the scan pulse. The eighth voltage Vb is continuously applied to the sustain electrode lines X1,..., Xn.

In the sustain discharge period PS, the sustain discharge voltage Vs and the ground voltage Vg are applied to the scan electrode lines Y1, ..., Yn and the sustain electrode lines X1, ..., Xn. Holding pulses are alternately applied. The ground voltage Vg is applied to the address electrode lines A1, A2, ..., Am.

In detail, the first voltage Vs is rapidly applied at the time t1 to the scan electrode lines Y1,..., And Yn in the reset period PR. A rising ramp signal is applied from t1 to t2 to reach the third voltage Vset + Vs that is increased by the second voltage Vset. The first initialization discharge occurs while the rising ramp signal is applied. The first initialization discharge is a weak discharge generated by the application of a rising ramp signal having an insignificant slope, and the negative discharge starts to accumulate in the vicinity of the scan electrode lines Y1,..., And Yn. . At a time t2, the voltage drops rapidly to the first voltage, and a falling ramp signal is applied from the time t2 to the time t3 to finally reach the fourth voltage Vnf. The second initialization discharge is generated while the falling ramp signal is applied. The second initialization discharge is a weak discharge generated by the application of a falling ramp signal having an insignificant slope, and part of the negative charges accumulated near the scan electrode lines Y1,... Is released. In the reset period PR, a negative charge appropriate for generating an address discharge remains near the scan electrode lines Y1, ..., Yn, and the address electrode lines A1, A2, ..., Am ) A positive amount of positive charge will remain.

In the address period PA, an address discharge occurs to select a cell to be turned on. Once the fifth voltage Vsch is applied to the scan electrodes, scan pulses having the sixth negative voltage Vscl are sequentially applied to the scan electrode lines, and the address electrode lines A1, A2, ..., ... Am) is applied with a display data signal having a seventh voltage Va in accordance with the scan pulse. That is, the seventh voltage Va applied to the address electrode A, the sixth voltage Vscl applied to the scan electrode Y, the wall voltage and the address electrode due to the negative charge in the vicinity of the scan electrode Y ( A) The address discharge is performed inside the discharge cell by the wall voltage caused by the positive charge in the vicinity. After the address discharge is performed, positive charges are accumulated in the vicinity of the scan electrode Y, and negative charges are accumulated in the vicinity of the sustain electrode X.

In the sustain discharge period PS, a sustain discharge occurs in a cell selected in the address period PA. First, when the first voltage Vs is applied to the scan electrode Y and the ground voltage Vg is applied to the sustain electrode X, the first voltage Vs applied to the scan electrode Y and the sustain voltage are maintained. The primary sustain discharge is performed inside the discharge cell by the ground voltage Vg applied to the electrode X, the positive charge near the scan electrode Y and the negative charge near the sustain electrode X. After the first sustain discharge is performed, negative charges accumulate near the scan electrodes Y, and positive charges accumulate near the sustain electrodes X. Next, when the ground voltage Vg is applied to the scan electrode Y and the first voltage Vs is simultaneously applied to the sustain electrode X, the first voltage Vs applied to the sustain electrode X and the first voltage Vs are applied. The second sustain discharge is performed inside the discharge cell by the ground voltage Vg applied to the scan electrode Y, the positive charge near the sustain electrode X and the negative charge near the scan electrode Y. Next, the first voltage Vs is applied to the scan electrode Y, and the ground voltage Vg is applied to the sustain electrode x, and the above process is repeated. In this way, the sustain pulse is alternately applied to the scan electrode Y and the sustain electrode X, and sustain discharge is continuously performed.

4 is a circuit diagram illustrating a problem of a conventional driving device of a plasma display panel.

In FIG. 4, the panel capacitor Cp represents the capacitance of the plasma display panel. The scan electrode Y is connected to the first end of the panel capacitor Cp, and the address electrode A is connected to the second end of the panel capacitor Cp.

First, referring to the configuration of the Y driver 204 of FIG. 2, the first switch M1 and the second switch M2 are connected in parallel to the first end of the panel capacitor Cp. The other end of the first switch M1 is connected in parallel with the first resistor R1 and the first diode D1. The second resistor R2 and the second diode D2 are connected in series between the fifth voltage terminal Vsch, the first resistor R1, and the first diode D1. The first capacitor C1 and the third resistor R3 are connected in parallel between the second switch M2, the first resistor R1, and the first diode D1. The third switch M3 is connected between the sixth voltage terminal Vscl, the first capacitor C1, and the third resistor R3.

Next, referring to the configuration of the address driver 206 of FIG. 2, the fourth switch M4 is connected between the second terminal of the panel capacitor Cp and the seventh voltage terminal Va, and the panel capacitor Cp The fifth switch M5 is connected between the second terminal and the ground voltage terminal Vg.

In the address period PA, when the sixth voltage Vscl is applied to the scan electrode Y and the seventh voltage Va is applied to the address electrode V, the fourth switch M4 and the panel capacitor ( A current path like? Is formed in Cp, the first switch M1, the first diode D1, the first capacitor C1, and the third switch M3.

When the fourth switch M4 is turned on in the same current path as 1), the panel capacitor Cp is momentarily shorted to increase the voltage at the point A to the seventh voltage Va. In this case, since the first switch M1 is also turned on, the point B is also increased by the point A, so that a situation in which the internal voltage of the first switch M1 is exceeded may occur. The first diode D1 is mounted to prevent the voltage rise of the first switch M1 and to conduct the current caused by the switching in a short time, thereby preventing the voltage rise. The resistance value of is lower than 10 Ω so that too much current flows through the first resistor R1.

In the address period PA, when the fifth voltage Vsch is applied to the scan electrode Y and the ground voltage Vg is applied to the address electrode V, the first capacitor C1 and the first resistor ( A current path like? Is formed in R1, the first switch M1, the panel capacitor Cp, and the fifth switch M5.

In the case where the fourth switch M4 is turned off and the fifth switch M5 is turned on in the current path as described above, the panel capacitor Cp is also turned on momentarily so that the voltages of the points A and B fall. At this time, all of the current flowing through the first resistor R1 causes excessive stress on the first resistor R1.

As shown in FIG. 4, when the switching operation of the fourth switch M4 and the fifth switch M5 is large, excessive stress is applied to the first resistor R1 by the switching current, and thus, a plurality of first resistors ( Since R1) must be connected in parallel and its capacity must be large, it is disadvantageous in terms of cost, and there is a problem that the main path pattern may be insufficient in configuring a driving board. Therefore, while reducing the stress of the resistance is required to operate as a stable drive while reducing the cost.

FIG. 5 is a circuit diagram illustrating a driving apparatus of a plasma display panel having an electrode arrangement shown in FIG. 1 to solve the above problem shown in FIG. 4.

In FIG. 5, the panel capacitor Cp represents the capacitance of the plasma display panel. The scan electrode Y is connected to the first end of the panel capacitor Cp, and the address electrode A is connected to the second end of the panel capacitor Cp.

The basic circuit configuration is the same as that of FIG. 4, but FIG. 5 removes the first diode D1 from FIG. 4 and adds a second capacitor C2 having good high frequency characteristics.

First, looking at the configuration of the Y driver 204, one end of the first switch M1 and one end of the second switch M2 are connected in parallel to the first end of the panel capacitor Cp. The first resistor R1, the second diode D1, and the second resistor R2 are connected in series between the other end of the first switch M1 and the fifth voltage terminal Vsch. A second capacitor C2 is connected in parallel to the other end of the first switch M1 and the other end of the second switch M2. The first capacitor C1 and the third resistor R3 are connected in parallel between the other end of the first resistor R1 and the other end of the second switch M2. The third switch M3 is connected between the sixth voltage terminal Vscl, the first capacitor C1, and the third resistor R3.

Next, referring to the configuration of the address driver 206 of FIG. 2, the fourth switch M4 is connected between the second terminal of the panel capacitor Cp and the seventh voltage terminal Va, and the panel capacitor Cp The fifth switch M5 is connected between the second terminal and the ground voltage terminal Vg.

In the address period PA, when the sixth voltage Vscl is applied to the scan electrode Y and the seventh voltage Va is applied to the address electrode V, the fourth switch M4 and the panel capacitor ( A current path as in? Is formed in Cp, the first switch M1, the second capacitor C2, the first resistor R1, the third resistor R3, and the third switch M3. .

When the fourth switch M4 is turned on in the current path as in?, The panel capacitor Cp is momentarily shorted to increase the voltage at the point A to the seventh voltage Va. In this case, since the first switch M1 is also turned on, the point B is also increased by the point A, so that a situation in which the internal voltage of the first switch M1 is exceeded may occur. The second capacitor C2 is provided to prevent the voltage rise. The second capacitor C2 bypasses the switching currents of the fourth switch M4 and the first switch M1 so that the switching current of the pure DC component flows through the first resistor R1. Therefore, the first resistor R1 may reduce excessive stress. In addition, since the capacitance of the second capacitor C2 is lower than that of the panel capacitor Cp, even when the panel capacitor Cp is momentarily turned on to increase the voltage at the points A and B, the second capacitor C2 Since the recovery to the normal state after a while does not cause a problem of exceeding the internal pressure of the first switch (M1).

In the address period PA, when the fifth voltage Vsch is applied to the scan electrode Y and the ground voltage Vg is applied to the address electrode V, the first capacitor C1 and the first resistor ( A current path like? Is formed in R1, the second capacitor C2, the first switch M1, the panel capacitor Cp, and the fifth switch M5.

When the fourth switch M4 is turned off and the fifth switch M5 is turned on in the current path as described above, the switching current is supplied by the second capacitor C2 to supply the first resistor R1 with pure water. Since only DC and current flow, stress can be reduced as compared with the first resistor R1 shown in FIG. 4. In addition, the voltage drop of the panel capacitor Cp is also smaller than that of the circuit shown in FIG. 4 due to the characteristics of the second capacitor C2.

Therefore, not only the circuit can be stably driven but also the number of the first resistors R1 can be reduced, and the capacity thereof can be designed small, so that a chip type resistor other than metal oxide can be used. You can either reduce the size or get more main path patterns. In addition, the use of capacitors that are cheaper than diodes enables cost reduction.

The present invention, by inserting a capacitor in the Y drive circuit to reduce the excessive stress generated in some resistance to create an effect that can improve the circuit stability. In addition, the number of resistors constituting the Y driving circuit can be reduced, and the capacity of the capacitor can be designed to be small, thereby reducing the size of the driving board and reducing the cost cost.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (4)

A driving device of a plasma display panel for outputting a driving signal for driving a plasma display panel, First and second switches having one end connected in parallel to a scan electrode Cp of the plasma display panel; A second capacitor connected in parallel to the other end of the first switch and the other end of the second switch; A first resistor having one end connected to the other end of the first switch and the other end connected to the fifth voltage terminal Vsch; A first capacitor having one end connected to the other end of the first resistor and the other end connected to the other end of the second switch; And And a third switch having one end connected to the other end of the first capacitor and the other end connected to the sixth voltage terminal (Vscl). The method of claim 1, A fourth switch connected to an address electrode (second end of Cp) and a seventh voltage end (Va) of the plasma display panel; And And a fifth switch connected to an address electrode (second end of Cp) and a ground voltage terminal (Vg) of the plasma display panel. The method of claim 2, wherein in the address period, And a fourth current path including the fourth switch, the plasma display panel, the first switch, the first resistor, and the third switch. The method of claim 2, wherein in the address period,  And a second current path including the first capacitor, the first resistor, the second capacitor, the first switch, the plasma display panel, and the fifth switch.

Images