KR20070104137A - Ldpc encoder - Google Patents

Abstract

An LDPC(Low Density Parity Check) encoder is provided to calculate plural parity bits using a single block manipulation process by using a triangular matrix. An LDPC encoder includes a manipulation processor(910), an adder module(920), a memory(930), a first scheduler(940), a second scheduler(950), and a controller(960). The manipulation processor processes a systematic part in a parity check matrix. The adder module accumulates the output from the manipulation processor. The memory stores the output from the adder module. The first scheduler performs a data process on a result from the memory. The second scheduler performs the data process on the output from the adder module according to a structure of the parity check matrix. The controller controls the schedulers.

Description

LDPC encoder {LDPC encoder}

1 is a view showing the structure of a mobile communication channel to which the present invention and the prior art are applied.

2 is a diagram for explaining structured LDPC.

3 is a view showing a model matrix according to the prior art.

4 is a diagram illustrating a method of expressing a matrix according to a shift number.

5 is a diagram illustrating an LDPC decoding method.

FIG. 6A is a diagram illustrating a parity bit calculator for calculating parity bits of a parity check matrix having a dual diagonal component.

6B is a diagram illustrating a structure of an encoding apparatus which simultaneously processes a plurality of bits according to the present embodiment.

7A shows the structure of a general model matrix.

7B is a diagram showing the structure of a model matrix used by the encoding apparatus according to the present embodiment.

8 is a diagram showing an example of a model matrix according to the present embodiment.

9 is a diagram illustrating an example of an encoding apparatus 900 that performs encoding by using the model matrix of FIG. 8.

FIG. 10 is a diagram for describing an encoding operation according to a parity part including a double diagonal component having a shift number of zero.

FIG. 11 is a diagram for describing an encoding operation according to a parity part including a double diagonal component having a shift number of any integer.

12 is a diagram illustrating an encoding operation according to a parity portion formed of a double diagonal component having a shift number of any integer.

13A to 13C are diagrams showing parity portions of the model matrix according to the present embodiment.

14A to 14D are diagrams for describing an operation of the encoding apparatus according to the present embodiment.

The present invention relates to LDPC (Low Density Parity Check) encoding and decoding, and more particularly, to an encoding apparatus using a parity check matrix for converting an information word into a code word through a simple process.

1 is a view showing the structure of a mobile communication channel to which the present invention and the prior art are applied. Hereinafter, the structure of a mobile communication channel will be described with reference to FIG. 1. In order to transmit the data to be transmitted from the transmitter without loss or distortion in the radio channel, a channel coding procedure is performed. As the channel coding technique, there are various techniques such as convolutional coding, turbo coding, and LDPC coding. Data that has undergone the channel coding procedure may be transmitted as a single symbol by collecting a plurality of bits when transmitted through a wireless channel. In this case, a procedure in which several bits are mapped to one symbol is called modulation.

The modulated data is converted into a signal for multiplex transmission through a multiplexing process or a multiple access method. As the multiplexing method, various methods such as CDM, TDM, and FDM exist. In FIG. 1, an example of orthogonal frequency division multiplexing (OFDM) is illustrated. The signal that has passed through the multiplexing block is changed into a structure suitable for transmission to one or more multiple antennas and transmitted to a receiver through a radio channel. Data transmitted in the course of passing through the wireless channel may experience fading and thermal noise, which may cause distortion of the data.

The modulated data is transmitted to a receiver through a wireless channel. In this process, the transmitted data may experience fading and thermal noise, which may cause distortion of the data. After receiving the distorted data, the receiving end performs a series of procedures in the reverse order. A demodulation operation of converting the data mapped to the symbol into a bit string is performed, and the distorted data is restored to the original data through a channel decoding process.

The apparatus for performing channel coding generates a parity check derived from an H matrix or an H matrix, which is a parity check matrix used to generate parity bits to be added to input data (Systematic Bits). It stores G matrix, which is a parity check generate matrix. That is, the transmitting end includes an encoder for generating parity bits through the H or G matrix and the input data. The apparatus for performing channel decoding checks whether the inputted data (Systematic Bits) are properly recovered through the H matrix and the operation of the received data (distorted Systematic Bits + Parity Bits). Rerun

The modulation includes Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), Quadrature Amplitude Modulation (16-QAM), 64-QAM, 256-QAM, and the like. For example, 16-QAM maps a sequence of data that has undergone a channel encoding procedure to one symbol in units of 4 bits during modulation. In demodulation, 16-QAM demaps one symbol of data received through a wireless channel into four bits.

Hereinafter, the LDPC code will be described. The concept of the LDPC code is as follows.

을 만족하도록 부호가 구성된다는 점이다. 이 선형 부호의 일종으로서, 최근에 주목받는 LDPC 부호는 1962년 Gallager에 의하여 처음 제안되었다. 이 부호의 특징으로는 패리티 체크 행렬의 성 분이 대부분 0으로 이루어지고, 0이 아닌 성분의 개수는 부호 길이에 비하여 적은 수를 가지도록 하여 확률을 기반으로 한 반복적 복호가 가능한 점이다. 처음 제안된 LDPC 부호는 패리티 체크 행렬을 비체계적인(non-systematic) 형태로 정의하였고, 그것의 행과 열에 균일하게 적은 무게(weight)를 갖도록 설계되었다. The linear code can be described by the generation matrix G or parity check matrix H. The characteristic of linear code is that for all codewords c,

The sign is constructed to satisfy. As a form of this linear code, a recent notable LDPC code was first proposed by Gallager in 1962. The feature of this code is that the components of the parity check matrix are mostly 0, and the number of nonzero components is smaller than the code length, so that it is possible to perform iterative decoding based on probability. The first proposed LDPC code defines the parity check matrix in a non-systematic form and is designed to have a uniformly low weight in its rows and columns.

Here, the weight means the number of 1s included in a column or a row in the matrix.

Since the density of nonzero components on the parity check matrix H of the LDPC code is small, the decoding complexity is low. In addition, the decoding performance is also better than the existing codes, showing a good performance close to Shannon's theoretical limit. The LDPC code, however, was a hardware technology that was difficult to implement at the time and has not attracted much attention for more than 30 years. In the early 1980s, a method of iterative decoding using a graph was developed, and various algorithms were developed to actually decode the LDPC code using the graph. The sum-product algorithm can be extracted as the representative algorithm.

Hereinafter, the features of the LDPC code will be described. LDPC codes have high error correction performance, which allows for improvements in communication speed and capacity. The LDPC code may be applied to a high speed wireless LAN capable of transmitting hundreds of Mbit / s in combination with a multiple input multiple output (MIMO) system, and may be applied to high speed mobile communication having a transmission speed of 1 Mbit / s or more at 250 km / h. It can also be applied to optical communication of 40Gbits / s or more. In addition, the high error correction performance of the LDPC code may improve the transmission quality, thereby enabling quantum encrypted communication that reduces the number of retransmissions in a low quality communication path. In addition, due to the low complexity and excellent loss compensation of the LDPC code, lost packets can be easily recovered, which makes it possible to transmit content of the same quality as TV quality through the Internet and mobile communication. Due to the wide coverage and large capacity of LDPC, 10GBASE-T transmissions up to the 100m range, previously considered impossible, are possible with LDPC codes. At the same time, the transmission capacity of a single satellite transmitter in the 36MHz band can be increased by 1.3 times to 80Mbit / s. These advantages are being adopted as the next generation channel coding method in IEEE802.16 system and IEEE802.11 system for high frequency efficiency.

The structured LDPC is described below.

In order to use the LDPC code includes a matrix H to use, uses a parity check matrix H is most 0 and part of one of the components (elemnet), the H matrix, since the size of the H matrix size by more than 10 ⁵ bits It requires a large amount of memory to represent. The structured LDPC technique is a method of expressing components of the H matrix used for LDPC encoding and decoding into sub-blocks having a constant size as shown in FIG. 2. In IEEE802.16e, the subblock is represented by one integer index to reduce the size of memory required to store the H matrix. The subblock may be various matrices, for example, a permutation matrix of a constant size.

In the structured LDPC technique, instead of storing a matrix of 1 or 0 in a specific memory, only one integer (that is, an index) needs to be stored. Can be reduced.

For example, when the size of the codeword reflected in the IEEE802.16e standard is 2304 and the code rate is 2/3, the model matrix used for LDPC encoding / decoding is shown in FIG. Same as 3.

As shown in Fig. 3, the structured LDPC matrix of IEEE802.16e consists of -1, 0 and positive integer components. -1 is a zero matrix of all elements 0 and 0 represents an identity matrix. Positive integer components other than -1 and 0 are permutation matrices in which the identity matrix is shifted to the right by a positive integer. That is, if the component of the matrix is 3, the permutation matrix is expressed by shifting the unit matrix three times to the right.

4 is a diagram illustrating a method of expressing a matrix according to the aforementioned positive integer, that is, a shift number. When a specific H matrix is structured and expressed as a matrix having a size of 4 * 4 (that is, a sub block), if the specific sub block is denoted as 3, the sub block becomes the matrix of FIG.

Hereinafter, the LDPC encoding method will be described.

A general LDPC encoding method derives a generation matrix G from an LDPC parity check matrix H and encodes an information bit. In order to derive the generation matrix G, the inspection matrix H is configured in the form of [P ^T : I] through a Gaussian Reduction method. When the number of information bits is k and the size of an encoded codeword is n, the P matrix is a matrix in which the number of rows is k and the number of columns is nk, and I is K is the identity matrix whose k column size is k.

The generation matrix G becomes a [I: P] matrix when the check matrix H is expressed as [P ^T : I]. If the encoded information bits of k-bit size are represented in a matrix, the number of rows is 1 and the number of columns is k. In this case, the code word c is described as follows.

In the above equation, x denotes a systematic part and xP denotes a parity part.

)을 이용하여, 상기 수학식 1에서 H^T을 곱하면, 하기 수학식 2 같은 수학식을 얻을 수 있다. 하기 수학식 2에 부합하는 패리티 비트를 정보 비트(x) 뒤에 추가하여 코드워드 c를 얻을 수 있다. On the other hand, in the case of encoding by the Gaussian Reduction method as described above, a large amount of calculation is performed, and a method of directly encoding the H matrix without inducing the G matrix by designing the shape of the H matrix into a special structure. Use That is, H ^{T in the} form of a transpose of the G matrix and the H matrix. The property that the product of is 0 (that is,

By multiplying H ^T by Equation 1, Equation 2 can be obtained. A codeword c may be obtained by adding a parity bit corresponding to Equation 2 after the information bit x.

Hereinafter, the LDPC decoding method will be described.

The coded data in the communication system includes noise in the process of passing through the wireless channel of FIG. 1, and the receiving end performs decoding of the data through the procedure of FIG. 5. The decoding block of the receiving end obtains the information bit (x) from the received signal (c ') with noise added to the coded code (c), and finds it using the property of cH ^T = 0. That is, when the received codeword is c ', the value of c'H ^T is calculated, and if the result is 0, the first k bits in c' are determined as the information bits x. If the value of c'H ^T is not 0, a decoding technique such as a sum-product algorithm through a graph is used to find c 'whose value of c'H ^T satisfies 0. recover (x)

Hereinafter, the code rate of the LDPC code will be described.

In general, a code rate (R) is as follows when the size of the information bit is k and the size of the codeword actually transmitted is n.

R = k / n

The code rate is as follows when the row size of the H matrix required for LDPC encoding and decoding is m and the size of the column is n.

R = 1-m / n

As described above, the conventional LDPC code is encoded and decoded by the H matrix, and thus the structure of the H matrix is very important. That is, since the performance of encoding and decoding is greatly affected by the structure of the H matrix, the design of the H matrix is most important.

It is proposed to improve the above-described prior art of the present invention, and an object of the present invention is to propose an encoding device with improved performance compared to the prior art.

Another object of the present invention is to propose an encoding apparatus for generating parity bits using a parity check matrix having improved complexity due to encoding.

The present invention calculates a plurality of parity bits in parallel to improve performance over the prior art. More specifically, the encoding apparatus according to the present invention performs encoding using a parity check matrix composed of subblocks having a specific size (z * z). In addition, the present invention calculates a parity bit in the sub-block unit. That is, parity bits corresponding to the size of the row or column of the subblock are calculated at one time.

In addition, the encoding apparatus according to the present invention is characterized by performing parallel processing on a parity check matrix of a lower triangle type. The encoding apparatus according to the present invention may reduce the complexity of encoding by using the parity check matrix of the lower triangle type.

In the LDPC encoding method according to the present invention, a method of encoding information bits using a parity check matrix, the LDPC encoding method comprising: a plurality of first information bits determined by a structure of a first region of an information word portion of the parity check matrix; Calculating first parity bits; And calculating a plurality of second parity bits by accumulating the second information bits and the first parity bits determined by the structure of a second region of the information word portion.

In addition, the LDPC encoding apparatus according to the present invention is a device for performing encoding using a parity check matrix generated from a model matrix consisting of sub-blocks, the information bit according to the structure of the information word portion of the parity check matrix. An information word partial calculating unit configured to output a plurality of operation values by performing an operation on the input unit; And a parity bit calculator configured to perform data processing on the output according to the structure of the parity portion of the parity check matrix, and generate a plurality of parity bits by accumulating the result of the data processing.

In addition, the data scheduler used in the encoding apparatus according to the present invention inputs a plurality of operation values obtained by adding information bits or a plurality of operation values obtained by adding the information bits and parity bits according to the structure of the parity check matrix. And perform data processing on the operation values according to the structure of the parity portion of the parity check matrix.

The construction, operation and effects of the present invention will be embodied by one embodiment of the present invention described below. Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

Hereinafter, a matrix representing a parity check matrix as a subblock having a specific z * z size according to the structured LDPC described above is referred to as a model matrix. Each sub block of the model matrix may be extended to various kinds of matrices by a specific index, and the model matrix has the index as a component of the model matrix. Each sub block of the model matrix may be determined in various ways according to the index. Hereinafter, it is assumed that the index is a shift number for a unit matrix of a specific size z * z. In addition, when the index is -1, the sub block having the index of -1 is a zero matrix of a specific size z * z.

The model matrix is extended to a specific parity check matrix according to the index, so that encoding and decoding are performed by the model matrix, and that encoding and decoding is performed by a specific parity check matrix generated by the model matrix. it means.

FIG. 6A is a diagram illustrating a parity bit calculator for calculating parity bits of a parity check matrix having a dual diagonal component. The parity bit calculator accumulates a result value generated according to a structure of an information word part of the parity check matrix and outputs a parity bit. That is, the parity bit calculator is an accumulator.

6B is a diagram illustrating a structure of an encoding apparatus which simultaneously processes a plurality of bits according to the present embodiment. The encoding apparatus according to the present embodiment includes an operation unit 610 that calculates encoded information bits according to a structure of a parity check matrix, and a parity calculator 620 that calculates a parity bit by accumulating the result values of the operation unit. The parity calculator 620 accumulates the output value of the calculator using a feedback structure. In addition, the parity calculator 620 preferably accumulates a specific number of result values simultaneously. The number of result values accumulated at the same time is determined according to the structure of the parity check matrix used by the encoding apparatus. The parity check matrix is composed of subblocks of a specific size (z * z). The parity check matrix performs z-parity through one data process by parallelizing a result value corresponding to the size (z) of a row or column of the subblock. Output a bit. That is, operations on one sub block are processed at the same time. The data processor stores or shifts data according to the structure of the double diagonal component of the parity check matrix.

The data processor performs a specific operation according to the structure of the parity check matrix (or a parity check matrix extended by a specific model matrix), which will be described in detail below. Since the encoding apparatus of FIG. 6B preferably performs an encoding operation using a parity check matrix of a lower triangle type (including a parity check matrix extended by a model matrix of a lower triangle type), the following operation is performed. The concept of the lower triangle will be described and the operation accordingly.

Hereinafter, the concept of the upper triangle will be described to explain the concept of the lower triangle, followed by the concept of the lower triangle.

7A shows the structure of a general model matrix. Each integer indicated in FIG. 7A represents an index, and an unmarked portion has an index of -1. The model matrix of FIG. 7A is largely comprised of a systematic part and a parity part. That is, the model matrix of FIG. 7A has a structure of [H _d : H _p ], where H _d is an information word portion corresponding to an information bit encoded by the model matrix in a 1: 1 ratio. , H _p is a parity portion for generating a parity bit included in the coded codeword.

As shown, a general model matrix has a dual diagonal component in the parity portion. However, the conventional double diagonal component is composed of one diagonal component and a component adjacent to the diagonal component as shown. The adjacent component is also located at the upper of the diagonal component. In other words, the adjacent component is located to the right of the diagonal component. The up, down, left, and right sides of the components of the matrix are variable depending on the direction of viewing the matrix. The matrix of FIG.

The model matrix is referred to as [H _d : H _p ], the row of sub blocks in the parity portion of FIG. 7A is r, the column is represented by c, and the number of shifts for a specific sub block is A _{r , c} . In this case, the indexes A _{r and c} have 0 when r = c and when c = r + 1. In addition, the remaining indexes A _{r and c} have −1. That is, when the parity portion of the model matrix of FIG. 7A has 16 subblocks, the parity portion is determined as shown in Equation 5 below.

The parity portion of the model matrix or the parity check matrix can be divided into various types according to the design method of the double diagonal component. The parity portion designed by the method of the model matrix of FIG. 7A has an upper triangle type. Expressed as designed accordingly.

7B is a diagram showing the structure of a model matrix used by the encoding apparatus according to the present embodiment. The model matrix of FIG. 7B is largely composed of an information word part and a parity part. That is, the model matrix of FIG. 7B has a structure of [H _d : H _p ], where H _d is an information word portion corresponding to an information bit encoded by the model matrix in a 1: 1 ratio. , H _p is a parity portion for generating a parity bit included in the coded codeword. There is no limitation in the method of configuring H _d , and details of the information word are not shown in FIG. 7B.

The model matrix of FIG. 7B also has a dual diagonal component. The double diagonal component of FIG. 7B consists of one diagonal component and the component adjacent to the diagonal component, as shown. However, the adjacent component is located at the lower end of the diagonal component. In other words, the adjacent component is located to the left of the diagonal component. The up, down, left, and right of the components of the matrix are variable depending on the direction of viewing the matrix. The model matrix according to the present embodiment is described in another way as follows.

The model matrix is called [H _d : H _p ], the row of sub blocks in the parity portion of FIG. 7B is r, the column is represented by c, and the number of shifts for a specific sub block is A _{r , c} . In this case, the index A _{r , c} has any integer that is not -1 when r = c and r = c + 1. That is, when the parity portion of the model matrix of FIG. 7B has 16 subblocks, the parity portion may be determined as shown in Equation 6 below.

In the above formula, x _i and y _i represent an arbitrary integer. The parity portion of the model matrix or parity check matrix can be divided into various types according to the design method of the double diagonal component. The parity portion designed in the same manner as the model matrix of FIG. 7B is a 'lower triangle type'. Expressed as designed according to

Hereinafter, a method of performing encoding by using the matrix of the lower triangle type will be described. The type of the lower triangular type is various, and a method of performing encoding using the model matrix of FIG.

When the model matrix of FIG. 8 is referred to as H _b , the H _b is composed of an information word, that is, an information word part H _b1 corresponding to the information bit one-to-one and a parity part H _b2 . The model matrix is summarized as follows.

K _b represents the number of subblocks corresponding to the information word in the model matrix of FIG. 8. In addition, the m _b is the number of sub-blocks located in the column direction in the model matrix. That is, the information word portion of the model matrix has a size of m _b * k _b when expressed in units of sub-blocks. In addition, the parity portion of the model matrix has a size of m _b * m _b when expressed in units of sub-blocks.

The codeword x generated by H _b includes an information bit s and a parity bit p, and is represented by the following formula.

As described above, the model matrix H _b is composed of sub blocks of size z * z. In addition, the encoding apparatus using H _b processes data in units of z. That is, for encoding, information bits s are grouped into k _b groups by z bits. The information bits s grouped into k _b groups are represented as vectors as shown in Equation 9 below.

In Equation 9, u (i) is a column vector of size z * 1.

According to this embodiment, z-bit parity bits are output at a time. The parity bits output by the encoding apparatus according to the present embodiment are represented by a column vector v (i) having a size z * 1. Can be. This can be summarized as Equation 10 below.

As shown in Equation 10, the parity is composed of m _b vectors, and each vector includes z bits of parity bits.

는 패리티 부분에 위치하는 서브 블록으로부터 확장되어 생성되는 행렬을 나타낸다. 예를 들어,

이라면, 특정한 모델 행렬의 첫 번째 행과 첫 번째 열에 위치하는 서브 블록을 나타내는 것이다. 상기 수학식 11a에서도 알 수 있듯이, 전체 패리티 비트 중 첫 번째 열 벡터(즉, 전체 패리티 비트 중 최초 z비트)는, 상기 첫 번째 열 벡터에 상응하는 정보어 부분(systematic part)에 대한 연산 결과이다. 두 번째 열 벡터는, 상기 두 번째 열 벡터에 상응하는 정보어 부분에 대한 연산 결과와 상기 첫 번째 열 벡터를 이용하여 계산된다. 이러한 내용을 정리하면, 패리티 비트를 산출하는 과정은 상기 수학식 11b와 같은 재귀적 방법으로 표현될 수 있다. In the above equation,

Denotes a matrix generated by extending from a subblock located in the parity portion. E.g,

, The subblock at the first row and first column of a particular model matrix. As can be seen from Equation 11a, the first column vector of all parity bits (ie, the first z bits of all parity bits) is an operation result of an information part corresponding to the first column vector. . The second column vector is calculated using the result of the calculation of the information word portion corresponding to the second column vector and the first column vector. In summary, the process of calculating the parity bits may be represented by a recursive method as shown in Equation 11b.

9 is a diagram illustrating an example of an encoding apparatus 900 that performs encoding by using the model matrix of FIG. 8. 9 illustrates an example of the encoding apparatus of FIG. 6B in more detail.

As shown, the encoding apparatus 900 includes an arithmetic processing unit 910 for performing arithmetic operations on an information word portion of a parity check matrix, a summation module 920 for cumulatively summing outputs of the arithmetic processing unit, and A memory 930 for storing the output of the summing module 920, a first scheduler 940 for performing data processing on a result value output from the memory, and the parity check matrix for the output of the summing module 920 A second scheduler 950 for performing data processing according to the structure of the structure, and a controller 960 for performing overall scheduling and operation control of the encoding device.

The operation processing unit 910 performs an operation on the information word portion of the parity check matrix generated by extending from the model matrix of FIG. 8. The fact that there are various calculation methods for the information word part is obvious to those skilled in the art. An operation method on the information word portion of the parity check matrix will be described below.

이고, 두 번째 결과값은

이고, 세 번째 결과값은,

이고, 네 번째 결과값은,

이다. 상기 결과값은 z개이므로, z개 단위로 병렬처리된다.If the information word portion is represented by [0 1 3 0] and the size z of the subblock constituting the model matrix is 4, the model matrix may be extended like the parity check matrix H of Equation 12. The information word portion of Equation 12 corresponds to sixteen information bits a ₀ to a ₁₅ . Accordingly, four result values are generated when the arithmetic operation is performed on the information word portion. In other words, the first result is

And the second result is

And the third result is

And the fourth result is

to be. Since the result value is z, it is processed in parallel in units of z.

The operation processor 910 outputs the result value of the z bits to the summing module 920. In the initial stage, since there is no stored value in the memory 930, a result value corresponding to the z bits is output to the second scheduler 950. Detailed operations of the second scheduler 950 will be described later. When the model matrix of FIG. 8 is used, the second scheduler 950 outputs an input as it is. The output of the second scheduler 950 is the first parity vector v (0) for the information bits.

The result value of the z bits is also transferred to and stored in the memory 930. The size of the memory 930 is preferably z bits. In addition, the stored data of the memory 930 is output to the first scheduler 940. Detailed operations of the first scheduler 940 will be described later. When the model matrix of FIG. 8 is used, the first scheduler 940 does not perform a shift operation.

The controller 960 instructs an operation on the information word portion through the operation processor 910, and performs an operation on the information word portion corresponding to the second parity vector v (1). The result of the performed operation has a size of z bits, and is output to the sum module 920 at one time. The sum module 920 includes information corresponding to the first parity vector v (0). A result of adding the result value for the fish portion and the result value for the information word portion corresponding to the second parity vector v (1) is performed (for example, an XOR operation). The summed result is also z data and is output at once to the second scheduler 950 and the memory 930. As described above, the second scheduler 950 still outputs an input value without data processing, and outputs a second parity vector v (1). The new value is stored in the memory 930, and the stored value is summed with the result of operation on the information word portion corresponding to the third parity vector v (2). If the above-described method is repeated, the parity vector from v (0) to v (m _b -1) can be obtained, and finally, the total parity bit can be obtained. The above is the encoding operation described in the above equation (11b).

Hereinafter, operations of the first scheduler 940 and the second scheduler 950 will be described.

The first and second schedulers are used to adjust the order of the summed data when specific data are summed according to the structure of the parity portion. In order to generate a specific parity bit, specific data bits are summed according to the structure of the double diagonal component of the model matrix according to the lower triangle type. The scheduler determines the summed data bits and adjusts the order of the summed result. That is, the scheduler performs data processing so that the bits to be summed are mapped correctly, and performs data processing so that the bits are output in the order required when outputting the parity bits.

There is no limit to the number of the scheduler. In the example of FIGS. 10 to 12, two schedulers are used. Since the scheduler adjusts the order in which data bits are mapped, the scheduler may be implemented through a device such as a shift register. 10 to 12, an example of implementing the scheduler through the shift register will be described.

FIG. 10 is a diagram for describing an encoding operation according to a parity part including a double diagonal component having a shift number of zero.

와 같은 패리티 부분을 구비한 모델 행렬을 이용하여 부호화를 수행한다. 상기 행렬

은, 전체 패리티 부분의 일부일 수 있는바, 설명의 편의를 위해 상기 행렬

를 기초로 하여 동작을 설명한다. 상기 모델 행렬은 패리티 검사 행렬로 확장되는바, 서브 블록의 크기가 4*4인 경우에 도시된 바와 같이 확장된다. 도시된 바와 같이, 패리티 비트 p₀ 내지 p₇은 상기 패리티 검사 행렬의 구조에 의해 산출된다. 보다 구체적으로는, 각 패리티 비트에 상응하는 정보어 부분에 대한 연산 값과 상기 패리티 검사 행렬의 패리티 부분의 구조에 따라 상기 패리티 비트가 결정된다. 상술한 바와 같이, 상기 패리티 비트는 4(=z) 비트 단위로 산출되는바, 현재 상태는 p₀ 내지 p₃은 산출되어 상기 메모리(930)에 저장된 상태다. As shown, in the example of FIG.

The encoding is performed using a model matrix having a parity portion as shown in FIG. The matrix

May be part of an entire parity part, for convenience of description the matrix

The operation will be described on the basis of the following. The model matrix is extended with a parity check matrix, as shown in the case where the size of the subblock is 4 * 4. As shown, parity bits p ₀ to p ₇ are calculated by the structure of the parity check matrix. More specifically, the parity bit is determined according to the operation value for the information word portion corresponding to each parity bit and the structure of the parity portion of the parity check matrix. As described above, the parity bit is calculated in units of 4 (= z) bits, and the current state is a state in which p ₀ to p ₃ are calculated and stored in the memory 930.

The first shift register 940 performs a shift operation by the control unit 960. The control unit 960 analyzes a structure of the parity check matrix and performs the first shift through the structure. Controls the operation of the register 940. More specifically, the component of 1001 and the component of 1002 are compared to determine how much shift is to be performed. In FIG. 10, since the component of 1001 and the component of 1002 are the same value, the shift is not performed.

The output of the first shift register 940 is output to the summing module 920. The adding module 920 adds the fourth to seventh result values with the result values of p ₀ to p ₃ , respectively. The sum result is input to the second shift register 950. The controller 960 analyzes the structure of the parity check matrix and controls the operation of the second shift register 950 through the structure. More specifically, the shift number is determined according to how much the shift number of 1005 is shifted compared to the identity matrix. In the case of FIG. 10, the component of 1005 represents an identity matrix, and thus no shift is performed. As a result, the summed result is determined by parity bits of p ₄ to p ₇ .

The zeroth to seventh result values shown represent operation values for information bits in the information word portion corresponding to p ₀ to p ₇ parity bits. The method for obtaining the result value may be based on Equation 12.

As shown on the right side of FIG. 10, parity bit p ₄ is determined by an operation between the fourth result value and parity bit p ₀ . The relationship between each variable is explained by leader 1003. In the case of the parit bit p ₅ , it is determined by the operation between the fifth result value and the parity bit p ₅ . The relationship between each variable is described by leader 1004.

10 is only a diagram for illustrating an example of the present invention, and the present invention is not limited to FIG. 10. That is, when the first shift register and the second shift register do not perform any operation, an encoding apparatus in which the shift register is excluded may be used.

FIG. 11 is a diagram for describing an encoding operation according to a parity part including a double diagonal component having a shift number of any integer.

를 포함하는 패리티 부분을 구비한 모델 행렬을 이용하여 부호화를 수행한다. 상기 모델 행렬은 패리티 검사 행렬로 확장되는바, 서브 블록의 크기가 4*4인 경우 도시된 바와 같이 확장된다. 도시된 바와 같이, 패리티 비트 p₀ 내지 p₇은 상기 패리티 검사 행렬의 구조에 따라 산출된다. 보다 구체적으로는, 각 패리티 비트에 상응하는 정보어 부분에 대한 연산 값과 상기 패리티 검사 행렬의 패리티 부분의 구조에 따라 상기 패리티 비트가 결정된다. 상술한 바와 같이, 상기 패리티 비트는 4(=z) 비트 단위로 산출되는바, 현재 상태는 p₀ 내지 p₃은 산출되어 상기 메모리(930)에 저장된 상태다. As shown, in the example of FIG.

Encoding is performed using a model matrix having a parity portion including. The model matrix is extended with a parity check matrix, and as shown in the case where the size of the subblock is 4 * 4. As shown, parity bits p ₀ to p ₇ are calculated according to the structure of the parity check matrix. More specifically, the parity bit is determined according to the operation value for the information word portion corresponding to each parity bit and the structure of the parity portion of the parity check matrix. As described above, the parity bit is calculated in units of 4 (= z) bits, and the current state is a state in which p ₀ to p ₃ are calculated and stored in the memory 930.

The first shift register 940 performs a shift operation by the control unit 960. The control unit 960 analyzes a structure of the parity check matrix and performs the first shift through the structure. Controls the operation of the register 940. More specifically, by comparing the components of 1101 and 1102 of Figure 11, it is determined how much shift to perform. In FIG. 11, since the components of 1101 and 1102 differ from each other by one, the first shift register 940 may perform a shift operation of one. That is, the values stored in the order of p ₀ , p ₁ , p ₂ , and p ₃ are output as p ₁ , p ₂ , p ₃ , and p ₀ . The output of the first shift register is input to the summing module 920 and added to the fourth to seventh result values.

The summing module 920 sums the fourth result value and p ₁ , sums the fifth result value and p ₂ , sums the sixth result value and p _3, and sums the seventh result value and p ₀ . do. The sum result is input to the second shift register 950. The controller 960 analyzes the structure of the parity check matrix and controls the operation of the second shift register 950 through the structure. As described above, the operation of the second shift register 950 is controlled according to the number of shifts for the 1103 component. In the case of FIG. 11, since the number of shifts for the component of 1103 is 0, the shift is not performed. As a result, the summed result is determined by parity bits of p ₄ to p ₇ . As shown on the right side of FIG. 11, parity bit p ₄ is determined by an operation between the fourth result value and parity bit p ₁ . The relationship between the above-described variables p ₁ , p ₄ and the fourth result is described by the leader line 1104. In the case of the parit bit p ₇ , it is determined by the operation between the seventh result value and the parity bit p ₀ . The relationship between the above-described variables p ₀ , p ₇ , and seventh resultant value is described by the leader line 1105.

11 is only a diagram for illustrating an example of the present invention, and the present invention is not limited to FIG. 11. That is, when the second shift register does not perform any operation, an encoding apparatus including only the first shift register may be used.

12 is a diagram illustrating an encoding operation according to a parity portion formed of a double diagonal component having a shift number of any integer.

와 같은 패리티 부분을 구비한 모델 행렬을 이용하여 부호화를 수행한다. 상기 모델 행렬은 패리티 검사 행렬로 확장되는바, 서브 블록의 크기가 4*4인 경우 도시된 바와 같이 확장된다. 도시된 바와 같이, 패리티 비트 p₀ 내지 p₇은 상기 패리티 검사 행렬의 구조에 따라 산출된다. 보다 구체적으로는, 각 패리티 비트에 상응하는 정보어 부분에 대한 연산 값과 상기 패리티 검사 행렬의 패리티 부분의 구조에 따라 상기 패리티 비트가 결 정된다. 상술한 바와 같이, 상기 패리티 비트는 4(=z) 비트 단위로 산출되는바, 현재 상태는 p₀ 내지 p₃은 산출되어 상기 메모리(930)에 저장된 상태다. As shown, in the example of FIG.

The encoding is performed using a model matrix having a parity portion as shown in FIG. The model matrix is extended with a parity check matrix, and as shown in the case where the size of the subblock is 4 * 4. As shown, parity bits p ₀ to p ₇ are calculated according to the structure of the parity check matrix. More specifically, the parity bit is determined according to the operation value for the information word portion corresponding to each parity bit and the structure of the parity portion of the parity check matrix. As described above, the parity bit is calculated in units of 4 (= z) bits, and the current state is a state in which p ₀ to p ₃ are calculated and stored in the memory 930.

The first shift register 940 performs a shift operation by the control unit 960. The control unit 960 analyzes a structure of the parity check matrix and performs the first shift through the structure. Controls the operation of the register 940. More specifically, the component of 1201 and the component of 1202 are compared to determine how much shift is to be performed. In FIG. 12, since the components of 1201 and 1202 are the same, the shift operation is not performed. The output of the first shift register is input to the summing module 920 and added to the fourth to seventh result values.

p₀, 제5 결과값

p₁, 제6 결과값

p₂, 제7 결과값

p₃의 순서로 출력된 값은, 상기 제2 쉬프트 레지스터(950)에 의해, 제7 결과값

p₃, 제4 결과값

p₀, 제5 결과값

p₁, 제6 결과값

p₂의 순서로 출력된다. The sum result is input to the second shift register 950. The controller 960 analyzes the structure of the parity check matrix and controls the operation of the second shift register 950 through the structure. In FIG. 12, since the number of shifts for the component of 1203 is 1, the shift operation of 1 is performed. As a result, the fourth result

p ₀ , fifth result

p ₁ , the sixth result

p ₂ , seventh result

The value output in the order of p ₃ is the seventh result value by the second shift register 950.

p ₃ , fourth result

p ₀ , fifth result

p ₁ , the sixth result

The output is in the order of p ₂ .

As shown on the right side of FIG. 12, parity bit p ₅ is determined by an operation between the fourth result value and parity bit p ₀ . The relationship between the above-described variables p ₀ , p ₅ , and the fourth result is explained by the leader line 1204. In the case of the parit bit p ₆ , it is determined by the operation between the fifth result value and the parity bit p ₁ . The relationship between the above-described variables p ₁ , p ₆ , and fifth resultant value is described by the leader line 1205.

When encoding is performed by a specific model matrix, the above-described example of FIGS. 10 to 12 may be selectively performed.

13A is a diagram illustrating a parity portion of a model matrix according to the present embodiment. Region 1301 of FIG. 13A is the same as the parity portion described in FIG. 10. That is, when parity bits are generated using the parity portion of FIG. 13A, parity bits corresponding to the region 1301 may be generated according to the parity bit generation method described with reference to FIG. 10. In addition, since the region 1302 is the same as the parity portion described with reference to FIG. 10, the parity bit generation method described with reference to FIG. 10 may be used to generate a parity bit corresponding to the region 1302.

As described above, the first scheduler performs data processing according to the structure of the double diagonal component. More specifically, the shift operation is performed according to the shift number difference between the diagonal component and the component positioned below the diagonal component. In area 1303, since the diagonal component and the component positioned below the diagonal component are both '0', the first scheduler does not perform data processing. As described above, the second scheduler performs data processing according to the structure of the double diagonal component. More specifically, the shift operation is performed according to the shift number of the diagonal component. In the 1303 region, the second scheduler does not perform data processing because all diagonal components have a component corresponding to the unit matrix.

That is, when encoding is performed according to the model matrix of FIG. 13A, the first and second schedulers do not perform special data processing. In this case, an encoding apparatus except for the first and second schedulers may be used.

13B is a diagram illustrating a parity portion of a model matrix according to the present embodiment. Region 1311 of FIG. 13B is the same as the parity portion described in FIG. 10. That is, when parity bits are generated using the parity portion of FIG. 13B, parity bits corresponding to the 1311 region may be generated according to the parity bit generation method described with reference to FIG. 10. On the other hand, the 1312 region is the same as the parity portion described in FIG. Accordingly, the parity bit generation method described with reference to FIG. 11 may be used to generate parity bits corresponding to the 1312 region.

As described above, the first scheduler performs data processing according to the structure of the double diagonal component. More specifically, the shift operation is performed according to the shift number difference between the diagonal component and the component positioned below the diagonal component. In area 1312, since the diagonal component is '0' and the component positioned below the diagonal component is '1', the first scheduler performs a shift operation by one. As described above, the second scheduler performs data processing according to the structure of the double diagonal component. More specifically, the shift operation is performed according to the shift number of the diagonal component. In the 1312 region, since the diagonal components all have a component corresponding to the unit matrix with 0, the second scheduler does not perform data processing. Since region 1313 of FIG. 13B also has the same form as region 1312, only the first scheduler performs data processing.

In conclusion, when encoding is performed according to the model matrix of FIG. 13B, since the diagonal components are all zero, the second scheduler does not perform data processing. In this case, an encoding apparatus other than the second scheduler may be used.

13C is a diagram illustrating a parity portion of a model matrix according to the present embodiment. Region 1321 of FIG. 13C is the same as the parity portion described in FIG. 10. That is, when parity bits are generated using the parity portion of FIG. 13B, parity bits corresponding to the region 1321 may be generated according to the parity bit generation method described with reference to FIG. 10. Meanwhile, the region 1322 is the same as the parity portion described with reference to FIG. 12. Accordingly, the parity bit generation method described with reference to FIG. 12 may be used to generate parity bits corresponding to the region 1322.

의 구조를 갖기 때문에, 제1 스케쥴러가 데이터 처리를 수행한다. 즉, 첫 번째 대각 성분 '1'과 첫 번째 대각 성분 아래에 위치한 성분 '0'간에 -1 만큼의 쉬프트 수가 차이가 나기 때문에, 상기 제1 스케쥴러는 차이 나는 쉬프트 수에 상응하는 쉬프트 연산을 수행한다. 또한, 두 번째 대각 성분이 '0'이기 때문에 제2 스케쥴러는 쉬프트 연산을 수행하지 않는다. When generating parity bits corresponding to the 1323 region, the 1323 region is

Since it has a structure of, the first scheduler performs data processing. That is, since the number of shifts by -1 differs between the first diagonal component '1' and the component '0' located below the first diagonal component, the first scheduler performs a shift operation corresponding to the shift number. . Also, since the second diagonal component is '0', the second scheduler does not perform a shift operation.

의 구조를 갖기 때문에, 제1 스케쥴러가 데이터 처리를 수행한다. 즉, 첫 번째 대각 성분 '0'과 첫 번째 대각 성분 아래에 위치한 성분 '1'간에 1 만큼의 쉬프트 수가 차이가 나기 때문에, 상기 제1 스케쥴러는 차이 나는 쉬프트 수에 상응하는 쉬프트 연산을 수행한다. 또한, 두 번째 대각 성분이 '1'이기 때문에 제2 스케쥴러는 두 번째 대각 성분에 상응하는 만큼의 쉬프트 연산을 수행한다. When generating a parity bit corresponding to the 1324 region, the 1324 region is

Since it has a structure of, the first scheduler performs data processing. That is, since the number of shifts of 1 differs between the first diagonal component '0' and the component '1' located below the first diagonal component, the first scheduler performs a shift operation corresponding to the shift number. Also, since the second diagonal component is '1', the second scheduler performs a shift operation corresponding to the second diagonal component.

의 구조를 갖기 때문에, 제1 스케쥴러가 데이터 처리를 수행한다. 즉, 첫 번째 대각 성분 '1'과 첫 번째 대각 성분 아래에 위치한 성분 '0'간에 -1 만큼의 쉬프트 수가 차이가 나기 때문에, 상기 제1 스케쥴러는 차이 나는 쉬프트 수에 상응하는 쉬프트 연산을 수행한다. 또한, 두 번째 대각 성분이 '0'이기 때문에 제2 스케쥴러는 쉬프트 연산을 수행하지 않는다. When generating a parity bit corresponding to region 1325, region 1325 is

Since it has a structure of, the first scheduler performs data processing. That is, since the number of shifts by -1 differs between the first diagonal component '1' and the component '0' located below the first diagonal component, the first scheduler performs a shift operation corresponding to the shift number. . Also, since the second diagonal component is '0', the second scheduler does not perform a shift operation.

Since there is a double diagonal component of '0' in the region 1326, the first and second schedulers do not perform data processing.

In conclusion, when encoding is performed according to the model matrix of FIG. 13C, the first and second schedulers perform various data processing according to the structure of the double diagonal component.

Since the encoding apparatus according to the present invention can operate according to various types of lower triangle type model matrices, the present invention is not limited to the matrices of FIGS. 13A to 13C. For example, unlike the matrices of FIGS. 13A to 13C, encoding may be performed according to a model matrix of a lower triangle type having a shift number equal to or greater than '0' in components other than the double diagonal component.

을 이용하여 부호화를 수행하는 동작을 설명한다. 우선, 도 14a와 같이, 상기 모델 행렬은 패리티 검사 행렬로 확장된다. 상기 모델 행렬은 이중 대각 성분을 제외한 나머지 성분 중에 0 이상의 쉬프트 수를 갖는 성분(구체적으로 5번째 행과 5번째 영에 위치하는 '+1')을 갖는다. 도 14a에서, a₀ 내지 a₁₉는 정보어 부분에 따른 정보 비트 정보어 부분에 대한 연산 처리 결과값이다. 14A-14D are model matrices

The operation of performing encoding by using will be described. First, as shown in FIG. 14A, the model matrix is extended to a parity check matrix. The model matrix has a component having a shift number of 0 or more (specifically, '+1' located in the fifth row and the fifth zero) among the remaining components except the double diagonal component. In FIG. 14A, a ₀ to a ₁₉ are arithmetic processing result values for the information bit information word portion according to the information word portion.

When encoding is performed according to the model matrix, operations on regions 1401, 1402, 1403, and 1404 of the model matrix are sequentially performed.

14B illustrates an operation of generating parity bits for an area 1401. The operation of FIG. 14B is the same as the encoding operation of FIG. 13A described above. As shown in FIG. 14B, the first shift register and the second shift register operate according to the structure of the parity portion of the model matrix to output parity bits p ₀ , p ₁ , p ₂ , and p ₃ . As described above, when the first shift register and the second shift register do not need to operate, the shift registers may be omitted in the encoding apparatus.

The encoding apparatus of FIG. 14B preferably further includes a shift data processor 1400. When the specific model matrix has a shift number equal to or greater than '0' at a position other than the double diagonal component, the shift data processor 1400 performs data processing by acquiring already generated parity bits. Since the model matrix of FIG. 14A has a '1' component in the area 1405, when the operation on the area 1404 is performed, the operation on the area 1405 must be performed together. Accordingly, the shift data processor 1400 directly outputs an input without performing data processing in an area except the 1404 area.

14C illustrates an operation of generating parity bits for an area 1401. The operation of FIG. 14C is the same as the encoding operation of FIG. 13A described above. As shown in FIG. 14C, the first shift register and the second shift register operate according to the structure of the parity portion of the model matrix to output parity bits p ₄ , p ₅ , p ₆ , and p ₇ . As described above, when the first shift register and the second shift register do not need to operate, the shift registers may be omitted in the encoding apparatus.

As described above, when performing an operation on an area 1401, the shift data processor 1400 directly outputs an input without performing data processing.

By repeating the operations of FIGS. 14B to 14C, parity bits of p ₈ to p ₁₅ may be calculated. However, in order to calculate parity bits of p ₁₆ to p ₁₉ , additional data processing by the 1405 region is required. An operation of calculating the parity bits of p ₁₆ to p ₁₉ will be described with reference to FIG. 14D.

In order to calculate the parity bits of p ₁₆ to p ₁₉ , data processing according to the indicator line 1411 and the indicator line 1412 of FIG. 14A is required. That is, to generate p ₁₆ , the operations on a ₁₆ , p _1, and p ₁₂ must be performed. In addition, to generate p ₁₈ , operations on a ₁₈ and p ₃ and p ₁₄ must be performed. As a result, in order to calculate the parity bits of p ₁₆ to p ₁₉ , not only a ₁₆ to a ₁₉ outputted from the arithmetic processing unit 910 for the p ₁₂ to p ₁₅ and the information word portion already stored in the memory are already calculated. The value of completed p ₀ to p ₃ is required. After the shift data processor 1400 acquires the parity bits p ₀ , p ₁ , p ₂ , and p ₃ that have already been calculated according to the structure of the model matrix, the shift data processor 1400 performs data according to the shift number '1' in the region 1405 of FIG. 14A. Adjust the order to p ₁ , p ₂ , p ₃ , p ₀ . The shift data processor 1400 outputs a ₁₆ + p ₁₂ , a ₁₇ + p ₁₃ , a ₁₈ + p ₁₄ , a ₁₉ + p _15, and the adjusted data p ₁ , p ₂ of the summing module 920. , p ₃ , p ₀ are added together and output. Since the second shift register does not operate separately due to the structure of the parity check matrix, the output value is output as a parity bit.

The encoding device according to the present embodiment may include various devices according to the structure of the model matrix. That is, at least one data scheduler may be included depending on whether a component of the double diagonal component of the model matrix is shifted based on the unit matrix. In addition, when weight is present in components other than the double diagonal component, the apparatus may further include a data processor configured to calculate a new parity bit by performing data processing on the already processed parity bit.

In conclusion, according to a module included in the encoding apparatus according to the present invention, encoding may be performed on a model matrix having various shift numbers at positions other than the double diagonal component.

The first and second shift registers, the memory, the summation module, and the shift data processing unit of the encoding apparatus according to the present embodiment may perform the operations described above. The first shift register, the second shift register, the summation module, and the shift data processor may be implemented by various hardware or software.

The encoding apparatus according to the present exemplary embodiment performs an operation according to a structure of a model matrix and processes a plurality of data bits according to the size of a subblock constituting the model matrix, which shows an improved performance compared to the prior art.

Those skilled in the art through the above description can be seen that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Hereinafter, the effect of the present invention will be described.

The encoding apparatus according to the present invention has an advantageous effect of generating parity bits at high speed using a simple accumulator. In addition, when encoding is performed using a lower triangle type matrix, there is an advantageous effect of calculating a plurality of parity bits in one block operation without additional operations.

Claims (15)

In the method for encoding information bits using a parity check matrix, Calculating a plurality of first parity bits for first information bits determined by a structure of a first region of an information word portion of the parity check matrix; And Calculating a plurality of second parity bits by accumulating second information bits and the first parity bits determined by a structure of a second region of the information word portion; Method of encoding using a parity check matrix comprising a. The method of claim 1, The number of the first parity bits is equal to the number of the second parity bits. A method of encoding using a parity check matrix characterized in that. The method of claim 1, The parity check matrix is generated by extending from a model matrix consisting of subblocks of a specific size. A method of encoding using a parity check matrix characterized in that. The method of claim 3, The number of the first parity bits is equal to the size of the sub block. A method of encoding using a parity check matrix characterized in that. The method of claim 3, wherein calculating the first parity bits comprises: And adjusting the order of the first information bits according to a double diagonal component of the model matrix to calculate the first parity bits. The method of claim 3, wherein the calculating of the second parity bits comprises: And adjusting the order of the first parity bits and the order of the second information bits according to the double diagonal component of the model matrix to calculate the second parity bits. The method of claim 1, And the first information bits are information bits corresponding to a component having a weight in the first region. The method of claim 1, And the second information bits are information bits corresponding to a component having a weight in the second region. An apparatus for performing encoding using a parity check matrix generated from a model matrix consisting of subblocks, An information word partial operation unit configured to output a plurality of operation values by performing an operation on information bits according to a structure of the information word portion of the parity check matrix; And Perform data processing on the output according to the structure of the parity portion of the parity check matrix, A parity bit calculator configured to accumulate a result of the data processing to generate a plurality of parity bits LDPC encoding apparatus comprising a. The method of claim 9, The output of the information word portion calculating unit, LDPC encoding apparatus characterized in that the sum of the information bits corresponding to the weight (weight) of the information word portion. The method of claim 9, The parity bit calculator, A memory for storing an output of the information word partial calculator; And An adder module configured to add an output of the information word partial calculator and an output of the memory to output a parity bit; LDPC encoding apparatus comprising a. The method of claim 9, The parity bit calculator, A memory for storing an output of the information word partial calculator; A first shift register configured to perform a shift operation on the output of the memory according to the structure of the parity portion; A summing module for summing an output of the information word partial calculator and an output of the first shift register; And A second shift register configured to perform a shift operation on an output of the summing module according to the structure of the parity part LDPC encoding apparatus comprising a. A data processing apparatus for processing data used when encoding is performed according to a parity check matrix, Receiving a plurality of operation values obtained by adding information bits or a plurality of operation values obtained by adding the information bits and parity bits according to the structure of the parity check matrix, And perform data processing on the operation values according to a structure of a parity portion of the parity check matrix. The method of claim 13, The parity check matrix is characterized in that it is generated by extending from a specific model matrix, The data processing for the operation values is due to a shift operation by a difference between shift numbers of the double diagonal components of the model matrix. Features a data scheduler. The method of claim 13, The parity check matrix is characterized in that it is generated by extending from a specific model matrix, The data processing for the calculation values is based on a shift operation by the shift number of the diagonal component of the model matrix. Features a data scheduler.

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