KR101187072B1 - Method for encoding using parity check matrix - Google Patents

Abstract

The present invention relates to a low density parity check (LDPC) encoding method, and more particularly, to an apparatus for transmitting and receiving data using a parity check matrix for converting an information word into a code word through a simple process, and a modulation and demodulation method using the same. will be. According to an aspect of the present invention, there is provided a method of performing low density parity check (LDPC) encoding, comprising: determining a specific region of a parity check matrix used to encode an input bit; And encoding the input bit by the determined region, wherein the parity check matrix has a different density of weights of rows or columns included in the information word portion according to a predetermined number of the specific regions. It is done.

LDPC, parity check matrix, coding, weight, density, code rate

Description

Method for encoding using parity check matrix}

1 is a view showing the structure of a mobile communication channel to which the present invention and the prior art are applied.

2 is a diagram illustrating a structured LDPC.

3 is a diagram illustrating an example of a model matrix proposed in the related art.

4 is a diagram illustrating a concept of extending and generating a parity check matrix according to a shift number.

5 is a diagram illustrating an apparatus for decoding LDPC coded data according to the prior art.

6 is a diagram illustrating a concept of supporting various code rates through one mother matrix according to an example of the present invention.

7A and 7B are diagrams illustrating a mother matrix according to an embodiment of the present invention through a model matrix.

8 is a view showing a comparison of the performance of one embodiment of the present invention and the prior art.

The present invention relates to a low density parity check (LDPC) encoding method, and more particularly, to an apparatus for transmitting and receiving data using a parity check matrix for converting an information word into a code word through a simple process, and a modulation and demodulation method using the same. will be.

1 is a view showing the structure of a mobile communication channel to which the present invention and the prior art are applied. Hereinafter, the structure of a mobile communication channel will be described with reference to FIG. 1. In order to transmit the data to be transmitted from the transmitter without loss or distortion in the radio channel, a channel coding procedure is performed. As the channel coding technique, there are various techniques such as convolutional coding, turbo coding, and LDPC coding. Data that has undergone the channel coding procedure may be transmitted as a single symbol by collecting a plurality of bits when transmitted through a wireless channel. In this case, a procedure in which several bits are mapped to one symbol is called modulation.

The modulated data is converted into a signal for multiplex transmission through a multiplexing process or a multiple access method. As the multiplexing method, various methods such as CDM, TDM, and FDM exist. In FIG. 1, an example of orthogonal frequency division multiplexing (OFDM) is illustrated. The signal that has passed through the multiplexing block is changed into a structure suitable for transmission to one or more multiple antennas and transmitted to a receiver through a radio channel. Data transmitted in the course of passing through the wireless channel may experience fading and thermal noise, which may cause distortion of the data.

The modulated data is transmitted to a receiver through a wireless channel. In this process, the transmitted data may experience fading and thermal noise, which may cause distortion of the data. After receiving the distorted data, the receiving end performs a series of procedures in the reverse order. A demodulation operation of converting the data mapped to the symbol into a bit string is performed, and the distorted data is restored to the original data through a channel decoding process.

The apparatus for performing channel coding generates a parity check derived from an H matrix or an H matrix, which is a parity check matrix used to generate parity bits to be added to input data (Systematic Bits). It stores G matrix, which is a parity check generate matrix. That is, the transmitting end includes an encoder for generating parity bits through the H or G matrix and the input data. The apparatus for performing channel decoding checks whether the inputted data (Systematic Bits) are properly recovered through the H matrix and the operation of the received data (distorted Systematic Bits + Parity Bits). Rerun

The modulation includes Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), Quadrature Amplitude Modulation (16-QAM), 64-QAM, 256-QAM, and the like. For example, 16-QAM maps a data string that has undergone a channel encoding procedure during modulation to one symbol in 4-bit units. In demodulation, 16-QAM demaps one symbol of data received through a wireless channel into four bits.

The LDPC code will be described below. The concept of the LDPC code is as follows.

을 만족하도록 부호가 구성된다는 점이다. 이 선형 부호의 일종으로서, 최근에 주목받는 LDPC 부호는 1962년 Gallager에 의하여 처음 제안되었다. 이 부호의 특징으로는 패리티 체크 행렬의 원소가 대부분 0으로 이루어지고, 0이 아닌 원소의 수는 부호 길이에 비하여 적은 수를 가지도록 하여 확률을 기반으로 한 반복적 복호가 가능한 점이다. 처음 제안된 LDPC 부호는 패리티 체크 행렬을 비체계적인(non-systematic) 형태로 정의하였고, 그것의 행과 열에 균일하게 적은 무게(weight)를 갖도록 설계되었다. The linear code can be described by the generation matrix G or parity check matrix H. The characteristic of linear code is that for all codewords c,

The sign is constructed to satisfy. As a form of this linear code, a recent notable LDPC code was first proposed by Gallager in 1962. The characteristic of this code is that the elements of the parity check matrix are mostly 0, and the number of non-zero elements has a smaller number than the code length, so that it is possible to perform iterative decoding based on probability. The first proposed LDPC code defines the parity check matrix in a non-systematic form and is designed to have a uniformly low weight in its rows and columns.

Here, the weight means the number of 1s included in a column or a row in the matrix.

Since the density of nonzero elements on the parity check matrix H of the LDPC code is small, the decoding complexity is low. In addition, the decoding performance is also better than the existing codes, showing a good performance close to Shannon's theoretical limit. The LDPC code, however, was a hardware technology that was difficult to implement at the time and has not attracted much attention for more than 30 years. In the early 1980s, a method of iterative decoding using a graph was developed, and various algorithms were developed to actually decode the LDPC code using the graph. The sum-product algorithm can be extracted as the representative algorithm.

Hereinafter, the features of the LDPC code will be described. LDPC codes have high error correction performance, which allows for improvements in communication speed and capacity. The LDPC code may be applied to a high speed wireless LAN capable of transmitting hundreds of Mbit / s in combination with a multiple input multiple output (MIMO) system, and may be applied to high speed mobile communication having a transmission speed of 1 Mbit / s or more at 250 km / h. It can also be applied to optical communication of 40Gbits / s or more. In addition, the high error correction performance of the LDPC code may improve the transmission quality, thereby enabling quantum encrypted communication that reduces the number of retransmissions in a low quality communication path. In addition, due to the low complexity and excellent loss compensation of the LDPC code, lost packets can be easily recovered, which makes it possible to transmit content of the same quality as TV quality through the Internet and mobile communication. Due to the wide coverage and large capacity of LDPC, 10GBASE-T transmissions up to the 100m range, previously considered impossible, are possible with LDPC codes. At the same time, the transmission capacity of a single satellite transmitter in the 36MHz band can be increased by 1.3 times to 80Mbit / s. These advantages are being adopted as the next generation channel coding method in IEEE802.16 system and IEEE802.11 system for high frequency efficiency.

The structured LDPC is described below.

In order to use the LDPC code includes a matrix H to use, uses a parity check matrix H is most 0 and a part 1 of an element (elemnet), representing the H matrix, since the size of the H matrix size by more than 10 ⁵ bits It requires a large amount of memory. The structured LDPC technique is a method of representing elements of the H matrix used for LDPC encoding and decoding as sub-blocks having a constant size as shown in FIG. 2. In IEEE802.16e, the subblock is represented by one integer index to reduce the size of memory required to store the H matrix. The subblock may be various matrices, for example, a permutation matrix of a constant size.

In the structured LDPC technique, instead of storing a matrix of 1 or 0 in a specific memory, only one integer (that is, an index) needs to be stored. Can be reduced.

For example, when the size of the codeword reflected in the IEEE802.16e standard is 2304 and the code rate is 2/3, the model matrix used for LDPC encoding / decoding is shown in FIG. Same as 3.

As shown in FIG. 3, the structured LDPC matrix of IEEE 802.16e consists of -1, 0 and positive integer elements. -1 is a zero matrix of all elements 0 and 0 represents an identity matrix. Positive integer elements other than -1 and 0 are permutation matrices in which the identity matrix is shifted to the right by a positive integer. That is, when the constituent elements of the matrix are three, the permutation matrix is expressed by shifting the unit matrix three times to the right.

4 is a diagram illustrating a method of expressing a matrix according to the aforementioned positive integer, that is, a shift number. When a specific H matrix is structured and expressed as a matrix having a size of 4 * 4 (that is, a sub block), if the specific sub block is denoted as 3, the sub block becomes the matrix of FIG.

Hereinafter, the LDPC encoding method will be described.

In the general LDPC encoding method, a generation matrix G is derived from an LDPC parity check matrix H to encode an information bit. In order to derive the generation matrix G, the inspection matrix H is configured in the form of [P ^T : I] through a Gaussian Reduction method. When the number of information bits is k and the size of an encoded codeword is n, the P matrix is a matrix in which the number of rows is k and the number of columns is nk, and I is K is the identity matrix whose k column size is k.

The generation matrix G becomes a [I: P] matrix when the check matrix H is expressed as [P ^T : I]. If the encoded information bits of k-bit size are represented in a matrix, the number of rows is 1 and the number of columns is k. In this case, the code word c is described as follows.

In the above equation, x denotes a systematic part and xP denotes a parity part.

)을 이용하여, 상기 수학식 1에서 H^T을 곱하면, 하기 수학식 2 같은 수학식을 얻을 수 있다. 하기 수학식 2에 부합하는 패리티 비트를 정보 비트(x) 뒤에 추가하여 코드워드 c를 얻을 수 있다. On the other hand, in the case of encoding by the Gaussian Reduction method as described above, a large amount of calculation is performed, and a method of directly encoding the H matrix without inducing the G matrix by designing the shape of the H matrix into a special structure. Use That is, H ^{T in the} form of a transpose of the G matrix and the H matrix. The product of 0 (that is,

By multiplying H ^T by Equation 1, Equation 2 can be obtained. A codeword c may be obtained by adding a parity bit corresponding to Equation 2 after the information bit x.

Hereinafter, the LDPC decoding method will be described.

The encoded data in the communication system includes noise in the process of passing through the wireless channel of FIG. In the decoding block of the receiving end, the information bit x is obtained from the received signal c 'having noise added to the coded code c, and is found using the property of cH ^T = 0. That is, when the received codeword is c ', the value of c'H ^T is calculated, and if the result is 0, the first k bits in c' are determined as the information bits x. If the value of c'H ^T is not 0, a decoding technique such as a sum-product algorithm through a graph is used to find c 'whose value of c'H ^T satisfies 0. recover (x)

Hereinafter, the code rate of the LDPC code will be described.

In general, a code rate (R) is as follows when the size of the information bit is k and the size of the codeword actually transmitted is n.

R = k / n

The code rate is as follows when the row size of the H matrix required for LDPC encoding and decoding is m and the size of the column is n.

R = 1-m / n

As described above, in the conventional LDPC code, since the encoding and decoding are performed by the H matrix, the structure of the H matrix is very important. That is, since the performance of LDPC encoding and decoding is greatly influenced by the structure of the H matrix, the design of the H matrix is most important.

Table 1 below shows the characteristics of the weight of the model matrix used in IEEE 802.16e.

Code rate The number of subblocks with weight on the model matrix 1/2 76 2 / 3A 80 2 / 3B 81 3 / 4A 85 3 / 4B 88 5/6 80

In IEEE 802.16e, channel coding having six types of code rates is performed. The encoding / decoding apparatus should basically include a memory for storing model matrices according to the six types of code rates. That is, since 490 memory spaces should be basically provided, an additional cost is incurred in the transceiver.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and an object of the present invention is to propose an encoding / decoding method for performing encoding and decoding using a small memory.

Another object of the present invention is to propose a parity check matrix capable of supporting various code rates.

According to an aspect of the present invention, there is provided a method of performing low density parity check (LDPC) encoding, comprising: determining a specific region of a parity check matrix used to encode an input bit; And encoding the input bit by the determined region, wherein the parity check matrix has a different density of weights of rows or columns included in the information word portion according to a predetermined number of the specific regions. It is done.

In addition, the present invention provides a method of performing low density parity check (LDPC) encoding, comprising: performing an encoding on an input bit using a specific first region of a parity check matrix; Determining whether to change a code rate of the encoded data; And encoding the input bit using a specific second region of the parity check matrix according to the determination result.

In addition, the encoding apparatus according to the present invention is a device for performing Low Density Parity Check (LDPC) encoding, comprising: a memory including a parity check matrix used for encoding input bits; And a coding module for determining a specific area of the parity check matrix and encoding the input bit by the determined area, wherein the parity check matrix is included in an information word portion according to a predetermined number of the specific areas. It is characterized in that the density of the weight of the row or column included is different.

The present invention is characterized by performing encoding and decoding using a specific region of one mother matrix in order to solve the above-described problems of the prior art. The specific region is determined according to a code rate of channel coding implemented by the specific region. When encoding and decoding are performed using the single matrix, all or part of the matrix is used.

In addition, the present invention proposes to change the structure of the conventional parity check matrix to support various code rates through one mother matrix. More specifically, the weight of a row or column of the informational part of the parity check matrix according to the present invention is determined according to a specific region. The specific area is more preferably determined according to the code rate of the channel code according to the parity check matrix. In addition, the density of the weight for the row or column belonging to the data area corresponding to the high code rate is preferably higher than the density of the weight for the row or column belonging to the data area corresponding to the low code rate. By using the parity check matrix, it is possible to perform encoding by varying the code rate according to a specific need.

The construction, operation and effects of the present invention will be embodied by one embodiment of the present invention described below. Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

Hereinafter, a matrix representing a parity check matrix as a subblock having a specific z * z size according to the structured LDPC described above is referred to as a model matrix. Each sub block of the model matrix may be extended to various kinds of matrices by a specific index, and the model matrix has the index as a component of the model matrix. Each sub block of the model matrix may be determined in various ways according to the index. Hereinafter, it is assumed that the index is a shift number for a unit matrix of a specific size z * z. In addition, when the index is -1, the sub block having the index of -1 is a zero matrix of a specific size z * z.

The model matrix is extended to a specific parity check matrix according to the index, so that encoding and decoding are performed by the model matrix, and that encoding and decoding is performed by a specific parity check matrix generated by the model matrix. it means.

According to the above-described prior art, in order to implement an encoding / decoding apparatus supporting a plurality of code rates, a model matrix corresponding to the number of supported code rates is required. However, in the present embodiment, encoding and decoding are performed using one mother matrix.

The parent matrix may be a model matrix or a parity check matrix. In addition, the parity check matrix may be generated by extending from a specific model matrix. Hereinafter, a method of encoding using a specific model matrix as a parent matrix will be described. As described above, the parent matrix may be a parity check matrix.

6 is a diagram illustrating a concept of supporting various code rates through one mother matrix. Hereinafter, the mother matrix according to the present embodiment will be described with reference to FIG. 6. When the model matrix of FIG. 6 is referred to as H _b , the H _b is composed of an information word, that is, an information word part H _b1 corresponding to the information bit one-to-one and a parity part H _b2 . The model matrix is summarized as follows.

M _b represents the number of sub blocks located in the column direction in the model matrix of FIG. 6. K _b is a value obtained by subtracting m _b from the number n _b of subblocks located in the row direction of the model matrix. That is, the information word portion of the model matrix has a size of m _b * k _b when expressed in units of sub-blocks. In addition, the parity portion of the model matrix has a size of m _b * m _b when expressed in units of sub-blocks. The code rate is determined by the size of the model matrix, and the code rate R is determined by R = k _b / (k _b + m _b ).

In the example of FIG. 6, the code rate of the mother matrix 604 is 1/3, and the partial matrices of the mother matrix 604 are located in regions 601, 602, and 603. The partial matrix means a partial region of the parent matrix and is configured as shown in the example of FIG. 6. That is, the length of the information bits encoded by the partial matrices 601, 602, 603 and the information bits encoded by the parent matrix 604 are the same. The partial matrices are different in size, and have a unique code rate according to the size. For example, the first partial matrix 601 has a code rate of 3/4, the second partial matrix 602 has a code rate of 2/3, and the third partial matrix 603 has a code rate of 1/2. Has a code rate. Further, the partial matrix for generating codewords with lower code rate includes the partial matrix for generating codewords with higher code rate. The parent matrix according to the present embodiment is characterized by including at least one partial matrix.

In the present embodiment, encoding / decoding is performed using the above-described mother matrix, but encoding / decoding by all or part of the region of the mother matrix is performed. That is, encoding / decoding that supports a plurality of code rates is performed by a mother matrix or at least one partial matrix. For example, the encoding apparatus included in the transmitter may store the mother matrix in a memory and perform encoding by reading all or some regions of the mother matrix according to a desired code rate. In addition, the decoding apparatus included in the receiver may store the mother matrix in a memory and read and decode all or some regions of the mother matrix according to a code rate used by the transmitter. That is, in the related art, different model matrices are stored and used according to respective code rates. However, when encoding and decoding are performed using the parent matrices proposed in this embodiment, all or part of one parent matrix is deleted. To perform the encoding. Through this operation, various kinds of code rates can be supported while using a small amount of memory.

When encoding and decoding are performed by the mother matrix according to the present embodiment, it is more preferable to change the structure of the information word portion of the mother matrix. Hereinafter, the design of the information word portion of the parent matrix will be described.

7A is a diagram illustrating a mother matrix according to an embodiment of the present invention through a model matrix. Three sub-matrices are included in the mother matrix, and four different code rates are supported by the mother matrix. The partial matrix is determined according to a code rate, the first sub-matrix 710 supports a code rate of 20/27, the second sub-matrix 720 supports a code rate of 2/3, and a third The submatrix 730 supports a code rate of 1/2, and the mother matrix 740 supports a code rate of 1/3.

It is preferable that the density of the weight with respect to the row or column of the information word part of each partial matrix is determined according to each said partial matrix. The weight represents the number of non-zero components of a particular row or column. In addition, the weight density represents the ratio of the non-zero component to the total component in a particular row or column. More specifically, it is preferable that the density of the weight of the row or column for the information word portion of the first partial matrix 710 is greatest, and the weight of the row or column for the information word portion of the second partial matrix 720 is greater. Preferably, the density is the second largest, and the density of the weight of the row or column with respect to the information word portion of the third partial matrix 730 is preferably the third largest, and the information word portion of the parent matrix 740 is provided. It is desirable that the density of the weight of the rows or columns for the smallest.

In other words, the density of the weight of the row or column with respect to the information word portion of the parent matrix 740 is preferably determined differently according to the information word portion determined according to the code rate. Further, it is more preferable that the density of the weight of the row or column for the information word portion supporting the high code rate is larger than the density of the weight of the row or column for the information word portion supporting the low code rate.

The weight density of the information word portion of the parent matrix or the partial matrix proposed in this embodiment may be divided as shown in FIG. 7B. That is, the first partial matrix 711 corresponding to the highest code string, the second partial matrix 721 corresponding to the second highest code rate, the third partial matrix 731 corresponding to the third highest code rate, It may be divided into a fourth partial matrix 741 corresponding to the lowest code rate. According to the present exemplary embodiment, the weight densities according to the respective partial matrices 711, 721, 731, and 741 are preferably different. That is, the density of the weight of any one of the four partial matrices may be the largest, and the density of the weight of the remaining three partial matrices may be small. In addition, the weight density of any two of the four partial matrices may be large, and the weight density of the remaining two partial matrices may be small. Preferably, the density of the weight may be determined according to the order of the partial matrix corresponding to the high code string. That is, the weight density of the first partial matrix 711 is highest, the weight density of the second partial matrix 721 is second highest, and the weight density of the third partial matrix 731 is third highest. The weight density of the fourth partial matrix 741 may be the lowest.

Table 2 below is a table for explaining the density of the weight according to the example of FIGS. 7A and 7B. Table 2 below shows average row weights for the information word portion of the parent matrix or the partial matrix. The average row weight represents an average value of the sum of the weights included in the rows. In other words, the average row weight is a data value corresponding to the density of the weight of the row or column.

Code rate Average row weight ( average  row weight ) Average row weight (%) Remarks 20/27 11.43 100% High code rate 2/3 9.90 86.6% High code rate 1/2 7.75 67.8% Low code rate 1/3 6.20 54.2% Low code rate

If the code rate is 20/27, each row contains, on average, a nonzero weight of 11.43. In addition, when the code rate is 2/3, each row includes a nonzero component of 9.90 on average, and has a weight of 86.6% compared to the case where the code rate is 20/27. In addition, when the code rate is 1/2, each row includes a non-zero component of 7.75 on average, which has a weight of 67.8% compared to the case where the code rate is 20/27. In addition, when the code rate is 1/3, each row includes non-zero components of 6.20 on average, and has a weight of 54.2% compared to the case where the code rate is 20/27.

As can be seen from Table 2, the weight density of the partial matrix supporting the high code rate is relatively high. That is, the weight is dense in the partial matrix supporting the high code rate. On the other hand, the weight density for the partial matrix supporting low code rate is relatively low. That is, weights are sparse in partial matrices that support low code rates.

When encoding is performed using the model matrices of FIGS. 7A and 7B, various code rates may be supported using one mother matrix. The mother matrix according to the present embodiment may be applied to various systems. A simple example of how to support the various code rates required by one mother matrix in a system that requires rate compatibility is:

First, since a high code rate communication is possible when the channel environment is good, when a code rate of 20/27 is applied, encoding is performed using the first partial matrix 710. In addition, the receiver stores the same mother matrix as the transmitter and decodes the codewords H _d and p ₁ using the stored first partial matrix 710.

If a change in the channel environment occurs and a code rate lower than that of the previous code rate is applied, for example, a code rate of 2/3, encoding is performed using the second partial matrix 720. The receiver stores the same mother matrix as the transmitter and decodes the codewords H _d , p ₁ , p ₂ using the stored second partial matrix 720.

If a change in the channel environment occurs and a code rate lower than that of the previous code rate is applied, for example, a code rate of 1/2 is applied, encoding is performed using the third partial matrix 730. The receiver stores the same parent matrix as the transmitter and decodes codewords H _d , p ₁ , p ₂ , and p ₃ using the stored third sub-matrix 730.

If a change in the channel environment occurs and a code rate lower than that of the previous code rate is applied, for example, a code rate of 1/3 is used, encoding is performed using all of the mother matrices 740. The receiver stores the same parent matrix as the transmitter and performs decoding on the codewords H _d , p ₁ , p ₂ , p ₃ and p ₄ using the stored parent matrix 740.

The specific code rate and the size and weight of the matrix are just examples for describing the present invention, and the present invention is not limited to the above-described specific numerical values. That is, the conditions such as the code rate can be freely changed.

It will be apparent to those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the above detailed description should not be construed as limiting in all aspects and should be considered as illustrative. The scope of the invention should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent scope of the invention are included in the scope of the invention.

Hereinafter, the effect of the present invention will be described.

The present invention has the advantageous effect of improving memory efficiency and simplifying the scheduler, compared with the prior art which uses separate parity check matrices according to the code rate. The present invention shows the same or improved performance as the prior art in terms of performance.

For example, 321 memories were required for the conventional IEEE 802.16e LDPC code to support code rates 1/2 to 3/4. However, if one mother matrix is used and the information word portion is designed according to the present invention, only 155 memories have the corresponding effect to the prior art.

8 shows a performance curve that supports various code rates using a single matrix. As shown, compared to various conventional encoding methods, the encoding method according to the present invention shows comparable or superior performance. Considering that the encoding method according to the present invention uses less memory, it can be said that the present invention shows better performance than the conventional low density parity check code of IEEE 802.16e.

Claims (15)

In the method of performing Low Density Parity Check (LDPC) encoding, Determining a particular region of the parity check matrix used to encode the input bits; And Encoding the input bit by the determined region , ≪ / RTI > The parity check matrix is a coding method using a parity check matrix, characterized in that the density of the weight of the row or column included in the information word portion is different according to a predetermined number of the specific areas. The method of claim 1, Specific region of the parity check matrix, An information word portion corresponding to an input bit of a preset length, Including a parity portion corresponding to a variable length parity bit. An encoding method using a parity check matrix. The method of claim 1, Specific region of the parity check matrix, Is determined according to a code rate by the parity check matrix. An encoding method using a parity check matrix. The method of claim 1, And a size of a density of a weight of a row or a column for each specific region of the parity check matrix corresponds to a size of a code rate of each specific region. The method of claim 1, The parity check matrix is A method of encoding using a parity check matrix, characterized in that it is extended from a model matrix consisting of sub blocks of a specific size. The method of claim 1, The parity check matrix is Is created by expanding from a model matrix of sub-blocks An encoding method using a parity check matrix. The method of claim 1, The density of the weight of the row or column, And a ratio between a weighted component and all of the components included in the rows or columns included in the specific region. In the method of performing Low Density Parity Check (LDPC) encoding, Encoding the input bits using a specific first region of the parity check matrix; Determining whether to change a code rate of the encoded data; And Encoding the input bits using a specific second region of the parity check matrix according to the determination result Encoding method using a parity check matrix comprising a. 9. The method of claim 8, The parity check matrix is a coding method using a parity check matrix, characterized in that the density of the weight of the row or column included in the information word portion is different according to a predetermined number of areas. 10. The method of claim 9, If the code rate of the parity check matrix of the first region is higher than the code rate of the parity check matrix of the second region, The density of the weight of the row or column for the first region is greater than the density of the weight of the row or column for the second region An encoding method using a parity check matrix. 10. The method of claim 9, When the code rate of the parity check matrix of the first region is lower than the code rate of the parity check matrix of the second region, The density of the weight of the row or column for the first region is smaller than the density of the weight of the row or column for the second region. An encoding method using a parity check matrix. 10. The method of claim 9, The density of the weight of the row or column, And a ratio between components having weight among all components included in the row or column included in the specific region and the whole components. 9. The method of claim 8, The first area and the second area, An information word portion corresponding to an input bit of a preset length, And a parity part corresponding to a parity bit of a variable length. 9. The method of claim 8, The parity check matrix is A method of encoding using a parity check matrix, characterized in that it is extended from a model matrix consisting of sub blocks of a specific size. In the apparatus for performing Low Density Parity Check (LDPC) encoding, A memory including a parity check matrix used to encode input bits; And An encoding module that determines a specific region of the parity check matrix and encodes the input bit by the determined region , ≪ / RTI > And wherein the parity check matrix has a different density of weights of rows or columns included in an information word portion according to a predetermined number of the specific regions.

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