KR20070096983A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided to utilize channel regions formed in each pair of fins corresponding to one gate as a conductive path for electric charges. At least a pair of fins(21a,21b) protrude from a substrate, and are spaced apart from each other. Insulating layers(22,23) are formed between the fins, and a storage node(26) is formed on the fins and a surface of a portion of the insulating layer. A gate electrode(27) is formed on the storage node. A source and a drain are formed on the fins, and a pair of channel regions are formed on inner surfaces of the fins between the source and drain. Widths of the fins contacting the storage node are smaller than those of the fins in a region where the source and the drain are formed.

Description

Semiconductor Memory Device

1 is a perspective view illustrating a semiconductor memory device according to an embodiment of the present invention.

FIG. 2A illustrates a vertical cross section taken along the line II ′ of FIG. 1.

FIG. 2B is a cross-sectional view illustrating a cross section taken along the line JJ ′ of FIG. 1.

3A to 3G are views illustrating a manufacturing process of a semiconductor memory device according to an embodiment of the present invention.

FIG. 4A is a cross-sectional view taken along the line II ′ of FIG. 3A.

4B is a view showing a manufacturing process of the structure of FIG. 4A.

5A is a cross-sectional view taken along the line AA ′ of FIG. 3C.

FIG. 5B is a cross-sectional view taken along the line BB ′ of FIG. 3C.

5C is a cross-sectional view taken along the line CC ′ of FIG. 3C.

6A is a cross-sectional view taken along the line AA ′ of FIG. 3D.

FIG. 6B is a cross-sectional view taken along the line BB ′ of FIG. 3D.

FIG. 6C is a cross-sectional view taken along the line CC ′ of FIG. 3D.

FIG. 7A is a cross-sectional view taken along the line AA ′ of FIG. 3E.

FIG. 7B is a cross-sectional view taken along the line BB ′ of FIG. 3E.

8A is a cross-sectional view taken along the line AA ′ of FIG. 3F.

FIG. 8B is a cross-sectional view taken along the line BB ′ of FIG. 3E.

9A is a cross-sectional view taken along the line AA ′ of FIG. 3G.

FIG. 9B is a cross-sectional view taken along the line BB ′ of FIG. 3F.

<Description of Symbols for Main Parts of Drawings>

10, 20 ... semiconductor substrates 11a, 11b, 21a, 21b ... pins

12, 22 ... first insulating layer 13, 23 ... second insulating layer

16, 26 ... storage nodes 17, 27 ... gate electrodes

24 ... PR layer 25 ... oxide layer

CH1, CH2 ... Channel Area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to semiconductor devices having pin-type channel regions and random access memory (RAM). For example, the semiconductor device may include a fin-FET, and the random access memory may include DRAM, RRAM, FeRAM, or NOR-type flash memory.

Fin-FET structures that can improve the performance of semiconductor devices have been studied. For example, US Pat. No. 6,664,582 to "FIN MEMORY CELL AND METHOD OF FABRICATION" by David M. Fried et al. Discloses a fin-pet and a pin memory cell. As another example, US Pat. No. 6,876,042, "ADDITIONAL GATE CONTROL FOR A DOUBLE-GATE MOSFET" by Bin Yu et al., Discloses a pin-pet comprising a fin formed on an insulating layer.

The fin-pet may use the upper and side surfaces of the fins formed in the shape of fish fins as channel regions. As a result, the pin-pet may have a larger channel area than the planar transistor, thereby providing a large current flow. As a result, the pin-pet can provide higher performance than planar transistors.

However, the pin-pet by David M. Fried et al. And Bin Yu et al. Is manufactured using an SOI substrate, so that the pin is floated from the substrate body. Accordingly, it is impossible to control the threshold voltage of the transistor using body-bias, and as a result, it is difficult to adjust the threshold voltage of the CMOS transistor. On the other hand, using a conventional bulk substrate can extend the drain depletion region to increase junction leakage current, off current, and junction capacitance. Furthermore, in the highly integrated device, the threshold voltage may be decreased and the off current may be further increased by the short channel effect.

Another problem with pin-pets is high contact resistance. For example, the pin-pet by David M. Fried includes bit line contacts formed across the pins. In this case, the bit line contact and the narrow upper surface of the pin come into contact with each other, so that the bit line contact resistance may be very high. In addition, since the pins may be bent to form a bit line contact, there is a manufacturing difficulty.

According to Bin Yu et al., The source and drain regions are formed wide to connect with the fins and to secure the contact area. However, the source and drain regions may increase the distance between the fins, resulting in a low pin-pet integration.

Therefore, the technical problem to be achieved by the present invention is to overcome the above-mentioned problems, it is possible to adopt the advantages of the SOI structure while being able to control the body-bias, and provide a high performance by providing a high operating current and low contact resistance It is providing the semiconductor element which has.

In the present invention, to achieve the above object,

Semiconductor substrates;

At least a pair of fins each protruding from the semiconductor substrate and spaced apart from each other;

An insulating layer formed between the pair of fins;

A storage node formed on the pair of fins and a portion of the surface of the insulating layer; And

And a gate electrode formed on the storage node.

According to an embodiment of the present invention, a source and a drain formed on the pair of pins are spaced apart from each other about an area where the pair of pins and the storage node contact each other; And

And a pair of channel regions each formed near at least an inner surface of the pair of fin portions between the source and the drain.

In the present invention, the width of the pair of fins of the region contacted by the storage node is smaller than the width of the pair of fins of the region where the source and drain are formed.

In the present invention, an oxide layer formed between the semiconductor substrate and the storage node; characterized in that it further comprises.

In the present invention, the storage node is formed by including polysilicon, silicon-germanium, metal dots, silicon dots or silicon nitride.

In the present invention, the storage node is formed by including a dielectric material, a resistance conversion material, a phase change material or a ferroelectric material.

In the present invention, the semiconductor substrate is characterized in that it comprises bulk silicon, bulk silicon-germanium or a silicon or silicon-germanium epi layer thereon.

Hereinafter, a semiconductor memory device having a buried channel structure according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Here, the present invention is not limited to the embodiments disclosed below, and may be implemented in various forms. This embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art the scope of the present invention. In the drawings, the components are to be noted that the size is somewhat exaggerated for convenience of description.

1 is a perspective view illustrating a semiconductor memory device according to an embodiment of the present invention. FIG. 2A is a vertical cross-sectional view taken along the line II ′ of the semiconductor memory device illustrated in FIG. 1, and FIG. 2B is a cross-sectional plan view taken along the line J-J ′ of the semiconductor memory device illustrated in FIG. 1.

1, 2A and 2B, in the semiconductor memory device according to the embodiment of the present invention, a pair of fins 11a and 11b are formed on the semiconductor substrate 10, and a pair of fins ( The first insulating layer 12 is formed on the substrate between 11a and 11b. The storage node 16 and the gate electrode 17 are formed between the pair of fins 11a and 11b on the first insulating layer 12. The width of the pair of fins 11a and 11b of the portion where the storage node 16 is formed is the width of the pair of fins 11a and 11b of the region where the storage node 16 is not formed, that is, the region where the source and drain are formed. It can be seen that significantly reduced compared to the width. This greatly limits the depletion region.

Channel regions CH1 and CH2 are formed in regions where the storage node 16 contacts the pair of pins 11a and 11b. A source S and a drain D are formed in the pair of fins 11a and 11b on both sides of the channel region CH1 and CH2. Accordingly, the memory device according to the embodiment of the present invention has a fin-FET structure because the channel regions CH1 and CH2 are formed in the pair of fins 11a and 11b. Here, the storage node 16 may be selectively formed according to the type of memory. For example, in the case of DRAM, a dielectric material may be applied to form a capacitor structure, in the case of RRAM, a transition metal oxide may be applied, in the case of PRAM, a phase change material may be applied, and in the case of FeRAM, ferroelectric materials may be applied. It can be applied. In the case of the SONOS structure, a multilayer structure of an oxide, a nitride, and an oxide may be formed. The storage node may be formed including polysilicon, silicon-germanium, metal dots, silicon dots, or silicon nitride. In addition, the storage node may be formed of a dielectric material, a resistance conversion material, a phase change material, or a ferroelectric material.

The semiconductor substrate 10 may be formed of a material typically used in a semiconductor memory device, and may be, for example, a bulk structure including bulk silicon, bulk silicon germanium, or a composite structure including a silicon or silicon germanium epi layer thereon. . The pair of fins 11a and 11b formed on the semiconductor substrate 10 may be the same material as the semiconductor substrate 10 or an epitaxial layer formed on the semiconductor substrate 10. A second insulating layer 13 is formed between the first fins 11a and the second fins 11b. The first insulating layer 12 and the second insulating layer 13 may be formed of a silicon oxide film, a silicon nitride film, a high-k dielectric film, or a composite film thereof. For convenience in the manufacturing process to be described later, the second insulating layer 13 is preferably formed of a material different from the first insulating layer. For example, the first insulating layer 12 may be formed of silicon oxide, and the second insulating layer 12 may be formed of silicon nitride.

The channel regions CH1 and CH2 may be formed in the surface of the portion where the pair of fins 11a and 11b contact the storage node 16, and the movement path of the charge between the source S and the drain D may exist. Plays a role. Referring to the drawings, it can be seen that two channel regions CH1 and CH2 are provided as a movement path of charge for one gate electrode 17. Therefore, since the two channel regions CH1 and CH2 can be used at the same time, the operating current of the semiconductor memory device can be increased, and as a result, the operating speed can be increased. Therefore, it can be used in a memory that requires a high operating current, for example, a phase change memory (PRAM) or a resistance conversion memory (RRAM) element. In addition, when used in DRAM, there is an advantage that can increase the sensing margin by increasing the operating current.

At least a pair of sources S and drains D may be formed in portions of the fins 11a and 11b at both sides of the channel regions CH1 and CH2, and the source S and the drain D may be named. They are not distinguished by their function, but are distinguished by their function and may be interchanged. The source S and the drain D are diode-bonded to portions of the fins 11a and 11b except for the semiconductor substrate 10 or the source S and drain D regions. For example, when the source S and the drain D are doped with n-type impurities, portions of the fins 11a and 11b except for the source S and drain D regions or the semiconductor substrate 10 may be p-type. It may be doped with impurities and vice versa.

The gate electrode 17 is formed on the storage node 16 and is formed of a conductive material. For example, it may be formed of polysilicon, metal, metal silicide or a composite material thereof. As shown in the figure, the gate electrode 17 may correspond to the pair of channel regions CH1 and CH2 in common, and when formed in an array structure, the gate electrode 17 may be formed in other unit devices through the upper portion of the second insulating layer 13. Can be electrically connected.

Hereinafter, an operation characteristic of a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 1, 2A, and 2B.

1, 2A, and 2B, when a turn-on voltage is first applied to the gate electrode 17, the channel regions CH1 and CH2 are simultaneously turned on to form a conductive path. Can be. Accordingly, an operating voltage is applied between the source S and the drain D formed in the fins 11a and 11b, and a current flows from the drain D to the source S through the channel regions CH1 and CH2. Can be. That is, the semiconductor device may provide one pin-pet operation.

In operation of the semiconductor device, as the widths of the fins 11a and 11b become thinner, the depletion region may be limited. Thus, although the fins 11a and 11b are connected to the semiconductor substrate 10, the semiconductor substrate 10 is similar to the SOI structure, that is, the SOI-like structure. Accordingly, off-current, junction leakage current, and junction capacitance, which may occur due to the expansion of the depletion region, can be reduced. Reducing the junction leakage current can improve the sensing margin of semiconductor devices, such as memory devices, and reduce power consumption. In addition, as the degree of integration of semiconductor devices increases, short channel effects, which may be a problem, may also be suppressed. However, the advantage of applying a body-bias to the fins 11a and 11b by applying a voltage to the semiconductor substrate 10 is maintained. Accordingly, the threshold voltage of the semiconductor device, for example, the CMOS pin-pet, can be easily adjusted. For example, the threshold voltages of the two pin-pets can be similarly adjusted by adjusting the body-bias of the NMOS pin-pet and the PMOS pin-pet.

Hereinafter, a manufacturing process of a semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. 3A to 3G are plan views illustrating a process of manufacturing a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3A, a plurality of first insulating layers 22 and second insulating layers 23 formed in the first direction are provided. A cross section cut in the direction of ll ′ of FIG. 3a is shown in FIG. 4a. Referring to FIG. 4A, a semiconductor substrate 21 including a pair of fins 21a and 21b protruding upward is provided. The first insulating layer 22 and the second insulating layer 23 are formed between the first fins 21a and the second fins 21b of the semiconductor substrate 21, respectively.

FIG. 4B shows the process of forming the structure shown in FIG. 4A. Referring to FIG. 4B, the method of forming the fins 21a and 21b may use a general method known to those skilled in the art. Specifically, for example, the fins 21a and 21b may be easily formed by forming the trenches 30a and 30b using photolithography and etching techniques in regions except for positions where the fins are to be formed on the Si substrate. Then, the first insulating layer 22 filling the first trench 30a and the second trench 30b is formed. The first insulating layer 22 may be formed by, for example, applying silicon oxide to fill and planarize the trenches 30a and 30b. The insulating material embedded in the second trench 30b is etched and removed. The planarization process is performed after forming the second insulating layer 23 filling the second trench 30b. The second insulating layer 23 may be formed by, for example, applying silicon nitride. Here, before filling the second trench 30b, impurities may be injected into the exposed upper and inner surfaces of the exposed fins 21a and 21b to form a source and a drain.

Referring to FIG. 3B, a photoresist (PR) layer 24 patterned in a second direction intersecting the first insulating layer 22 and the second insulating layer 23 is formed. Referring to FIG. 3C, holes (not shown) are formed by etching the exposed first insulating layer 22. Then, the PR layer 24 is removed.

5A is a cross-sectional view taken along the line AA ′ of FIG. 3C. The portion A-A ′ of FIG. 3C forms the PR layer 24, and it can be seen that the first insulating layer 22 is not etched and remains. FIG. 5B is a cross-sectional view taken along the line BB ′ of FIG. 3C. Referring to FIG. 5B, it can be seen that the hole h1 is formed in the region between the fins 21a and 21b by etching and removing the first insulating layer 22 between the PR layers 24 of FIG. 3B. . 5C is a cross-sectional view taken along the line CC ′ of FIG. 3C. Referring to FIG. 5C, it can be seen that a hole h1 is formed in a region between the first insulating layers 22 which remain unetched.

An oxidation process is performed inside the hole h1 shown in FIG. 5B. For example, a thermal oxidation process can be performed. By the oxidation process, for example, silicon oxide is formed on the fins 21a and 21b on the side of the hole h1 and the width of the fins 21a and 21b is reduced. Therefore, referring to FIG. 3D, it can be seen that the widths of the fins 21a and 21b and the second insulating layer 23 of the portion where the hole h is formed are narrowed. The narrow width of the second insulating layer 23 is a region in which the oxides 25 are formed by oxidizing the fins 21a and 21b on the side of the hole h1 shown in FIG. 5B.

6A is a cross-sectional view taken along the line AA ′ of FIG. 3D, and it can be seen that the first insulating layer 22 remains as it is. FIG. 6B is a cross-sectional view taken along the line BB ′ of FIG. 3D, and side surfaces of the pins 21a and 21b are etched to decrease the width. In addition, the oxide 25 is formed on the side surfaces of the fins 21a and 21b and the semiconductor substrate 21. FIG. 6C is a cross-sectional view taken along the line CC ′ of FIG. 3D. Referring to FIG. 6C, the first insulating layer 22 is formed in a patterned structure on the semiconductor substrate 21, and on the substrate between the side surface of the first insulating layer 22 and the first insulating layer 22. It can be seen that the insulating layer 25 is formed. Here, the oxide 25 may be made of the same material as the first insulating layer 22, and may be, for example, silicon oxide. Hereinafter, the oxide 25 and the first insulating layer 22 will be described using the same member numbers.

Referring to FIG. 3E, an oxide is filled up in the hole h1 of FIG. 3D, and then planarized by, for example, a CMP process. FIG. 7A is a cross-sectional view taken along the line AA ′ of FIG. 3E, and it can be seen that the first insulating layer 22 remains as it is. FIG. 7B is a cross-sectional view taken along the line BB ′ of FIG. 3E, and it can be seen that the first insulating layer 22 is buried on the semiconductor substrate 21 between the fins 21a and 21b having the reduced width.

Referring to FIG. 3F, the first insulating layer 22 is selectively etched by a predetermined depth. In this case, the remaining first insulating layer 22 ′ may serve as a device isolation layer. 8A is a cross-sectional view taken along the line AA ′ of FIG. 3F, and it can be seen that the first insulating layer 22 is etched by a predetermined depth. FIG. 8B is a cross-sectional view taken along the line BB ′ of FIG. 3E and shows that the first insulating layer 22 is etched by a predetermined depth on the semiconductor substrate 21 between the fins 21a and 21b having the reduced width. .

Referring to FIG. 3G, a storage node 26 (not shown) is formed between regions of the side surfaces of the pins 21a and 21b which are etched, and then a conductive material is applied to form the gate electrode 27. FIG. 9A is a cross-sectional view taken along the line AA ′ of FIG. 3G, and it is understood that the first insulating layer 22 is etched to a predetermined depth because no separate process is performed in this region. FIG. 9B is a cross-sectional view taken along the line BB ′ of FIG. 3F, wherein a first insulating layer 22 is formed on the semiconductor substrate 21 between the fins 21a and 21b having reduced width, and a storage node thereon. It can be seen that 26 and the gate electrode 27 are formed.

The storage node 26 may be selectively formed according to the type of memory. For example, in the case of DRAM, a dielectric material may be applied to form a capacitor structure, in the case of RRAM, a transition metal oxide may be applied, in the case of PRAM, a phase change material may be applied, and in the case of FeRAM, ferroelectric materials may be applied. It can be applied. In the case of the SONOS structure, a multilayer structure of an oxide, a nitride, and an oxide may be formed.

The foregoing description of specific embodiments of the invention has been presented for purposes of illustration and description. For example, in the present invention, the semiconductor device may include a pin-pet and a memory device using the same. In addition, in the present invention, the random access memory may include a NOR-type array structure in which the presented unit cells are arranged in a matrix. The present invention is not limited to the above embodiments, and it is apparent that many modifications and changes can be made in the technical spirit of the present invention by those having ordinary skill in the art in combination. .

According to the present invention, the semiconductor devices may simultaneously use channel regions respectively formed in the pair of fins corresponding to one gate electrode as the conductive path for charge. Therefore, it is possible to implement two channels at the same time in one device, it is possible to implement two memory nodes. In addition, the operating current of the semiconductor element can be increased, and as a result, the operating speed can be increased. Accordingly, semiconductor devices can be used in memories that require high operating currents, such as PRAM or RRAM. In addition, when used in a DRAM, the semiconductor device may have an increased sensing margin by increasing an operating current.

In addition, according to the semiconductor device of the present invention, the semiconductor substrate may have a similar SOI structure, that is, an SOI-like structure, even though the fins of the semiconductor substrate are connected to the body. Accordingly, off-current, junction leakage current and junction capacitance, which may occur due to the expansion of the depletion region, can be reduced. In addition, a body-bias may be applied to the pins by applying a voltage to the semiconductor substrate. Furthermore, as the degree of integration of semiconductor devices increases, short channel effects, which may be problematic, may also be suppressed.

Claims (7)

Semiconductor substrates; At least a pair of fins each protruding from the semiconductor substrate and spaced apart from each other; An insulating layer formed between the pair of fins; A storage node formed on the pair of fins and a portion of the surface of the insulating layer; And And a gate electrode formed on the storage node. The method of claim 1, A source and a drain formed on the pair of pins, the source and the drain being spaced apart from each other about an area where the pair of pins and the storage node contact each other; And And a pair of channel regions each formed near at least an inner surface of the pair of fin portions between the source and the drain. The method of claim 2, And the width of the pair of fins in an area in which the storage node contacts is smaller than the width of the pair of fins in an area in which the source and drain are formed. The method of claim 1, And an oxide layer formed between the semiconductor substrate and the storage node. The method of claim 1, The storage node may be formed of polysilicon, silicon-germanium, metal dots, silicon dots, or silicon nitride films. The method of claim 1, And the storage node is formed of a dielectric material, a resistance conversion material, a phase change material, or a ferroelectric material. The method of claim 1, And the semiconductor substrate comprises bulk silicon, bulk silicon-germanium, or a silicon or silicon-germanium epi layer thereon.

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