JP2006147861A - Semiconductor element and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To operate a tunnel effect element which shows negative differential resistance characteristic and to increase a peak current value. <P>SOLUTION: The semiconductor element has a first semiconductor region 11 constituting a channel region; a gate electrode 13 formed on the region 11 via a gate insulating film 12; a source electrode 14 and a drain electrode 15 formed in both sides of the region 11 corresponding to the gate electrode 13; an n<SP>+</SP>type second semiconductor region 16 which is formed between the region 11 and the source electrode 14, and has higher impurity concentration than the region 11, and a p<SP>+</SP>type third semiconductor region 17 which is formed between the region 11 and the drain electrode 15, and has a higher impurity concentration than the region 11. The part of the semiconductor regions 16, 17 in contact with the channel region is depleted all over a channel length direction with no voltage applied, and a tunnel diode is formed between the channel region and the semiconductor regions 16, 17. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor element such as a tunnel effect element that exhibits negative differential resistance characteristics, and more particularly to a semiconductor element that is improved in source / drain. The present invention also relates to a semiconductor device such as a semiconductor memory device or a semiconductor logic circuit device configured using this semiconductor element.

Silicon LSI has been improved in performance by miniaturizing CMOS elements. However, CMOS operation becomes very difficult at 0.1 μm as a boundary. The cause is a short channel effect typified by punch-through. In order to overcome such limitations of the CMOS device, a device based on a new operation principle, for example, a surface junction tunnel device has been proposed (see, for example, Patent Document 1). The structure of the surface junction tunnel element is similar to that of a normal MOSFET, and the difference is that the impurity types of the source and drain are opposite to each other. In other words, one has an n ⁺⁺ region source and the other a p ⁺⁺ region drain with the gate electrode interposed therebetween.

In the surface junction tunnel element, if no voltage is applied to the gate, normal pn junction characteristics appear between the source and the drain, and current flows when a constant drain voltage is applied. On the other hand, when a voltage is applied to the gate, an n ⁺ -p ⁺⁺ junction, so-called Esaki diode, is formed near the drain. Esaki diodes exhibit negative differential resistance characteristics due to the tunnel effect. With the same effect, the surface junction tunnel element also has a negative differential resistance function. Therefore, the surface junction tunnel element has both the current modulation function (switching function) by the gate and the Esaki diode function, and can overcome the disadvantages of the Esaki diode circuit.

Thus, since there is only one depletion layer region in the surface junction tunnel element, the problem of punch-through does not occur in principle. Also, since it uses a micro phenomenon called tunnel effect, it operates normally even in the ultrafine region. Further, since the element has functionality, there is an advantage that a functional circuit can be easily configured.
JP-A-9-260690

However, the above-described silicon tunnel effect element (surface junction tunnel element) has a problem that the current value is small. Although a large current value is required for actual circuit design, in the prior art, the current density of the tunnel current in the silicon device is 1 A / cm ² , and the current density of the tunnel current in the compound semiconductor device is 10 ^3. At present, the current value is inferior to that of A / cm ² . Regarding the surface junction tunnel element, a silicon element is desirable from the viewpoint of incorporation into an LSI. For circuit design using a current modulation function by a gate voltage, improvement of the peak current value showing the negative differential resistance characteristic becomes a problem. .

  As described above, in the conventional tunnel effect element, the circuit performance is determined by the peak current of the tunnel current. However, the silicon element has a problem that the peak current value is low because the effective mass is large.

  The present invention has been made in view of the above circumstances, and the object of the present invention is to exhibit the operation of a tunnel effect element that exhibits negative differential resistance characteristics and to increase the peak current value. It is to provide a semiconductor device to be obtained.

  Another object of the present invention is to provide a semiconductor device capable of realizing a semiconductor memory device, a semiconductor logic circuit device, or the like using the semiconductor element.

  In order to solve the above problems, the present invention adopts the following configuration.

That is, according to one embodiment of the present invention, a first semiconductor region that forms a channel region, a gate electrode formed over the first semiconductor region with a gate insulating film interposed therebetween, and the gate electrode corresponding to the gate electrode A source electrode and a drain electrode formed on both sides of the first semiconductor region, and n ⁺ having an impurity concentration higher than that of the first semiconductor region formed between the first semiconductor region and the source electrode. A second semiconductor region of a type, and a third semiconductor region of a p ⁺ type formed between the first semiconductor region and the drain electrode and having an impurity concentration higher than that of the first semiconductor region. A portion of the second and third semiconductor regions in contact with the channel region is depleted over the entire channel length direction when no voltage is applied, and the channel region and the first semiconductor region are provided. 2 and And a tunnel diode is formed between the third semiconductor region and the third semiconductor region.

According to one embodiment of the present invention, a first semiconductor region that forms a channel region, a gate electrode formed over the first semiconductor region with a gate insulating film interposed therebetween, and the gate electrode corresponding to the gate electrode A source electrode and a drain electrode formed on both sides of the first semiconductor region, and n ⁺ having an impurity concentration higher than that of the first semiconductor region formed between the first semiconductor region and the source electrode. A second semiconductor region of a type, and a third semiconductor region of a p ⁺ type formed between the first semiconductor region and the drain electrode and having an impurity concentration higher than that of the first semiconductor region. A semiconductor element comprising the second and third semiconductor regions, wherein the impurity concentration of the second and third semiconductor regions is 1 × 10 ¹⁹ cm ⁻³ or more, and the portions of the second and third semiconductor regions that are in contact with the channel region The thickness in the channel length direction is 10 It is formed to be less than nm and thinner than the depletion layer width determined by the impurity concentration.

According to one embodiment of the present invention, a first semiconductor region that forms a channel region, a gate electrode formed over the first semiconductor region with a gate insulating film interposed therebetween, and the gate electrode corresponding to the gate electrode A source electrode and a drain electrode formed on both sides of the first semiconductor region, and n ⁺ having an impurity concentration higher than that of the first semiconductor region formed between the first semiconductor region and the source electrode. A second semiconductor region of a type, and a third semiconductor region of a p ⁺ type formed between the first semiconductor region and the drain electrode and having an impurity concentration higher than that of the first semiconductor region. The semiconductor element is characterized in that the steepness of the impurity profile of the second and third semiconductor regions is 4 nm / decade or less.

In one embodiment of the present invention, a first semiconductor region that forms a channel region, and first and second gate electrodes formed above and below the first semiconductor region with gate insulating films interposed therebetween, The source and drain electrodes formed on both sides of the first semiconductor region corresponding to the gate electrodes, and the first semiconductor formed between the first semiconductor region and the source electrode An n ⁺ -type second semiconductor region having an impurity concentration higher than that of the region, and p ⁺ having an impurity concentration higher than that of the first semiconductor region formed between the first semiconductor region and the drain electrode. And a portion of the second and third semiconductor regions in contact with the channel region is depleted over the entire channel length direction when no voltage is applied. And A tunnel diode is formed between the channel region and the second and third semiconductor regions.

  Another embodiment of the present invention is a semiconductor element having the above structure, a load element having one end connected to the drain electrode of the semiconductor device and the other end connected to a power source, and a source connected to the drain electrode of the semiconductor device. And a MOS transistor having a drain connected to a bit line and a gate connected to a word line.

  Another embodiment of the present invention includes a voltage controlled oscillation circuit including the semiconductor element having the above structure and a series circuit of a resistor and an inductance element inserted between the semiconductor device and a power source. A semiconductor device characterized by the above.

  According to the present invention, by configuring the second and third semiconductor regions formed between the channel region and the source and drain electrodes as described above, the thickness of the source / drain impurity regions made of the semiconductor regions can be reduced. In addition to being extremely thin and highly concentrated, it can be regarded as a tunnel effect element in which the region is completely depleted. The concentration gradient of the semiconductor region is 5 to 7 nm / decade in the prior art, and is 4 nm / decade or less according to the present invention. When the tunnel distance is estimated from this and the tunnel current value is calculated, the improvement is 3 digits or more compared to the conventional technique.

  Therefore, according to the present invention, a tunnel effect element having a negative resistance characteristic with a high peak current value of a tunnel current by gate control can be realized with silicon, and performance equivalent to that of a compound semiconductor can be achieved.

  The details of the present invention will be described below with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a sectional view showing a schematic configuration of a silicon tunnel effect element according to the first embodiment of the present invention.

A gate electrode 13 is formed on a silicon substrate (first semiconductor region) 11 via a gate insulating film 12, and a source electrode 14 and a drain electrode 15 are formed on the surface of the substrate 11 with the gate electrode 13 interposed therebetween. Yes. An n ⁺ region (second semiconductor region) 16 is formed between the source electrode 14 and the substrate 11, and a p ⁺ region (third semiconductor region) 17 is formed between the drain electrode 15 and the substrate 11. Has been.

The first semiconductor region 11 is a p-type layer doped with B (boron), for example, and forms a channel region. The second semiconductor region 16 is, for example, an n ⁺ type layer doped with As at a high concentration, and the third semiconductor region 17 is, for example, a p ⁺ type layer doped with B at a high concentration. The second and third semiconductor regions 16 and 17 are formed extremely thin with the first semiconductor region 11 sandwiched from the channel length direction. The source / drain electrodes 14 and 15 are made of a metal such as Co or Ni or a silicide thereof, and form a Schottky junction with the first and second semiconductor regions 16 and 17.

In the present embodiment, the impurity concentrations of the second and third semiconductor regions 16 and 17 serving as the source / drain regions are extremely high and the thickness is reduced, so that the second and third semiconductor regions 16 and 17 are substantially formed. It is characterized by being completely depleted. That is, the second and third semiconductor regions 16 and 17 are formed to a thickness that allows the entire channel length direction to be depleted when no voltage is applied. In the present embodiment, the thicknesses of the second and third semiconductor regions 16 and 17 are set to 10 nm or less, and the impurity concentration is set to 1 × 10 ²⁰ cm ⁻³ , whereby the second and third semiconductor regions are set. 16 and 17 are completely depleted.

When a positive voltage is applied to the gate electrode 13 of this embodiment, an inversion layer (n ⁺ type) is formed on the surface of the silicon substrate 11, and a tunnel diode is formed around the p ⁺ type third semiconductor region 17. . When a negative voltage is applied to the gate electrode 13, a storage layer (p ⁺ type) is formed on the surface of the silicon substrate 11, and a tunnel diode is formed around the n ⁺ type second semiconductor region 16.

  As a result, as shown in FIGS. 2A and 2B, the negative differential resistance characteristic is exhibited with respect to the gate voltage in any direction, and the characteristic changes according to the gate voltage.

The tunnel current in this embodiment is estimated. Consider a case where an inversion layer is formed in a channel. The result is the same for the storage layer. The depletion layer thickness W of the pn junction formed by the third semiconductor region 17 (p ⁺ ) and the channel inversion layer (n ⁺ ) is:

It is.

Where ε _s is the dielectric constant of silicon, V _bi is the built-in potential, q is the elementary charge, and a is the gradient of the impurity concentration. When the steepness of the impurity profile of the third semiconductor region 17 is D [nm / decade] and the impurity concentration is N, it can be approximated as a = N / D. Therefore, the equation (1) is expressed as follows.

Further, according to the WKB approximation, the tunnel current is given as follows in a form proportional to the tunnel probability.

Where m ^* is the effective mass of silicon, E _g is the energy gap of silicon, and h is the Planck constant. E is an electric field applied to the tunnel junction, and E = E _g / W. Therefore, the expression (3) can be expressed by the steepness D of the impurity profile of the third semiconductor region 17.

  FIG. 3 shows a plot of equation (4).

  The steepness (D1) of the impurity profile of the third semiconductor region according to the prior art is D1 = 5 to 7 nm / decade, and according to this embodiment, the steepness (D2) of the impurity profile of the third semiconductor region is D2 = 4 nm / decade or less. According to equation (4), the tunnel current value can be estimated to be improved by two orders of magnitude or more compared to the conventional technique.

  The experimental results obtained using the following segregation joining technique and the experimental results according to the prior art are also shown. With respect to the element of the present embodiment, the experiment showed that the tunnel current value was improved by about two orders of magnitude.

Note that complete depletion of the second and third semiconductor regions 16 and 17 can be confirmed, for example, from measurement of junction capacitance or concentration measurement by EDX. Here, a profile by SIMS measurement is specifically shown. FIG. 4 is a SIMS profile of As and Co of the source / drain electrode part according to the present embodiment. The Co sputtering film thickness before silicidation is 12 nm. In the SIMS profile, micro unevenness at the interface makes the profile appear broad, so that the impurity profile is estimated in consideration of this and becomes 2.5 nm / decade. Note that a more steep impurity profile can be achieved by optimizing the manufacturing process. Regarding the peak impurity concentration, a concentration of 1 × 10 ¹⁹ cm ⁻³ or more is required for the development of interband tunneling.

  As described above, when an extremely high concentration impurity is introduced into a thin region, it is very difficult to control the concentration and depth. However, this can be realized very easily by using, for example, the segregation bonding method described here.

  FIG. 5 is a process cross-sectional view for explaining the principle of the segregation bonding method. When siliciding a semiconductor substrate containing impurities, a region deeper than the ion-implanted depth is silicidized, so that a very high concentration impurity can be introduced into a thin region by utilizing a segregation phenomenon. In the figure, 21 is a silicon substrate, 22 is a mask insulating film, 23 is an impurity ion implantation region, 24 is a silicide film, and 26 is a high concentration impurity region.

Specifically, for example, As ion implantation is performed at an acceleration voltage of 30 keV and a dose amount of 2 × 10 ¹⁵ cm ⁻² to form an impurity ion implantation region 23 as shown in FIG. Subsequently, for example, a metal such as nickel (Ni) is formed to a thickness of about 10 nm by sputtering or the like, and annealed at, for example, 300 to 500 ° C. for about 30 to 200 seconds. After silicidation, unreacted Ni is removed. As a result, a metal electrode (silicide film) 24 is formed. As the metal electrode 24 is formed, the impurity ion implantation region 23 is pushed out toward the substrate 21, thereby forming a very thin high-concentration second semiconductor region 26 between the metal electrode 24 and the channel region. become. Specifically, the thickness of the second semiconductor region 26 in the channel direction was 10 nm, and the impurity concentration was 1 × 10 ²⁰ cm ⁻³ .

  That is, as shown in FIG. 5A, after the impurity is ion-implanted shallowly near the surface of the silicon substrate 21, silicidation is performed to a position deeper than the implantation depth (depth at which the impurity concentration has a peak). As shown in FIG. 5B, the high concentration impurity region 26 can be formed in an extremely narrow range from the end of the silicide film 24. This is because the diffusion of impurities does not occur at the silicidation temperature, and the junction depth and impurity concentration can be controlled by the segregation phenomenon accompanying silicidation. Even if there are variations in impurity concentration and depth in the first ion implantation, the influence can be minimized. In this way, a very steep impurity profile (having a very small value of D) that cannot be obtained by the prior art can be realized.

  As described above, the structure of the tunnel effect element according to the present embodiment is such that the thickness of the source / drain region composed of the second and third semiconductor regions 16 and 17 is extremely thin and the concentration is high, and the region is completely depleted. It can be regarded as a tunnel element. This has the advantage of making it possible to create a steep impurity profile and increasing the effective tunneling current. Therefore, good negative differential resistance characteristics can be realized, and the amount of tunnel current can be increased. This is extremely important when actually designing a circuit.

In this embodiment, a normal silicon substrate is used, but an SOI substrate can also be used. FIG. 6 shows an example using an SOI substrate, in which 31 is a silicon layer (first semiconductor region), 33 is a gate electrode, 34 is a source electrode, 35 is a drain electrode, and 36 is an n ⁺ region (second region). , 37 is a p ⁺ region (third semiconductor region), 38 is a silicon substrate, and 39 is a buried insulating film.

  Since the parasitic pn junction can be eliminated by using the element formation substrate as the SOI substrate, the negative differential resistance characteristic is further improved. Thus, it can be used with various modifications depending on the situation.

(Second Embodiment)
7 and 8 are diagrams for explaining a schematic configuration of the tunnel effect element according to the second embodiment of the present invention. FIG. 7 is a plan view, and FIG. 8 is a cross-sectional view taken along line AA ′ in FIG. FIG. In the figure, 41 is a silicon layer (first semiconductor region), 42 is a gate insulating film, 43 is a gate electrode, 44 is a source electrode, 45 is a drain electrode, and 46 is an n ⁺ region (second semiconductor region). , 47 are p ⁺ regions (third semiconductor regions), 51 is an insulating film for element isolation, 52 is an interlayer insulating film, and 53 is a wiring.

  As shown in FIG. 7, an element isolation region 51 is formed so as to surround the element region of the silicon substrate 41. The gate electrode 43 is formed so as to surround the drain electrode 45, and the drain electrode 45 is formed away from the element isolation region 51. The source electrode 44 and the drain electrode 45 are formed in the element region so as to sandwich the gate electrode 43 from both sides. The gate contact is connected to the gate electrode on the element isolation region 51 in order to prevent delay due to capacitance.

  The basic element structure is the same as that of the first embodiment. A gate electrode 44 is formed on a silicon substrate (first semiconductor region) 41 with a gate insulating film 42 interposed therebetween. Second and third semiconductor regions 46 and 47 and source / drain electrodes 44 and 45 are formed. However, the gate electrode 43 is formed so as to surround the drain electrode 45 and the drain region 46 as described above.

  The conductivity types and impurities of the first to third semiconductor regions 41, 46, and 47 are the same as those in the first embodiment. The source / drain electrodes 44 and 45 are made of metal or silicide and form Schottky junctions with the second and third semiconductor regions 44 and 47.

  Similar to the first embodiment, the impurity concentrations of the second and third semiconductor regions 46 and 47 to be the source / drain regions are made extremely high and the thickness is reduced, so that the second and third semiconductor regions 46 and 47 are formed. 47 is formed to a thickness that allows the entire channel length direction to be depleted when no voltage is applied.

  In the structure of the surface junction tunnel device according to the present embodiment, it is possible to create a steep impurity profile and increase the effective tunnel current, and the Esaki diode is not formed in contact with the device isolation end. It has both of the advantages of the surface junction tunnel element that the leakage current caused by the element isolation end can be eliminated. Therefore, good negative differential resistance characteristics can be realized, and the amount of tunnel current can be increased.

When the storage layer is formed on the silicon surface and the device is operated, the source electrode 43 and the n ⁺ region 46 may be surrounded by the gate electrode 43, contrary to FIG. Further, both regions can be surrounded by the gate electrode 43. Furthermore, although a normal silicon substrate is used in this embodiment, it is of course possible to use an SOI substrate.

(Third embodiment)
FIG. 9 is a sectional view showing a schematic configuration of a double gate type tunnel effect element according to the third embodiment of the present invention. First, second, and third semiconductor regions 61, 66, and 67, a source electrode 64, and a drain electrode 65 are formed on a semiconductor substrate (not shown). Then, first and second gate electrodes 63 and 69 are formed above and below the first, second and third semiconductor regions via a gate insulating film.

The first semiconductor region 61 is a p-type layer doped with, for example, B (boron) and forms a channel region. The second semiconductor region 64 is an n ⁺ type layer doped with, for example, As at a high concentration, and the third semiconductor region 65 is a p ⁺ type layer doped with, for example, a high concentration of B. The region 61 is formed extremely thin across the channel length direction. The source / drain electrodes 64 and 65 are made of metal or silicide, and are formed by sandwiching the first, second and third semiconductor regions 61, 66 and 67 from the channel length direction, and the semiconductor regions 66 and 67 are Schottky. A junction is formed.

When a voltage is applied to the first and second gate electrodes 63 and 69 of the present embodiment, the “volume inversion” effect (F. Balestra, et al., “Double-gate silicon-0n-insulator transistor with volume inversion: A new device”). with greatly enhanced performance, "IEEE Electron Device Lett., vol. EDL-8, no. 9, pp. 410-412, 1987)), an inversion layer (n ⁺ type) is formed inside the first semiconductor region 61. A tunnel diode is formed around the drain region which is formed and is the p ⁺ -type third semiconductor region 65.

  In the tunnel effect element, defects at the tunnel junction interface cause a large leakage current. When the leak current is large, the tunnel current is hidden in the leak current component, and thus reducing the leak current by controlling the defects in the tunnel junction is a big problem. By using the structure of this embodiment, the tunnel junction does not have a common contact with the insulating film, and is not affected by defects at the silicon / insulating film interface.

  Therefore, according to the present embodiment, the leakage current can be reduced, the peak current / valley current ratio can be greatly improved, and good negative resistance characteristics can be obtained.

(Fourth embodiment)
FIG. 10 is an equivalent circuit diagram showing an SRAM cell according to the fourth embodiment of the present invention. This SRAM cell is composed of, for example, a memory signal storage unit including the tunnel effect element 71 and the load element 72 of the first embodiment, and a MOS transistor 73.

  The tunnel effect element 71 and the load element 72 are connected in series between the power supply terminal and the ground terminal. The source of the MOS transistor 73 is connected to the connection point between the tunnel effect element 71 and the load element 72, the drain is connected to the bit line BL, and the gate is connected to the word line WL.

  FIG. 11 shows current / voltage characteristics of the element of this embodiment in the SRAM cell configured as described above. Two stable states are taken at the intersection of the characteristic curve of the element of the present embodiment and the characteristic curve of the load element, and these stable states are used for the stored signal. The stored charge is written and read by a MOS transistor. Since the number of elements is as small as three, it is suitable for high integration.

  By the way, in this type of SRAM cell, a constant level of drive current (tunnel current) I0 always flows in the conventional Esaki diode, so that the power consumption during standby and the reading speed of the memory signal can be improved at the same time. It was difficult. This is because the drive current I0 needs to be reduced in order to reduce power consumption during standby, whereas the drive current I0 needs to be increased in order to increase the reading speed.

  According to the present embodiment, the tunnel current can be controlled by the gate voltage by using the tunnel effect element of the first embodiment. Furthermore, a large tunnel current value can be obtained as compared with the conventional tunnel element. As a result, according to the present embodiment, the tunnel current can be increased and the stored signal can be read at high speed. Further, according to the present embodiment, the tunnel current can be reduced by adjusting the gate voltage, and the power consumption during standby can be reduced.

  As described above, according to the element of this embodiment, an SRAM cell effective for high integration, low power consumption, and high-speed operation can be realized.

(Fifth embodiment)
FIG. 12 is an equivalent circuit diagram showing a voltage controlled oscillation circuit (VCO) according to the fifth embodiment of the present invention. This voltage controlled oscillation circuit is composed of the tunnel effect element and the RL circuit of the first embodiment, for example.

  One end of the tunnel effect element 81 is connected to the minus end of the power supply 82, and the other end of the tunnel effect element 81 is simply connected to the plus of the power supply 82 via a series circuit of a resistor 83 (R) and an inductor 84 (L). Yes. An output voltage Vout is taken out from both ends of the tunnel effect element 81.

  FIG. 13 shows the oscillation characteristics in this embodiment. In the present embodiment, an oscillation characteristic in which the output voltage oscillates with time can be obtained by the negative differential resistance characteristic of the tunnel effect element 81. Further, the frequency of the oscillation characteristic can be modulated by adjusting the gate voltage of the tunnel effect element 81. By adopting the structure of the present embodiment, it is possible to have a VCO function required for an analog circuit and to realize on-chip implementation.

  By the way, in the voltage controlled oscillation circuit of this kind of configuration, since the oscillation frequency depends on the peak current, it is necessary to improve the tunnel current amount when the tunnel effect element is used. In this case, by using the first tunnel effect element, a large amount of tunnel current can be obtained, and a higher frequency (high speed) VCO circuit can be realized.

(Modification)
The present invention is not limited to the above-described embodiments. The impurity concentration and thickness of the second and third semiconductor regions can be changed as appropriate within the range in which a tunnel diode is formed between the channel region and the entire channel length direction when no voltage is applied. It is. In other words, the steepness of the impurity profiles of the second and third semiconductor regions can be appropriately changed within a range where the steepness is 4 nm / decade or less. More specifically, the impurity concentration may be 1 × 10 ¹⁹ cm ⁻³ or more necessary for the development of band-to-band tunneling. Furthermore, the film thickness in the channel direction may be 10 nm or less through which a tunnel current flows.

  Further, the method for forming the second and third semiconductor regions is not necessarily limited to the segregation junction formation method, and any method can be used as long as the high-concentration impurity layer can be formed sufficiently thin. The semiconductor material and the metal material for forming the source / drain electrodes are not limited to Ni and Co, and can be appropriately changed according to the specifications. The semiconductor element of the present invention is not limited to a semiconductor memory device or a semiconductor logic circuit device, but can be applied to various semiconductor devices using a tunnel effect element having negative differential resistance characteristics. .

  In addition, various modifications can be made without departing from the scope of the present invention.

Sectional drawing which shows schematic structure of the silicon tunnel effect element concerning 1st Embodiment. The figure which shows the Vd-Id characteristic in 1st Embodiment. The figure which plots and shows (4) Formula. The figure which shows the SIMS profile of As and Co of a source / drain electrode part. Process sectional drawing for demonstrating the principle of a segregation joining formation method. Sectional drawing which shows the example using an SOI substrate. The top view which shows schematic structure of the tunnel effect element concerning 2nd Embodiment. Sectional drawing which shows schematic structure of the tunnel effect element concerning 2nd Embodiment. Sectional drawing which shows schematic structure of the double gate type | mold tunnel effect element concerning 3rd Embodiment. The equivalent circuit diagram which shows the SRAM cell concerning 4th Embodiment. The figure which shows the electric current and voltage characteristic of SRAM concerning 4th Embodiment. FIG. 9 is an equivalent circuit diagram showing a voltage controlled oscillation circuit (VCO) according to the fifth embodiment. The figure which shows the oscillation characteristic of the voltage control oscillation circuit (VCO) concerning 5th Embodiment.

Explanation of symbols

11, 21... Silicon substrate (first semiconductor region)
12, 42 ... Gate insulating film 13, 33, 43 ... Gate electrode 14, 34, 44, 64 ... Source electrode 15, 35, 45, 65 ... Drain electrode 16, 36, 46, 66 ... n ⁺ source region (second Semiconductor area)
17, 37, 47, 67... P ⁺ drain region (third semiconductor region)
22 ... Mask insulating film 23 ... Impurity ion implantation region 24 ... Silicide film 26 ... High concentration impurity region 31, 41, 61 ... Silicon layer (first semiconductor region)
DESCRIPTION OF SYMBOLS 38 ... Silicon substrate 39 ... Embedded insulating film 51 ... Element isolation insulating film 52 ... Interlayer insulating film 53 ... Wiring 63 ... First gate electrode 69 ... Second gate electrode 71, 81 ... Tunnel effect element 72 ... Load element 73 ... MOS transistor 73
82 ... Power supply 83 ... Resistance (R)
84: Inductor (L)

Claims (8)

A first semiconductor region constituting a channel region; a gate electrode formed on the first semiconductor region via a gate insulating film; and formed on both sides of the first semiconductor region corresponding to the gate electrode A source electrode and a drain electrode, and an n ⁺ -type second semiconductor region formed between the first semiconductor region and the source electrode and having an impurity concentration higher than that of the first semiconductor region; A p ⁺ -type third semiconductor region formed between the first semiconductor region and the drain electrode and having an impurity concentration higher than that of the first semiconductor region;
Portions of the second and third semiconductor regions that are in contact with the channel region are depleted over the entire channel length direction when no voltage is applied, and the portion between the channel region and the second and third semiconductor regions is depleted. A tunnel diode is formed in the semiconductor element. A first semiconductor region constituting a channel region; a gate electrode formed on the first semiconductor region via a gate insulating film; and formed on both sides of the first semiconductor region corresponding to the gate electrode A source electrode and a drain electrode, and an n ⁺ -type second semiconductor region formed between the first semiconductor region and the source electrode and having an impurity concentration higher than that of the first semiconductor region; A p ⁺ -type third semiconductor region formed between the first semiconductor region and the drain electrode and having an impurity concentration higher than that of the first semiconductor region;
The impurity concentration of the second and third semiconductor regions is 1 × 10 ¹⁹ cm ⁻³ or more, and the thickness in the channel length direction of the portion of the second and third semiconductor regions in contact with the channel region is 10 nm or less. The semiconductor element is formed to be thinner than a depletion layer width determined by the impurity concentration. A first semiconductor region constituting a channel region; a gate electrode formed on the first semiconductor region via a gate insulating film; and formed on both sides of the first semiconductor region corresponding to the gate electrode A source electrode and a drain electrode, and an n ⁺ -type second semiconductor region formed between the first semiconductor region and the source electrode and having an impurity concentration higher than that of the first semiconductor region; A p ⁺ -type third semiconductor region formed between the first semiconductor region and the drain electrode and having an impurity concentration higher than that of the first semiconductor region;
A semiconductor element, wherein the steepness of the impurity profile of the second and third semiconductor regions is 4 nm / decade or less.   The semiconductor element according to claim 1, wherein the first semiconductor region is formed on an insulating film.   5. The semiconductor element according to claim 1, wherein the first to third semiconductor regions are silicon, and the source electrode and the drain electrode are metal or silicide. A first semiconductor region constituting a channel region, first and second gate electrodes formed above and below the first semiconductor region via gate insulating films, respectively, and corresponding to each of the gate electrodes A source electrode and a drain electrode formed on both sides of the first semiconductor region, and n ⁺ having an impurity concentration higher than that of the first semiconductor region formed between the first semiconductor region and the source electrode. A second semiconductor region of a type, and a third semiconductor region of a p ⁺ type formed between the first semiconductor region and the drain electrode and having an impurity concentration higher than that of the first semiconductor region. Equipped,
Portions of the second and third semiconductor regions that are in contact with the channel region are depleted over the entire channel length direction when no voltage is applied, and the portion between the channel region and the second and third semiconductor regions is depleted. A tunnel diode is formed in the semiconductor element.   The semiconductor element according to claim 1, one end connected to the drain electrode of the semiconductor device, the other end connected to a power source, and a source connected to the drain electrode of the semiconductor device. And a memory signal storage unit comprising a MOS transistor having a drain connected to a bit line and a gate connected to a word line.   A voltage-controlled oscillation circuit comprising: the semiconductor element according to claim 1; and a series circuit of a resistor and an inductance element inserted between the semiconductor device and a power source. A featured semiconductor device.

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