KR20070089542A - Method for fabricating the same of semiconductor device with recess gate - Google Patents

Method for fabricating the same of semiconductor device with recess gate Download PDF

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KR20070089542A
KR20070089542A KR1020060019718A KR20060019718A KR20070089542A KR 20070089542 A KR20070089542 A KR 20070089542A KR 1020060019718 A KR1020060019718 A KR 1020060019718A KR 20060019718 A KR20060019718 A KR 20060019718A KR 20070089542 A KR20070089542 A KR 20070089542A
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recess
gate
semiconductor device
forming
semiconductor substrate
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KR1020060019718A
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Korean (ko)
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남상혁
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주식회사 하이닉스반도체
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Publication of KR20070089542A publication Critical patent/KR20070089542A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method for manufacturing a semiconductor device with a recess gate is provided to secure characteristics and reliability of the semiconductor device by forming symmetrically source/drain regions regardless of the misalignment of a gate pattern. A recess(25) is formed by etching selectively a semiconductor substrate(21). Source/drain regions(27) are formed on the resultant structure by implanting dopants into the substrate. A gate pattern is formed on the resultant structure. At this time, the recess is completely filled with the gate pattern and an upper portion of the gate pattern is protruded from the substrate. The recess is formed on the substrate by using a pad pattern composed of a pad oxide layer and a nitride layer as an etch mask. The nitride layer is removed from the resultant structure after the recess forming process. The nitride layer is removed by a wet etching process.

Description

리세스 게이트를 갖는 반도체 소자의 제조방법{METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE WITH RECESS GATE}A method of manufacturing a semiconductor device having a recess gate {METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE WITH RECESS GATE}

도 1은 종래 기술에 따른 리세스 게이트를 갖는 반도체 소자를 설명하기 위한 단면도,1 is a cross-sectional view illustrating a semiconductor device having a recess gate according to the prior art;

도 2a 내지 도 2e는 본 발명의 바람직한 실시예에 따른 리세스 게이트를 갖는 반도체 소자의 제조방법을 설명하기 위한 공정 단면도,2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate according to an exemplary embodiment of the present invention;

도 3은 본 발명의 바람직한 실시예에 따른 리세스 게이트를 갖는 반도체 소자를 설명하기 위한 단면도.3 is a cross-sectional view illustrating a semiconductor device having a recess gate in accordance with a preferred embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체 소자 22 : 패드산화막21 semiconductor device 22 pad oxide film

23 : 패드질화막 24 : 소자분리막23: pad nitride film 24: device isolation film

25 : 리세스 26 : 절연막25 recess 26 insulating film

27 : 소스/드레인 28 : 게이트패턴27: source / drain 28: gate pattern

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 리세스 게이트를 갖는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a recess gate.

반도체 소자가 초고집적화 됨에 따라 게이트를 평탄한 활성영역 위에 형성하는 기존의 플라나 게이트(Planar Gate)배선 형성 방법은 게이트 채널길이(Gate channel Length)가 점점 작아지고 이온주입도핑(Implant Dopping)농도가 증가함에 따라 전계(Electric Filed) 증가에 의해 접합 누설전류(Junction Leakage)가 생겨 소자의 리프레시특성을 확보하기가 어렵다.As the semiconductor devices become highly integrated, the conventional planar gate wiring forming method for forming a gate over a flat active region becomes smaller as the gate channel length and the ion implantation doping concentration increase. As a result, an increase in electric filed causes junction leakage, which makes it difficult to secure refresh characteristics of the device.

이를 개선하기 위해 게이트 배선 형성방법으로 활성영역 기판을 리세스패턴으로 식각 후 게이트를 형성하는 리세스 게이트 공정이 실시되고 있다. 상기 리세스 게이트 공정을 적용하면 채널길이 증가 및 이온주입 도핑 농도의 감소가 가능하여 소자의 리프레시 특성이 개선된다.In order to improve this, a recess gate process is performed in which a gate is formed after the active region substrate is etched into the recess pattern using a gate wiring method. Applying the recess gate process can increase the channel length and decrease the ion implantation doping concentration, thereby improving the refresh characteristics of the device.

도 1은 종래 기술에 따른 리세스 게이트를 갖는 반도체 소자를 설명하기 위한 단면도이다.1 is a cross-sectional view for describing a semiconductor device having a recess gate according to the related art.

도 1에 도시된 바와 같이, 소자분리막(12)이 형성된 반도체 기판(11)에 리세스(13)를 형성하고, 리세스(13)에 일부 매립되고 나머지는 반도체 기판(11)에 돌출되는 게이트패턴(15)을 형성한다. 여기서, 게이트패턴(15)은 폴리실리콘막(15a)와 메탈전극(15b)이 순차로 적층된 구조로 형성할 수 있다.As shown in FIG. 1, a recess 13 is formed in the semiconductor substrate 11 on which the device isolation film 12 is formed, a portion of which is partially embedded in the recess 13, and the gate protrudes from the semiconductor substrate 11. The pattern 15 is formed. The gate pattern 15 may have a structure in which the polysilicon film 15a and the metal electrode 15b are sequentially stacked.

이어서, 게이트패턴(15) 사이의 반도체 기판(11)에 불순물을 주입하여 소스/ 드레인(14)을 형성한다.Subsequently, impurities are implanted into the semiconductor substrate 11 between the gate patterns 15 to form the source / drain 14.

그러나, 리세스(13)와 게이트패턴(15)간에 오정렬이 발생할 경우, 게이트패턴(15) 형성 후에 실시되는 소스/드레인(14) 형성 공정시 리세스(13)와 게이트패턴(15)이 오정렬 된 넓이만큼 반도체 기판(11)에 공간(Space, 100)이 남게되어 소스/드레인(14) 간의 대칭성이 파괴됨으로써 균일한 반도체 소자의 특성을 갖지 못하고, 특성 변화가 심해지는 문제점이 있다.However, when misalignment occurs between the recess 13 and the gate pattern 15, the recess 13 and the gate pattern 15 misalign during the process of forming the source / drain 14 performed after the gate pattern 15 is formed. Since the space 100 remains in the semiconductor substrate 11 as much as possible, the symmetry between the source and the drain 14 is destroyed, so that the characteristics of the semiconductor device 11 do not have uniform characteristics of the semiconductor device, and the characteristic change is severe.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 게이트 정렬 불량에 의한 소스/드레인의 비대칭을 방지하기 위한 리세스 게이트를 갖는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device having a recess gate for preventing asymmetry of a source / drain due to a gate misalignment.

상기 목적을 달성하기 위한 본 발명은 반도체 기판을 선택적으로 식각하여 리세스를 형성하는 단계, 상기 리세스를 포함한 반도체 기판에 불순물주입을 실시하여 소스/드레인을 형성하는 단계, 상기 리세스에 일부가 매립되고 나머지는 상기 반도체 기판 상부로 돌출되는 게이트패턴을 형성하는 단계를 포함한다.In accordance with another aspect of the present invention, there is provided a method of forming a recess by selectively etching a semiconductor substrate, and implanting impurities into a semiconductor substrate including the recess to form a source / drain. Forming a gate pattern buried and protruding above the semiconductor substrate.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자라 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, the present invention will be described in detail with reference to the accompanying drawings so that the present invention may be described in detail so that the technical idea of the present invention can be easily implemented. do.

도 2a 내지 도 2e는 본 발명의 바람직한 실시예에 따른 리세스 게이트를 갖는 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate according to an exemplary embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체 기판(21) 상에 패드산화막(22)과 패드질화막(23)을 순차로 형성한다.As shown in FIG. 2A, the pad oxide film 22 and the pad nitride film 23 are sequentially formed on the semiconductor substrate 21.

이어서, 도시되지는 않았지만 패드질화막(23) 상에 감광막을 형성하고 노광 및 현상으로 소자분리 영역을 오픈시킨다. 이어서, 감광막을 식각마스크로 패드질화막(23), 패드산화막(22)과 반도체 기판(21)을 식각하여 트렌치를 형성한 후, 산소플라즈마로 감광막을 제거한다. 이어서, 트렌치를 매립하는 절연막을 형성한 후 패드질화막(23)이 드러날때까지 평탄화 하여 소자분리막(24)을 형성한다.Subsequently, although not shown, a photoresist film is formed on the pad nitride film 23 and the device isolation region is opened by exposure and development. Subsequently, the pad nitride film 23, the pad oxide film 22, and the semiconductor substrate 21 are etched to form a trench using an etching mask, and then the photosensitive film is removed using an oxygen plasma. Subsequently, an insulating film filling the trench is formed and then planarized until the pad nitride film 23 is exposed to form the device isolation film 24.

여기서, 소자분리막(24)은 활성영역을 정의하기 위한 것으로, 적어도 후속 리세스보다 깊게 형성한다.In this case, the device isolation layer 24 is for defining an active region, and is formed at least deeper than a subsequent recess.

도 2b에 도시된 바와 같이, 반도체 기판(21)을 선택적으로 식각하여 리세스(25)를 형성한다.As shown in FIG. 2B, the semiconductor substrate 21 is selectively etched to form the recess 25.

리세스(25)를 형성하기 위해, 도시되지는 않았지만 패드질화막(23) 상에 감광막을 형성하고 노광 및 현상으로 리세스 예정지역을 오픈시킨다. 이어서, 감광막을 식각마스크로 패드질화막(23), 패드산화막(22)과 반도체 기판(21)을 식각하여 리세스(25)를 형성하고, 산소플라즈마로 감광막을 제거한다.In order to form the recess 25, although not shown, a photoresist film is formed on the pad nitride film 23, and the recess scheduled area is opened by exposure and development. Subsequently, the pad nitride film 23, the pad oxide film 22, and the semiconductor substrate 21 are etched using the photoresist as an etch mask to form a recess 25, and the photoresist is removed using an oxygen plasma.

이때, 소자분리막(24) 형성을 위한 패드산화막(22)과 패드질화막(23)을 제거하지 않고 그대로 리세스(25) 형성을 위한 하드마스크로 사용함으로써 공정을 단순화 시킬 수 있다.In this case, the process may be simplified by using the pad oxide layer 22 and the pad nitride layer 23 for forming the isolation layer 24 as a hard mask for forming the recess 25 without removing the pad oxide layer 22 and the pad nitride layer 23.

도 2c에 도시된 바와 같이, 리세스(25)를 매립하는 절연막(26)을 형성한다. 여기서, 절연막(26)은 후속 소스/드레인 형성을 위한 불순물 주입 공정시 방어막으로 사용하여 채널이 형성되는 리세스(25)에는 불순물 주입이 안되도록 하기 위한 것이다.As shown in FIG. 2C, an insulating film 26 filling the recess 25 is formed. In this case, the insulating layer 26 is used as a protective layer during the impurity implantation process for the subsequent source / drain formation so as to prevent impurity implantation into the recess 25 in which the channel is formed.

절연막(26)은 리세스(25)를 채울때까지 패드질화막(23) 상에 절연막층을 형성하고, 패드질화막(23)이 드러날때까지 평탄화(Chemical Mechanical Polishing;CMP)하여 형성할 수 있다. 여기서, 절연막(26)은 예컨대 실리콘산화막으로 형성할 수 있다.The insulating film 26 may be formed by forming an insulating film layer on the pad nitride film 23 until the recess 25 is filled, and planarizing (Chemical Mechanical Polishing (CMP)) until the pad nitride film 23 is exposed. Here, the insulating film 26 may be formed of, for example, a silicon oxide film.

도 2d에 도시된 바와 같이, 패드질화막(23)을 제거한다. 여기서, 패드질화막(23)은 습식식각으로 제거하되, 패드산화막(22)과 절연막(26)은 그대로 있도록 선택적으로 제거한다.As shown in FIG. 2D, the pad nitride film 23 is removed. Here, the pad nitride film 23 is removed by wet etching, but the pad oxide film 22 and the insulating film 26 are selectively removed to remain intact.

이어서, 리세스(25)와 소자분리막(24) 사이의 반도체 기판(21)에 불순물을 주입하여 소스/드레인(27)을 형성한다. 이때, 리세스(25)를 매립하고 있는 절연막(26)이 방어막 역할을 하여 반도체 소자의 채널내에 불순물이 주입되는 것을 방지한다. 그리고, 패드산화막(23)과 절연막(26)은 이온주입시 반도체 기판(21) 표면의 손상을 방지하는 역할을 한다.Subsequently, an impurity is implanted into the semiconductor substrate 21 between the recess 25 and the device isolation layer 24 to form a source / drain 27. At this time, the insulating film 26 filling the recess 25 serves as a protective film to prevent impurities from being injected into the channel of the semiconductor device. In addition, the pad oxide layer 23 and the insulating layer 26 may prevent damage to the surface of the semiconductor substrate 21 during ion implantation.

도 2e에 도시된 바와 같이, 절연막(26)을 제거한다. As shown in FIG. 2E, the insulating film 26 is removed.

여기서, 절연막(26)은 건식 또는 습식식각으로 제거하되, 반도체 기판(21)이 드러날때까지 식각한다. 또한, 절연막(26)의 제거와 동시에 패드산화막(22)과 반도체 기판(21) 상부로 돌출되어있는 소자분리막(24)도 일부 제거되어 반도체 기판 (21)의 표면은 평탄하게된다.In this case, the insulating layer 26 is removed by dry or wet etching, and is etched until the semiconductor substrate 21 is exposed. In addition, at the same time as the insulating layer 26 is removed, the pad oxide layer 22 and the device isolation layer 24 protruding over the semiconductor substrate 21 are also partially removed to make the surface of the semiconductor substrate 21 flat.

이어서, 리세스(25)에 일부가 매립되고 나머지는 반도체 기판(21) 상부로 돌출되는 게이트패턴(28)을 형성한다. 여기서, 게이트패턴(28)은 폴리실리콘막(28a)과 메탈전극(28b)가 순차로 적층된 구조로 형성할 수 있다. 또한, 메탈전극(28a)는 텅스텐 또는 텅스텐실리사이드로 형성할 수 있다.Subsequently, a portion of the recess 25 is embedded in the recess 25, and the gate pattern 28 is formed to protrude above the semiconductor substrate 21. Here, the gate pattern 28 may be formed in a structure in which the polysilicon layer 28a and the metal electrode 28b are sequentially stacked. In addition, the metal electrode 28a may be formed of tungsten or tungsten silicide.

도 3은 본 발명의 바람직한 실시예에 따른 리세스 게이트를 갖는 반도체 소자를 설명하기 위한 단면도이다.3 is a cross-sectional view for describing a semiconductor device having a recess gate according to an exemplary embodiment of the present invention.

도 3을 참조하면, 도 2a 내지 도 2e에 도시된 방법대로 소스/드레인을 형성하되 게이트패턴(35)이 리세스(33)와 오정렬 된 모습이다. Referring to FIG. 3, the source / drain is formed in the manner illustrated in FIGS. 2A to 2E, but the gate pattern 35 is misaligned with the recess 33.

이때, 도 1에서와 같이 게이트패턴을 형성한 후에 소스/드레인을 형성할 시 소스/드레인이 비대칭을 갖는 것과 달리, 게이트패턴(35)을 형성하기 전에 리세스(33) 형성 후 소스/드레인(34)을 형성하여 게이트패턴(35) 형성을 위한 포토(Photo)공정 시 발생되는 층간정렬 불량현상이 있더라도 이러한 게이트패턴(35)의 오정렬과 관계없이 대칭적인 소스/드레인(34)을 형성할 수 있다.In this case, unlike the source / drain having an asymmetry when the source / drain is formed after the gate pattern is formed, as shown in FIG. 1, the source / drain after the recess 33 is formed before the gate pattern 35 is formed. 34 may be used to form a symmetrical source / drain 34 regardless of misalignment of the gate pattern 35 even if there is an interlayer misalignment occurring during the photo process for forming the gate pattern 35. have.

설명되지 않은 도면부호 31은 반도체 기판, 32는 소자분리막, 35a는 폴리실리콘막, 35b는 메탈전극이다.Reference numeral 31, which is not described, denotes a semiconductor substrate, 32 an element isolation film, 35a a polysilicon film, and 35b a metal electrode.

상술한 본 발명은 게이트패턴을 형성하기 전에 리세스 형성 후 바로 소스/드레인을 형성하여 후속 게이트패턴 형성을 위한 포토공정 시 발생되는 층간정렬 불량현상이 있더라도 이러한 게이트패턴의 오정렬과 관계없이 대칭적인 소스/드레인을 형성할 수 있는 장점이 있다.According to the present invention, the source / drain is formed immediately after the recess is formed before the gate pattern is formed, and even though there is an interlayer misalignment occurring during the photo process for subsequent gate pattern formation, the source is symmetrical regardless of misalignment of the gate pattern. There is an advantage to form a drain.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명에 의한 리세스 게이트를 갖는 반도체 소자의 제조방법은 게이트패턴의 오정렬과 관계없이 대칭적인 소스/드레인을 형성하여 반도체 소자의 특성 및 신뢰성을 확보할 수 있는 효과가 있다.The above-described method of manufacturing a semiconductor device having a recess gate according to the present invention has an effect of securing characteristics and reliability of the semiconductor device by forming a symmetrical source / drain regardless of misalignment of the gate pattern.

Claims (5)

반도체 기판을 선택적으로 식각하여 리세스를 형성하는 단계;Selectively etching the semiconductor substrate to form a recess; 상기 리세스를 포함한 반도체 기판에 불순물주입을 실시하여 소스/드레인을 형성하는 단계; 및Impurity implantation into the semiconductor substrate including the recess to form a source / drain; And 상기 리세스에 일부가 매립되고 나머지는 상기 반도체 기판 상부로 돌출되는 게이트패턴을 형성하는 단계Forming a gate pattern which is partially embedded in the recess and protrudes above the semiconductor substrate 를 포함하는 리세스 게이트를 갖는 반도체 소자의 제조방법.Method for manufacturing a semiconductor device having a recess gate comprising a. 제1항에 있어서,The method of claim 1, 상기 리세스를 형성하는 단계는,Forming the recess, 상기 반도체 기판 상에 리세스 예정지역이 오픈되고 패드산화막과 질화막이 적층된 패드층패턴을 형성하는 단계; 및Forming a pad layer pattern on which the recess scheduled region is opened and a pad oxide film and a nitride film are stacked on the semiconductor substrate; And 상기 패드층패턴을 식각마스크로 상기 반도체 기판을 식각하여 리세스를 형성하는 단계Forming a recess by etching the semiconductor substrate using the pad layer pattern as an etch mask 를 포함하는 것을 특징으로 하는 리세스 게이트를 갖는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device having a recess gate, characterized in that it comprises a. 제2항에 있어서,The method of claim 2, 상기 리세스를 형성한 후,After forming the recess, 상기 리세스를 매립하면서 상기 패드층패턴 전면에 절연막을 형성하는 단계;Forming an insulating film on the entire surface of the pad layer pattern while filling the recess; 상기 패드층패턴이 드러날때까지 상기 절연막을 평탄화하는 단계; 및Planarizing the insulating film until the pad layer pattern is exposed; And 상기 패드층패턴의 질화막을 선택적으로 제거하는 단계Selectively removing the nitride film of the pad layer pattern 를 더 포함하는 것을 특징으로 하는 리세스 게이트를 갖는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device having a recess gate further comprising. 제3항에 있어서,The method of claim 3, 상기 질화막은 습식식각으로 제거하는 것을 특징으로 하는 리세스 게이트를 갖는 반도체 소자의 제조방법.The nitride film is a method of manufacturing a semiconductor device having a recess gate, characterized in that for removing by wet etching. 제3항에 있어서,The method of claim 3, 상기 절연막은,The insulating film, 상기 불순물주입을 실시한 후 건식 또는 습식식각으로 제거하는 것을 특징으로 하는 리세스 게이 트를 갖는 반도체 소자의 제조방법.And a method of manufacturing a semiconductor device having a recess gate, wherein the impurity implantation is performed to remove the wafer by dry or wet etching.
KR1020060019718A 2006-02-28 2006-02-28 Method for fabricating the same of semiconductor device with recess gate KR20070089542A (en)

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