KR20070079806A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20070079806A
KR20070079806A KR1020060010790A KR20060010790A KR20070079806A KR 20070079806 A KR20070079806 A KR 20070079806A KR 1020060010790 A KR1020060010790 A KR 1020060010790A KR 20060010790 A KR20060010790 A KR 20060010790A KR 20070079806 A KR20070079806 A KR 20070079806A
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South Korea
Prior art keywords
landing plug
semiconductor device
polysilicon layer
bit line
manufacturing
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KR1020060010790A
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Korean (ko)
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배경진
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주식회사 하이닉스반도체
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Priority to KR1020060010790A priority Critical patent/KR20070079806A/en
Publication of KR20070079806A publication Critical patent/KR20070079806A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to increase a contact area and to improve overlay characteristics by using a storage node contact landing plug with a height and size relatively large compared to those of a bit line contact landing plug. An interlayer dielectric(40) is formed on a semiconductor substrate(10) in which a gate(43) is formed. An etching process is performed on landing plug regions of the interlayer dielectric by using a first landing plug contact mask. A first polysilicon layer(60) for filling the landing plug regions is formed on the entire surface of the resultant structure. A storage node contact landing plug(110) and a bit line contact landing plug(100) are formed on the resultant structure by etching selectively the first polysilicon layer using a second landing plug contact mask. The height of the storage node contact landing plug is larger than that of the bit line contact landing plug.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도 1은 종래기술에 따른 반도체 소자의 제조 방법을 도시한 평면도. 1 is a plan view showing a method for manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2h는 본 발명의 제 1 실시예에 따른 반도체 소자의 제조 방법을 도시한 단면도.2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

도 3a 내지 도 3d는 본 발명의 제 2 실시예에 따른 반도체 소자의 제조 방법을 도시한 단면도.3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

도 4는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 평면도. 4 is a plan view showing a method of manufacturing a semiconductor device according to the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 비트라인 콘택영역과 저장전극 콘택영역의 랜딩 플러그를 서로 다른 높이와 서로 다른 면적을 가지도록 형성하되, 상대적으로 취약했던 저장전극 콘택영역의 랜딩플러그의 높이를 더 높이고 평면의 면적을 더 넓게 형성하여 후속 공정 진행시 접촉 면적 및 오버레이 특성을 향상시키는 기술을 개시한다.The present invention relates to a method of manufacturing a semiconductor device, wherein the landing plugs of the bit line contact region and the storage electrode contact region are formed to have different heights and different areas, and the landing plugs of the storage electrode contact regions, which are relatively fragile, are relatively weak. A technique is disclosed that increases the height and makes the area of the plane wider to improve the contact area and overlay properties during subsequent processing.

반도체 소자의 제조 공정이 고집적화되면서 미세해진 게이트와 게이트 사이에 랜딩플러그를 형성하는데 있어서, 상기 랜딩플러그 역시 미세하고 작아지게 된 다. As the manufacturing process of the semiconductor device is highly integrated, in forming a landing plug between the gate and the gate, the landing plug becomes fine and small.

종래 기술에 따른 반도체 소자의 제조 방법은 게이트가 형성된 반도체 기판 상부에 층간절연막을 형성한 후 상기 층간 절연막 상부에 랜딩플러그 예정영역을 정의하는 감광막 패턴을 형성한다. In the method of manufacturing a semiconductor device according to the related art, an interlayer insulating film is formed on a semiconductor substrate on which a gate is formed, and then a photosensitive film pattern defining a landing plug predetermined region is formed on the interlayer insulating film.

다음에, 상기 감광막 패턴을 마스크로 상기 층간절연막을 식각하여 반도체 기판이 노출되는 랜딩 플러그 영역을 형성하고, 상기 감광막 패턴을 제거한다. Next, the interlayer insulating layer is etched using the photoresist pattern as a mask to form a landing plug region through which a semiconductor substrate is exposed, and the photoresist pattern is removed.

그 다음에, 상기 랜딩 플러그 영역을 매립하는 폴리실리콘층을 반도체 기판 전면에 형성한 후 게이트가 노출될때까지 평탄화하여 랜딩 플러그를 형성한다. Next, a polysilicon layer filling the landing plug region is formed on the entire surface of the semiconductor substrate, and then planarized to form a landing plug until the gate is exposed.

도 1은 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 평면도로서, 게이트(3) 사이에 'A'의 면적을 가지는 랜딩플러그가 형성되는 것을 알 수 있다. 1 is a plan view illustrating a method of manufacturing a semiconductor device according to the related art, and it can be seen that a landing plug having an area of 'A' is formed between gates 3.

상술한 종래 기술에 따른 반도체 소자의 제조 방법에서, 랜딩 플러그가 작아지면서 비트라인 콘택 및 저장전극 콘택과의 연결에서 SAC 페일이 발생하고, 접촉면적이 줄어들어 저항이 증가되면서 소자의 특성과 신뢰성이 악화되는 문제점이 있다. In the above-described method of manufacturing a semiconductor device, as the landing plug becomes smaller, SAC fail occurs in the connection between the bit line contact and the storage electrode contact, and the contact area decreases to increase the resistance, thereby deteriorating the characteristics and reliability of the device. There is a problem.

또한, 랜딩 플러그의 상부 면적이 작게 형성되면서 후속 공정시 오버레이 마진이 취약해지는 문제점이 있다. In addition, as the upper area of the landing plug is formed small, there is a problem in that the overlay margin becomes weak in a subsequent process.

상기 문제점을 해결하기 위하여, 비트라인 콘택영역과 저장전극 콘택영역의 랜딩 플러그를 서로 다른 높이와 서로 다른 면적을 가지도록 형성하되, 상대적으로 취약했던 저장전극 콘택영역의 랜딩플러그의 높이를 더 높이고 평면의 면적을 더 넓게 형성하여 후속 공정 진행시 접촉 면적 및 오버레이 특성을 향상시키는 반도체 소자의 제조 방법을 제공하는 것을 목적으로 한다. In order to solve the above problems, the landing plugs of the bit line contact region and the storage electrode contact region are formed to have different heights and different areas, and the height of the landing plug of the storage electrode contact region, which is relatively weak, is increased and the plane is flat. It is an object of the present invention to provide a method for manufacturing a semiconductor device, in which the area of the film is formed to be wider, thereby improving the contact area and the overlay characteristics during the subsequent process.

본 발명에 따른 반도체 소자의 제조 방법은 Method for manufacturing a semiconductor device according to the present invention

(a) 게이트가 구비된 반도체 기판 전면에 층간절연막을 형성하는 단계와,(a) forming an interlayer insulating film on the entire surface of the semiconductor substrate provided with a gate;

(b) 상기 제 1 랜딩플러그 콘택 마스크를 사용하여 랜딩플러그 영역의 층간절연막을 식각하는 단계와,(b) etching the interlayer dielectric layer of the landing plug region using the first landing plug contact mask;

(c) 상기 랜딩 플러그 영역을 매립하는 제 1 폴리실리콘층을 형성하는 단계와,(c) forming a first polysilicon layer filling the landing plug region;

(d) 상기 제 2 랜딩플러그 콘택 마스크를 사용하여 비트라인 콘택영역의 제 1 폴리실리콘층을 식각하여 랜딩플러그를 형성하되, 저장전극 콘택영역의 랜딩플러그가 비트라인 콘택영역의 랜딩플러그보다 높게 형성되는 단계(d) forming a landing plug by etching the first polysilicon layer of the bit line contact region using the second landing plug contact mask, wherein the landing plug of the storage electrode contact region is formed higher than the landing plug of the bit line contact region. Steps

를 포함하는 것을 특징으로 하며, Characterized in that it comprises a,

상기 층간절연막은 산화막으로 형성하는 것과,The interlayer insulating film is formed of an oxide film,

상기 제 1 랜딩플러그 콘택 마스크는 랜딩플러그 영역을 노출시키는 것과,The first landing plug contact mask may be configured to expose the landing plug area.

상기 (b) 단계 후 층간절연막을 평탄화하는 단계를 더 포함하는 것과,After the step (b), further comprising planarizing the interlayer insulating film;

상기 제 2 랜딩플러그 콘택 마스크는 비트라인 콘택영역을 노출시키는 것과, The second landing plug contact mask may expose the bit line contact area,

상기 (c) 단계 후 상기 제 1 폴리실리콘층을 평탄화 식각하여 상기 게이트를 노출시키는 단계와 상기 제 1 폴리실리콘층 상부에 제 2 폴리실리콘층을 형성하는 단계와, Exposing the gate by planarizing etching the first polysilicon layer after the step (c), and forming a second polysilicon layer on the first polysilicon layer;

상기 (d) 단계는 게이트 상부가 노출되도록 실시하는 것을 특징으로 한다. Step (d) is characterized in that the upper portion of the gate is exposed.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 2a 내지 도 2h는 본 발명의 제 1 실시예에 따른 반도체 소자의 제조 방법을 도시한 단면도이다.2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

도 2a 및 도 2b를 참조하면, 게이트(43)가 형성된 반도체 기판(10) 전면에 산화막으로 층간절연막(40)을 형성한다. 2A and 2B, an interlayer insulating film 40 is formed on the entire surface of the semiconductor substrate 10 on which the gate 43 is formed by an oxide film.

도 2c를 참조하면, 층간절연막(40) 상부에 랜딩플러그 예정영역(55)을 정의하는 제 1 감광막 패턴(50)을 형성한다. Referring to FIG. 2C, a first photoresist layer pattern 50 defining a landing plug predetermined region 55 is formed on the interlayer insulating layer 40.

도 2d를 참조하면, 제 1 감광막 패턴(50)을 마스크로 층간절연막(40)을 식각하여 게이트(43)와 게이트(43) 사이의 트랜지스터 접합 영역(13)을 노출시킨 후 제 1 감광막 패턴(50)을 제거한다. Referring to FIG. 2D, the interlayer insulating layer 40 is etched using the first photoresist pattern 50 as a mask to expose the transistor junction region 13 between the gate 43 and the gate 43, and then the first photoresist pattern ( 50) Remove.

다음에, 남겨진 층간절연막(40)을 평탄화 식각하여 게이트(43)를 노출시킨다. Next, the remaining interlayer insulating film 40 is planarized and etched to expose the gate 43.

도 2e를 참조하면, 반도체 기판(10) 전면에 랜딩플러그 예정영역(55)을 매립하는 제 1 폴리실리콘층(60)을 형성한다. Referring to FIG. 2E, a first polysilicon layer 60 filling the landing plug predetermined region 55 is formed on the entire surface of the semiconductor substrate 10.

도 2f를 참조하면, 저장전극 콘택영역(11) 상측에 제 2 감광막 패턴(65)을 형성한다. Referring to FIG. 2F, a second photoresist layer pattern 65 is formed on the storage electrode contact region 11.

도 2g를 참조하면, 제 2 감광막 패턴(65)을 마스크로 제 1 폴리실리콘층(60)을 식각한다.Referring to FIG. 2G, the first polysilicon layer 60 is etched using the second photoresist pattern 65 as a mask.

이때, 게이트(43) 상부도 일부 식각되어 노출되도록 하는 것이 바람직하다. At this time, the upper portion of the gate 43 is also preferably etched to be exposed.

도 2h를 참조하면, 제 2 감광막 패턴(65)을 제거하여 랜딩플러그(100, 110)를 형성한다. Referring to FIG. 2H, the landing plugs 100 and 110 are formed by removing the second photoresist pattern 65.

여기서, 저장전극 콘택영역(11)의 랜딩플러그(110)가 비트라인 콘택영역(12)의 랜딩플러그(100)보다 높게 형성되는 것이 바람직하다.Here, the landing plug 110 of the storage electrode contact region 11 is preferably formed higher than the landing plug 100 of the bit line contact region 12.

도 3a 내지 도 3d는 본 발명의 제 2 실시예에 따른 반도체 소자의 제조 방법을 도시한 단면도이다. 3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

본 발명에 따른 제 2 실시예는 상기 도 2a 내지 도 2e에 도시된 공정을 수행한 후 후속 공정을 진행하도록 한다.The second embodiment according to the present invention allows the subsequent process to proceed after performing the process shown in FIGS.

도 3a를 참조하면, 전면식각 또는 CMP 공정을 수행하여 제 1 폴리실리콘층(60)을 평탄화시킨다. Referring to FIG. 3A, the first polysilicon layer 60 is planarized by performing an entire surface etching or CMP process.

이때, 상기 평탄화 공정은 제 1 폴리실리콘층(60)은 게이트 하드마스크층(30)이 노출될때까지 진행한다. In this case, the planarization process is performed until the first polysilicon layer 60 is exposed to the gate hard mask layer 30.

도 3b를 참조하면, 반도체 기판(10) 전면에 제 2 폴리실리콘층(70)을 형성한다. Referring to FIG. 3B, a second polysilicon layer 70 is formed on the entire surface of the semiconductor substrate 10.

도 3c를 참조하면, 저장전극 콘택영역(11) 상측에 제 2 감광막 패턴(65)을 형성한다. Referring to FIG. 3C, a second photoresist layer pattern 65 is formed on the storage electrode contact region 11.

도 3d를 참조하면, 제 2 감광막 패턴(65)을 마스크로 제 1 폴리실리콘층(60)을 식각한다. Referring to FIG. 3D, the first polysilicon layer 60 is etched using the second photoresist pattern 65 as a mask.

이때, 게이트(43) 상부도 일부 식각되어 노출되도록 하는 것이 바람직하다. At this time, the upper portion of the gate 43 is also preferably etched to be exposed.

다음에, 제 2 감광막 패턴(65)을 제거하여 랜딩플러그(100, 110)를 형성한다. Next, the second photosensitive film pattern 65 is removed to form the landing plugs 100 and 110.

여기서, 저장전극 콘택영역의 랜딩플러그(110)가 비트라인 콘택영역의 랜딩플러그(100)보다 높게 형성되는 것이 바람직하다.Here, the landing plug 110 of the storage electrode contact region may be formed higher than the landing plug 100 of the bit line contact region.

도 4는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 평면도이다. 4 is a plan view illustrating a method of manufacturing a semiconductor device according to the present invention.

도 4를 참조하면, 게이트(43) 사이에 'B'의 면적을 가지는 랜딩플러그가 형성되되, 상기 도 1과 비교해 볼 때 랜딩플러그가 X축으로 확장되면서 상기 랜딩 플러그의 접촉 면적이 넓어진 것을 알 수 있다. Referring to FIG. 4, a landing plug having an area of 'B' is formed between the gates 43, and as compared with FIG. 1, the landing plug is extended along the X axis and the contact area of the landing plug is widened. Can be.

본 발명에 따른 반도체 소자의 제조 방법은 비트라인 콘택영역과 저장전극 콘택영역의 랜딩 플러그를 서로 다른 높이와 서로 다른 면적을 가지도록 형성하되, 상대적으로 취약했던 저장전극 콘택영역의 랜딩플러그의 높이를 더 높이고 평면의 면적을 더 넓게 형성하여 후속 공정 진행시 접촉 면적 및 오버레이 특성을 향상시키는 효과가 있다.In the method of manufacturing a semiconductor device according to the present invention, the landing plugs of the bit line contact region and the storage electrode contact region are formed to have different heights and different areas, and the landing plugs of the storage electrode contact regions, which are relatively weak, The higher the height and the larger the area of the plane, there is an effect of improving the contact area and overlay properties in the subsequent process.

또한, 반도체 소자가 고집적화 될수록 취약해지는 소자의 특성과 신뢰성을 향상시킬 수 있으며, 공정이 안정화되어 제품의 제조수율이 향상시키는 효과가 있다. In addition, the higher the integration of the semiconductor device can improve the characteristics and reliability of the weaker device, the process is stabilized has the effect of improving the production yield of the product.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으 로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as being in scope.

Claims (7)

(a) 게이트가 구비된 반도체 기판 전면에 층간절연막을 형성하는 단계;(a) forming an interlayer insulating film on the entire surface of the semiconductor substrate provided with the gate; (b) 상기 제 1 랜딩플러그 콘택 마스크를 사용하여 랜딩플러그 영역의 층간절연막을 식각하는 단계;(b) etching the interlayer dielectric layer of the landing plug region using the first landing plug contact mask; (c) 상기 랜딩 플러그 영역을 매립하는 제 1 폴리실리콘층을 전체 표면 상부에 형성하는 단계; 및(c) forming a first polysilicon layer filling the landing plug region over the entire surface; And (d) 상기 제 2 랜딩플러그 콘택 마스크를 사용하여 비트라인 콘택영역의 제 1 폴리실리콘층을 소정 깊이 식각하여 랜딩플러그를 형성하되, 저장전극 콘택영역의 랜딩플러그가 비트라인 콘택영역의 랜딩플러그보다 높게 형성되는 단계;(d) etching the first polysilicon layer of the bit line contact region using the second landing plug contact mask to form a landing plug, wherein the landing plug of the storage electrode contact region is larger than the landing plug of the bit line contact region. Highly formed; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법. Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 층간절연막은 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. And the interlayer insulating film is formed of an oxide film. 제 1 항에 있어서,The method of claim 1, 상기 제 1 랜딩플러그 콘택 마스크는 랜딩플러그 영역을 노출시키는 것을 특징으로 하는 반도체 소자의 제조 방법. And the first landing plug contact mask exposes a landing plug region. 제 1 항에 있어서,The method of claim 1, 상기 (b) 단계 후 층간절연막을 평탄화하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법. And (b) planarizing the interlayer insulating film after the step of fabricating the semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 제 2 랜딩플러그 콘택 마스크는 비트라인 콘택영역을 노출시키는 것을 특징으로 하는 반도체 소자의 제조 방법. The second landing plug contact mask exposes a bit line contact region. 제 1 항에 있어서, The method of claim 1, 상기 (c) 단계 후 After step (c) 상기 제 1 폴리실리콘층을 평탄화 식각하여 상기 게이트를 노출시키는 단계; 및Planarizing etching the first polysilicon layer to expose the gate; And 상기 제 1 폴리실리콘층 상부에 제 2 폴리실리콘층을 형성하는 단계; Forming a second polysilicon layer on the first polysilicon layer; 를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법. Method of manufacturing a semiconductor device further comprising. 제 1 항에 있어서, The method of claim 1, 상기 (d) 단계는 게이트 상부가 노출되도록 실시하는 것을 특징으로 하는 반도체 소자의 제조 방법. Step (d) is a method of manufacturing a semiconductor device, characterized in that to perform the upper portion of the gate exposed.
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