KR20070077976A - Display apparatus - Google Patents

Abstract

A display device is provided to equip the first gate line to a display area, thereby preventing the width of a peripheral area from increasing due to the first gate line. A display panel comprises an array panel(100) and an opposite substrate oppositely combined with the array substrate and displays an image in response to a gate signal and a data signal. A driving member(400) is equipped on the array substrate and offers the gate signal and the data signal to the display panel. The array substrate includes a base substrate having a display area for displaying an image and a peripheral area adjacent to the display area. The first gate line is equipped to the display area of the base substrate, connected with the driving member and receives the gate signal. The second gate line is extended to the direction vertically crossing to the gate line at the display area and electrically connected with the first gate line. A data line is extended in parallel to the first gate line at the display area and receives the data signal from the driving member. A pixel(101) is electrically connected with the second gate line and the data line at the display area.

Description

Display device {DISPLAY APPARATUS}

1 is a plan view of an array substrate according to an embodiment of the present invention.

FIG. 2 is a layout of a portion A shown in FIG. 1.

3 is a cross-sectional view taken along the line II ′ and the line II-II ′ of FIG. 2.

4 is a plan view of a liquid crystal display device having the array substrate shown in FIG. 1.

FIG. 5 is a cross-sectional view taken along the line III-III ′ of FIG. 4.

* Description of the symbols for the main parts of the drawings *

100: array substrate 110: first base substrate

120: interlayer insulating film 130: gate insulating film

140: protective film 150: organic film

160: pixel electrode 200: color filter substrate

210: second base substrate 221, 222: first and second black matrices

230: color filter layer 240: overcoating layer

300: common electrode 300: liquid crystal display panel

310: liquid crystal layer 350: sealant

400: driving chip 500: liquid crystal display

The present invention relates to a display device, and more particularly, to a display device capable of expanding a display area.

In general, a liquid crystal display device includes a liquid crystal display panel for displaying an image. The liquid crystal display panel includes a display area for displaying an image and a peripheral area adjacent to the display area. The display area includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. Each pixel consists of a thin film transistor and a liquid crystal capacitor. The peripheral region includes a gate driver for outputting a gate signal to gate lines and a data driver for outputting a data signal to data lines.

In a conventional liquid crystal display device, the gate driver is formed in the peripheral area of the liquid crystal display panel at the same time through the same thin film process as the thin film transistor, or embedded together with the data driver in one driving chip mounted in the peripheral area.

However, in the structure in which the gate driver is directly formed in the peripheral area of the liquid crystal display panel, the width of the peripheral area is increased by the gate driver, and in the structure in which the gate driver is embedded in the driving chip, an auxiliary device for connecting the gate driver and the gate line is provided. The gate line is further provided in the peripheral region. Therefore, in the conventional liquid crystal display device, the width of the peripheral area is increased by the gate driver or the auxiliary gate line, and as a result, the ratio of the display area to the liquid crystal display panel is reduced.

Accordingly, an object of the present invention is to provide a display device for increasing the ratio of the display area in the display panel.

The display device according to the present invention includes a display panel and a driver. The display panel includes an array substrate and an opposite substrate coupled to the array substrate to display an image in response to a gate signal and a data signal. The driver is provided on the array substrate to provide the gate signal and the data signal to the display panel.

The array substrate includes a base substrate, first and second gate lines, data lines, and pixels. The base substrate includes a display area for displaying an image and a peripheral area adjacent to the display area. The first gate line is provided in the display area of the base substrate and is electrically connected to the driver to receive the gate signal. The second gate line extends in a direction orthogonal to the first gate line in the display area of the base substrate and is electrically connected to the first gate line. The data line extends in parallel with the first gate line to receive the data signal. The pixel is electrically connected to the second gate line and the data line.

According to such a display device, a first gate line for electrically connecting a second gate line formed in a display area to a driver is formed in the display area, thereby preventing the width of the peripheral area from being increased by the first gate line. As a result, the ratio of the display area to the size of the same display panel can be increased.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of an array substrate according to an embodiment of the present invention.

Referring to FIG. 1, the array substrate 100 includes a display area DA displaying an image and a first base substrate 110 including a peripheral area PA adjacent to the display area DA.

The display area DA of the first base substrate 110 is orthogonal to the plurality of first gate lines GL1-1 to GL1-n and the first direction D1 extending in the first direction D1. A plurality of second gate lines GL2-1 to GL2-n extending in the second direction D2 are provided. In addition, the display area DA of the first base substrate 110 includes a plurality of data lines DL1 to DLm extending in the first direction D1.

The plurality of first gate lines GL1-1 to GL1-n have the same number as the plurality of second gate lines GL2-1 to GL2-n, and are electrically connected to the corresponding second gate lines. And the second gate lines are electrically insulated from each other. For example, three data lines may be provided between the first gate lines adjacent to each other.

The driver 400 is mounted in a chip form in the peripheral area PA of the first base substrate 110. The driver 400 includes a gate driver circuit 410 for outputting a gate signal and a data driver circuit 420 for outputting a data signal.

The gate driving circuit 410 is directly connected to the plurality of first gate lines GL1-1 to GL1-n to provide the gate signal. The plurality of second gate lines GL2-1 to GL2-n are electrically connected to the gate driving circuit 410 through corresponding first gate lines to receive the gate signals.

The plurality of data lines DL1 to DLm are directly connected to the data driving circuit 420 to receive the data signal.

A plurality of pixel regions are formed by the plurality of data lines DL1 to DLm and the plurality of second gate lines GL2-1 to GL2-n, and the pixel 101 is provided in each pixel region. The pixel 101 includes a thin film transistor Tr and a pixel electrode 160. A gate electrode of the thin film transistor Tr is electrically connected to a corresponding second gate line, a source electrode is electrically connected to a corresponding data line, and a drain electrode is electrically connected to the pixel electrode 160. Accordingly, the thin film transistor Tr provides the data signal to the pixel electrode 160 in response to the gate signal.

FIG. 2 is a layout of a portion A shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along the cutting line I-I ′ and the cutting line II-II ′ shown in FIG. 2.

2 and 3, a plurality of second gate lines GL2-1 and GL2-2 and gate electrodes made of a gate metal are formed on the first base substrate. Thereafter, the interlayer insulating layer 120 is formed in a region where the first gate lines that do not correspond to the plurality of second gate lines GL2-1 and GL2-2 cross each other. A plurality of first gate lines GL1-1 formed of a gate metal is formed on the first base substrate 110. Here, the plurality of first gate lines GL1-1 are electrically connected to the corresponding second gate lines GL2-1, while the first gate lines GL2-2 are not interposed with the first gate line GL2-2. It is electrically insulated by an insulating film.

Next, a gate insulating layer 130 is formed on the first base substrate 110 as a whole so that the plurality of first gate lines GL1-1, the plurality of second gate lines GL2-1 and GL2-2, and the gates are formed. Cover the electrode GE. A plurality of data lines DL1, DL2, DL3, source electrode SE, and drain electrode DE are formed on the gate insulating layer 130.

Subsequently, a passivation layer 140 is formed on the gate insulating layer 130 to protect the data lines DL1, DL2, DL3, the source electrode SE, and the drain electrode DE. An organic insulating layer 150 is further formed on the passivation layer 140. A contact hole 151 for exposing the drain electrode DE is formed in the passivation layer 140 and the organic insulating layer 150.

The pixel electrode 160 is formed on the organic insulating layer 150, and the pixel electrode 160 is electrically connected to the drain electrode DE through the contact hole 151.

2 and 3 illustrate a structure in which the plurality of first gate lines GL1-1 to GL1-n are made of a gate metal. However, the plurality of first gate lines GL1-1 to GL1-n may be made of data metal and simultaneously patterned with the plurality of data lines DL1 to DLm. As described above, when the plurality of first gate lines GL1-1 to GL1-n are made of data metal, the gate insulating layer 130 may be connected to the plurality of first gate lines GL1-1 to GL1-n. Contact holes (not shown) are formed to expose corresponding second gate lines. Accordingly, the plurality of first gate lines GL1-1 to GL1-n may be electrically connected to the corresponding second gate lines. In this case, the plurality of first gate lines GL1-1 to GL1-n may be spaced at predetermined intervals so as to be electrically insulated from adjacent data lines.

FIG. 4 is a plan view of the liquid crystal display device having the array substrate illustrated in FIG. 1, and FIG. 5 is a cross-sectional view taken along the cutting line III-III ′ of FIG. 4. However, the same reference numerals are given to the same components as those shown in FIGS. 1 to 3 among the components illustrated in FIGS. 4 and 5, and detailed description thereof will be omitted.

4 and 5, the liquid crystal display device 500 includes a liquid crystal display panel 300 for displaying an image and a driver 400 for driving the liquid crystal display panel 300.

The liquid crystal display panel 300 includes an array substrate 100, a color filter substrate 200 that is coupled to face the array substrate 100, and between the array substrate 100 and the color filter substrate 200. It is made of an interposed liquid crystal layer 310.

The color filter substrate 200 includes a second base substrate 210, first and second black matrices 221 and 222, a color filter layer 230, an overcoating layer 240, and a common electrode 250. The first black matrix 221 is formed in the display area DA of the second base substrate 210, and the second black matrix 222 is a peripheral area PA of the second base substrate 210. It is formed within.

The color filter layer 230 includes red, green, and blue color pixels R G and B, and the first black matrix 221 is interposed between the color pixels R G and B. Here, a step occurs between the color pixels R, G, and B and the first black matrix 221. The overcoat layer 240 is formed on the color filter layer 230 and the first and second black matrices 221 and 222 to reduce the step difference. Therefore, the surface of the color filter substrate 200 is planarized by the overcoating layer 240. Thereafter, the common electrode 250 is formed on the overcoat layer 240. The common electrode 250 faces the pixel electrode 160 formed on the array substrate 100 with the liquid crystal layer 310 interposed therebetween.

The liquid crystal display panel 300 further includes a sealant 350 for coupling the color filter substrate 200 to the array substrate 100. The sealant 350 is interposed between the color filter substrate 200 and the array substrate 100 in the peripheral area PA. In this case, the second black matrix 222 may be formed to correspond to a region where the sealant 350 is formed to prevent light leakage in the peripheral area PA.

According to such a display device, since a plurality of first gate lines for electrically connecting the plurality of second gate lines and the driving unit are provided in the display area of the array substrate, the width of the peripheral area adjacent to the display area is reduced.

Therefore, since the display area can be extended by the width of the reduced peripheral area in the display panel of the same size as in the related art, the ratio of the display area in the display panel can be increased.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (5)

A display panel including an array substrate and an opposite substrate coupled to the array substrate to display an image in response to a gate signal and a data signal; And A driver provided on the array substrate to provide the gate signal and the data signal to the display panel; The array substrate, A base substrate comprising a display area for displaying an image and a peripheral area adjacent to the display area; A first gate line provided in the display area of the base substrate and electrically connected to the driver to receive the gate signal; A second gate line extending in a direction orthogonal to the first gate line in the display area of the base substrate and electrically connected to the first gate line; A data line extending in parallel with the first gate line in the display area of the base substrate and receiving the data signal from the driver; And And a pixel electrically connected to the second gate line and the data line in the display area. The method of claim 1, wherein the first and second gate lines are provided in plurality. And the plurality of first gate lines are electrically insulated from the remaining second gate lines except for a corresponding second gate line. The interlayer of claim 2, wherein the array substrate is interposed between the plurality of first gate lines and the remaining second gate lines in a region where the plurality of first gate lines and the remaining second gate lines cross each other. A display device further comprising an insulating film. The display device of claim 1, wherein the driving part is formed in a chip shape and mounted on a peripheral area of the base substrate. The display device of claim 4, wherein the driving unit includes a data driving circuit for outputting the data signal and a gate driving circuit for outputting the gate signal.

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