KR102297897B1 - Substrate with multi layer pad, display panel comprising the substrate, and method of fabricating thereof - Google Patents

Abstract

The present invention relates to a substrate including a multi-layered pad part, a display panel including the substrate, and a method of manufacturing the same. Silver includes a pad portion composed of any one of a quadruple layer or a triple layer.

Description

A substrate including a multi-layered pad part, a display panel including the substrate, and a method of manufacturing the same

The present invention relates to a display panel including a multi-layered pad part and a method for manufacturing the same.

A display device (display device) is a device for visually displaying data, and includes a liquid crystal display (LCD), electrophoresis; Electrophoretic Display, Organic Light Emitting Display, Inorganic EL Display, (Electro Luminescent Display), Field Emission Display, Surface-conduction Electron -emitter display), plasma display, and cathode ray tube display (Cathode Ray, Display).

In the display panel, thin film transistors are formed in each pixel region, and a specific pixel region in the display panel is controlled by using an electrical signal such as a current or voltage applied to the thin film transistor. A thin film transistor consists of a gate, source-drain electrodes, and an active layer. In addition, in order to provide a predetermined electrical signal to various lines connected to the pixels of the display panel, it is necessary to provide a pad on the display panel.

A process of forming a thin film transistor and a pad plays an important role in order to output a high-resolution image as the display panel becomes larger, and the process includes deposition and etching processes to form the components of the thin film transistor. In this process, a process of depositing and etching a pad, a gate, an active layer, and a source-drain portion is required, and it is necessary to reduce the number of depositions or etchings in each process.

The present invention provides a substrate, a display panel, and their process for forming a source-drain and a pad unit in the same process.

The present invention proposes a method for forming a source-drain and a pad portion in the same process to increase process efficiency and reduce the process cost by reducing the number of masks.

The present invention relates to a substrate, a display panel, and a substrate capable of protecting the conductive material constituting the source-drain and the pad part by configuring the source-drain and the pad part of the display panel as a quadruple layer, but the uppermost layer includes the poly(ITO) layer. present the process.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned may be understood by the following description, and will be more clearly understood by the examples of the present invention. Moreover, it will be readily apparent that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

In the display panel or substrate according to an embodiment of the present invention, the first region of the pad part includes a quadruple layer, and the second region includes a pad part composed of either a quadruple layer or a triple layer.

A display panel or a substrate according to another embodiment of the present invention is produced in the same process as the pad part and the source or drain of the thin film transistor.

The pad part of the display panel or substrate according to another embodiment of the present invention includes a first layer including MoTi, a second layer including Cu on the first layer, and a third layer including MoTi on the second layer. and optionally a fourth layer comprising polyized ITO on the third layer.

In the pad portion of the display panel or substrate according to another embodiment of the present invention, the height of the layer including the polyized ITO in the passivation area is the height of the layer including the polyized ITO in the area where the passivation is not disposed. bigger than

A method of manufacturing a display panel or a substrate according to an embodiment of the present invention includes disposing a source, a drain, and a pad portion in a quadruple layer on a substrate, and a passivation layer and an overcoat layer on the disposed source, drain, and pad portion. and disposing using one mask.

When the present invention is applied, since the pad part can be formed in the same process in the process of forming the source and the drain, the number of masks can be reduced and the efficiency of the process can be increased while protecting the pad part.

In addition, since the number of masks is reduced when the present invention is applied, it is possible to reduce a process error occurring in the mask alignment process.

In addition, when the present invention is applied, polyized ITO is disposed on the pad part disposed in the non-display area to sufficiently protect the conductive materials constituting the pad part during various processes of arranging the pixel electrode and the bank in the display area. make it possible

In addition, when the present invention is applied, the polyized ITO may be disposed on the upper portion of the pad portion to protect various conductive materials disposed thereunder during the process.

In addition, when the present invention is applied, since conductive materials can be repeatedly disposed on the pad portion, the source and the drain, etc., the electrical properties of the electrical components of the display panel can be improved.

The effects of the present invention are not limited to the above-described effects, and those skilled in the art can easily derive various effects of the present invention from the configuration of the present invention.

1 is a diagram schematically illustrating a display device according to an embodiment of the present invention.
2 is a view showing a display device on which a pad part is displayed to which an embodiment of the present invention is applied.
FIG. 3 is a view showing a configuration in which a pad part and source-drain electrodes are disposed in the display panel 11 of FIG. 2 .
FIG. 4 is another diagram illustrating a configuration in which a pad part and source-drain electrodes are disposed in the display panel 11 of FIG. 2 .
5 is a view showing the configuration of a pad part and a source-drain electrode having a quadruple layer structure according to an embodiment of the present invention.
6 to 13 are views illustrating a process of forming a pad part and a source-drain electrode having the same structure as in FIG. 5 .
14 is an enlarged view showing the configuration of the quadruple layer of the pad part according to an embodiment of the present invention.
15 is a view showing a configuration in which the height of the pad portion ITO according to an embodiment of the present invention is not uniform.
16 is a view showing a configuration in which the ITO of the pad part according to an embodiment of the present invention is removed from the hole.
17 is a view showing a configuration applied to the source-drain electrode 150 according to an embodiment of the present invention.
19 is a view showing the configuration of a pad part according to another embodiment of the present invention.
20 is a diagram illustrating a process of manufacturing a display panel according to an embodiment of the present invention.

Hereinafter, with reference to the drawings, embodiments of the present invention will be described in detail so that those of ordinary skill in the art to which the present invention pertains can easily implement them. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

In order to clearly explain the present invention, parts irrelevant to the description are omitted, and the same reference numerals are given to the same or similar elements throughout the specification. Further, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In the following, the provision or arrangement of an arbitrary component on the “upper (or lower)” or “top (or below)” of the substrate means that any component is provided or disposed in contact with the upper surface (or lower surface) of the substrate. It is not intended to mean, but is not limited to, the inclusion of other components between the substrate and any component provided or disposed on (or under) the substrate. In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It will be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

The display device outputs image data provided from the outside using various light sources. In this process, image data is divided into R (red), G (green), and B (blue) and provided to the display device, and may optionally include W (white) or Black (black).

1 is a diagram schematically illustrating a display device according to an embodiment of the present invention. The present invention can be applied to various display devices such as an organic light emitting display device and a liquid crystal display device.

Referring to FIG. 1 , in the display device 10 according to the embodiments, a plurality of first lines VL1 to VLm are formed in a first direction (eg, a vertical direction), and a second direction (eg, a horizontal direction) is formed. ), a display panel 11 having a plurality of second lines HL1 to HLn formed therein, a first driver 12 supplying a first signal to a plurality of first lines VL1 to VLm, and a plurality of first lines. It includes a second driving unit 13 for supplying a second signal to the two lines HL1 to HLn, and a timing controller 14 for controlling the first driving unit 12 and the second driving unit 13 .

The display panel 11 includes a plurality of first lines VL1 to VLm formed in a first direction (eg, a vertical direction) and a plurality of second lines HL1 to HLn formed in a second direction (eg, a horizontal direction). A plurality of pixels (P: Pixel) are defined according to the intersection of

Each of the first and second drivers 12 and 13 described above may include at least one driver IC that outputs a signal for displaying an image. The first driver 12 includes one or more data drivers or source driver ICs (Integrated Circuits). The second driving unit 13 includes one or more gate drivers.

The plurality of first lines VL1 to VLm formed in the first direction on the display panel 11, for example, are formed in a vertical direction (first direction) to transmit data voltages (first signals) to pixel columns in the vertical direction. data line, and the first driver 12 may be a data driver supplying a data voltage to the data line.

In addition, the plurality of second lines HL1 to HLn formed in the second direction on the display panel 11 are formed in the horizontal direction (the second direction) to transmit the scan signal (first signal) to the pixel column in the horizontal direction. line, and the second driver 13 may be a gate driver supplying a scan signal to the gate line.

In addition, a pad part is configured in the display panel 11 to be connected to the first driving part 12 and the second driving part 13 . When a first signal is supplied from the first driving unit 12 to the plurality of first lines VL1 to VLm, the pad unit transmits it to the display panel 11 , and similarly, the second driving unit 13 provides a plurality of second lines ( When the second signal is supplied to HL1 to HLn), it is transmitted to the display panel 11 .

Each pixel may include one or more subpixels, or each pixel may indicate each of these subpixels. The sub-pixel refers to a unit in which a specific color filter is formed or a color filter is not formed and the organic light emitting device can emit a special color. The colors defined in the sub-pixel may include red (R), green (G), blue (B), and optionally white (W), but the present invention is not limited thereto. Since each sub-pixel includes a separate thin film transistor and an electrode connected thereto, the sub-pixel constituting the pixel is also referred to as one pixel area hereinafter. In addition, an electrode that controls light emission of each pixel area is designated as a pixel electrode.

An electrode connected to the thin film transistor for controlling light emission of each pixel area of the display panel is referred to as a first electrode, and an electrode disposed on the entire surface of the display panel or disposed to include two or more pixel areas is referred to as a second electrode. When the first electrode is an anode electrode, the second electrode becomes a cathode electrode, and vice versa. Hereinafter, an anode electrode as an embodiment of the first electrode and a cathode electrode as an embodiment of the second electrode will be mainly described, but the present invention is not limited thereto.

As described above, the display panel constituting the display device selectively emits the above-described R/G/B and W colors to output an image. For this purpose, thin film transistors are disposed in pixel areas corresponding to each color. When the thin film transistor is manufactured to include an oxide semiconductor, a process of depositing a gate, an active layer, and a source-drain, respectively, and etching each is required. In this process, there is a problem in that the chamber for deposition needs to be changed. In addition, there is a problem that each etching must be performed.

In addition, in order to arrange the pad part in the edge region of the display panel, the pad part may be disposed together during the process of forming the thin film transistor. However, unlike the pixel region, the pad part can be coupled to the drivers 12 and 13 without a protective layer thereon. In this process, the pad part is exposed to the outside for a long time compared to the source or drain of the thin film transistor or is etched. There is a problem of being exposed to the process as it is.

Therefore, in the present specification, a configuration capable of protecting the pad part even in the absence of a protective layer in the process of forming the pad part and the thin film transistor together and a manufacturing process related thereto will be described.

2 is a view showing a display device on which a pad part is displayed to which an embodiment of the present invention is applied.

As shown in FIG. 2 , the display panel 11 of the display device 10 of FIG. 1 is divided into a display area 20 and a non-display area 21 outside the display area, and the non-display area 21 includes a plurality of pads. It includes pad areas 22, 23, 24 in which parts are disposed. The pad areas 22, 23, and 24 connect the gate and source to the display panel with driver ICs at the upper and lower, left and right ends of the display area 20, and the pad areas 22, 23 and 24), a plurality of pad parts to which the aforementioned IC can be connected are implemented.

Reference numeral 25 includes a plurality of pad units. In FIG. 2 , the pad unit 25 is a data pad unit and is connected to a data line. The pad portions of the pad regions 22 and 24 on the left and right sides of the display panel 11 are gate pad portions and are connected to the gate line.

According to an embodiment of the present invention, the data pad unit, the data line, and the source-drain electrode may be formed using the same material in the same process. Also, according to another embodiment of the present invention, the gate pad part may be formed using the same material in the same process as the gate line and the gate.

The display panel 11 of the display device 10 of FIGS. 1 and 2 may be composed of two substrates, and among the two substrates, the first substrate (110 in the drawings to be described later) is a display in which the above-described two regions are displayed. It may be divided into an area 20 and a non-display area 21 .

Accordingly, a plurality of thin film transistors are disposed on the first substrate (110 in a drawing to be described later), and sources or drains of the thin film transistors may be respectively connected to data lines (VL1 to VLm in FIG. 1 ). In addition, the gates of the thin film transistors are also electrically connected to the gate lines (HL1 to HLn in FIG. 1), respectively. On the other hand, the source or drain is electrically connected to the pad parts to which the present invention is applied through the data line.

In another embodiment, pad parts generated in the same process as the above-described gate, to which the present invention is not applied, may also electrically connect the gate line and the above-described gate.

In the process of FIGS. 6 to 13, which will be described later, the pad part and the source or drain are simultaneously generated. In particular, the configuration of the pad part includes a region made of a quadruple conductive material and a triple or quadruple layer as shown in FIG. 15 or FIG. 16 . and a second region composed of

Also, according to another embodiment of the present invention, the gate line and the gate are formed in the same process, and the data pad part, the data line, and the source-drain electrode of the gate pad part may also be formed using the same material in the same process. . In this process, a hole for connecting the gate line and the gate pad part may be separately formed.

Hereinafter, the pad part described in this specification will be mainly described with respect to the data pad part, but the present invention is not limited thereto, and as described above, it may be applied to both the gate pad part and the data pad part.

In one embodiment, the pad part of the present specification may be disposed together with the thin film transistor on the substrate. When A-A' of FIG. 2 is enlarged, it is the same as FIG. 2 or FIG. 3 .

FIG. 3 is a view showing a configuration in which a pad part and source-drain electrodes are disposed in the display panel 11 of FIG. 2 .

Since the pad part provides a signal to the gate line or the data line, the same material as the source-drain electrode is disposed on the substrate 11a of the display panel for an efficient process. The pad portion 11b and the source-drain electrode 11c of FIG. 3 are generated in the same manner. However, after the pad part 11b is formed, the passivation layer 11d is disposed thereon and the pad part 11b must be opened so that the pad part 11b can be connected to the first driving part 12 . Of course, when the pad part 11b is a gate pad part, it needs to be opened so as to be connected to the second driving part 13 .

The opening timing of the pad part 11b may be variously selected. However, when the source-drain electrode 11c and the pad part 11b are simultaneously opened, chemical and physical damage may occur on the opened pad part 11b in various subsequent processes. For example, the open space of the source-drain electrode 11c is covered with the pixel electrode in the process of disposing the pixel electrode and disposing the light emitting material using the pixel electrode.

On the other hand, after being opened once, the pad part 11b maintains an open state until various layers are disposed on the substrate 11a. This may have a physical and chemical effect on the pad portion 11b. In addition, there may be a problem that the pad part 11b partially disappears during another process.

FIG. 4 is another diagram illustrating a configuration in which a pad part and source-drain electrodes are disposed in the display panel 11 of FIG. 2 . Since the pad part provides a signal to the gate line or the data line, the same material as the source-drain electrode is disposed on the substrate 11a of the display panel for an efficient process. However, unlike FIG. 2 , the source-drain electrode 11c is opened to arrange the pixel electrode, but the pad part 11b is not open.

Unlike FIG. 3 , since the pad part 11b is not opened, the protected state is continuously maintained until various layers are disposed on the substrate 11a. However, in order to connect the first driving unit 12 to the pad unit 11b, the pad unit 11b must be opened using a separate mask. Of course, when the pad part 11b is a gate pad part, it needs to be opened so as to be connected to the second driving part 13 .

3 and 4, when the passivation layer 11d is etched using a single mask as the source-drain electrode 11c for the pad portion 11b as shown in FIG. 3, the pixel electrode connected to the thin film transistor is formed. There is a problem in that the pad part 11b is exposed to various etching processes during the process of generating it.

On the other hand, when the passivation layer 11d is etched using a mask different from that of the source-drain electrode 11c for the pad portion 11b as shown in FIG. 4 , there is a problem in that a separate mask must be used. Accordingly, a method for increasing process efficiency by allowing the pad portion 11b to be etched using a single mask without being affected by a chemical process such as etching will be described.

5 is a view showing the configuration of a pad part and a source-drain electrode having a quadruple layer structure according to an embodiment of the present invention. The substrate 110 of FIG. 5 uses a substrate in which a light shield, an active layer, a gate layer, and an interlayer insulating layer are already formed before the pad part and the source-drain electrodes are formed. That is, it is assumed that the above-described components are disposed on the substrate 110 .

In FIG. 5 , the pad part 200 , the electrode part 180 of the bezel region, and the source-drain electrode 150 of the thin film transistor are disposed on the substrate 110 , and a passivation layer 115 , an overcoat An overcoat layer 120 , a pixel electrode 155 and a bank 160 are disposed. The bank 160 defines a light emitting area on the pixel electrode 155 .

The electrode unit 180 of the bezel region may be disposed to apply an electrical signal to the display panel or to provide a function such as preventing static electricity from flowing into the display panel, and may be selectively disposed.

The pad part 200 may be made of four layers of material, and similarly, the source-drain electrode 150 and the electrode part 180 of the bezel region may also be made of four layers of material. In the present specification, ITO, Moti, Cu, and Moti are used as an embodiment for the materials of the four layers, but in addition, various materials may be selected and configured. Of course, the pixel electrode 155 may also be composed of three layers. In one embodiment, it may be composed of ITO/Ag/ITO, but the present invention is not limited thereto, and the pixel electrode may be composed of one or two layers. .

5, that is, when the pad part 200 and the source-drain electrode 150 are formed with a quadruple layer (ITO/MoTi/Cu/MoTi), the pad part 200 is formed with ITO/Moti on Cu. Since a predetermined barrier is formed, a final complete structure can be derived without a separate passivation mask for the pad part 200 .

In addition, the number of masks can be reduced by integrating and simultaneously patterning the overcoat layer 120 and the passivation layer 115 . In this case, in the related art, the mask used to open the hole of the pad part 200 can be reduced, which increases process efficiency.

As shown in FIG. 5 , when the pad part 200 and the source-drain electrode 150 are formed of a quadruple layer (ITO/MoTi/Cu/MoTi), the pad part 200 is formed and etched in the passivation layer 115 process. ) can be opened, and a separate mask can be omitted. Accordingly, a process of forming the pad part and the source-drain electrodes on the display panel with the configuration shown in FIG. 5 will be described. In this specification, the source-drain electrode 150 refers to a component serving as either a source or a drain. Designated as the source-drain electrode may correspond to the source or the drain of the thin film transistor.

6 to 13 are views illustrating a process of forming a pad part and a source-drain electrode having the same structure as in FIG. 5 .

In 501 of FIG. 6 , a conductive material is stacked on the substrate 110 as a quadruple layer or quadruple layer to form a pad part and a source-drain electrode. In one embodiment, MoTi (510), Cu (520), Moti (530), and ITO (540) are laminated.

In order to pattern the conductive materials, photo resists are disposed as 550a, 550b, and 550c (refer to 502) and then wet-etched using Cu as an etchant. As a result, as shown in 503 of FIG. 7 , the degree of etching of the lower triple layers among the quadruple layers of the conductive material and the degree of etching of the ITO portion thereon may be different.

In one embodiment, the ITO portion is left with both edges protruding (see 503a, 503b, 503c exemplarily indicated at 503 in FIG. 7 ). Also, in step 503 , the pad part 200 , the electrode part 180 of the bezel region, and the source-drain electrode 150 are formed.

Thereafter, the ITO may be wet-etched as shown in 601 of FIG. 8 . Oz acid may be used for wet etching, and the protruding shapes exemplarily shown in 503a, 503b, and 503c of 503 of FIG. 7 disappear. Thereafter, when the photoresist is removed as shown in 602 of FIG. 8 , the pad part 200 , the electrode part 180 of the bezel region, and the source-drain electrode 150 are formed.

Thereafter, as shown in 603 of FIG. 9 , a passivation layer 115 is deposited on the entire surface of the display panel, and as shown in 604 of FIG. 9 , an overcoat layer 120 is also applied on the entire surface. During the deposition of the passivation layer 115 , the ITO layers 540a , 540b , and 540c are polyized. As a result, the robustness of the ITO layers 540a, 540b, and 540c is improved to protect the underlying layers 530, 520, and 510 made of conductive materials in the subsequent physical or chemical etching process. In particular, it is possible to block damage generated during chemical and physical processing of the second layers 540a, 540b, and 540c including Cu.

Thereafter, as shown in 701 of FIG. 10 , a half-tone photoresist 710 is applied. This allows the overcoat layer 120 and the passivation layer 115 to be etched simultaneously. First, as shown in 702 of FIG. 11 , the overcoat layer 120 is hole ashed.

Next, as shown in 703 of FIG. 11 , the passivation layer 115 is wet-etched. As a result, an open hole 750 of the pad part 200 and an open hole 740 of the source-drain electrode 150 are formed. In this case, in the process of etching the passivation layer 115 , the ITO layer 540a of the pad part 200 protects the materials below it. In particular, the second layer 520a including Cu is protected. Similarly, the ITO layer 540c of the source-drain electrode 150 may also protect the materials underneath it.

Thereafter, as shown in 801 of FIG. 12 , the remaining photoresist is stripped to complete the formation of the overcoat layer 120 and the passivation layer 115 . Then, as shown in 802 of FIG. 12 , the pixel electrode 155 is formed. In this process, after depositing the pixel electrode, wet etching is performed and the pixel electrode can be completed by stripping. The pixel electrode may be composed of multiple layers, and may be composed of ITO (155a), Ag (155b), and ITO (155c) according to an embodiment.

Thereafter, the bank 160 is formed as shown in 803 of FIG. 13 . A second substrate 1310 is also disposed in FIG. 13 , and a color filter 1320 may be selectively disposed on the second substrate 1310 . The color filter means converting a color of a pixel controlled by each pixel electrode 155 into red/green/blue (R/G/B).

When the process illustrated in FIGS. 6 to 13 is applied, since the ITO 540a is configured to be disposed on the upper surface of the pad part 200 , the pad part 200 is opened simultaneously with the source-drain electrode 150 of the thin film transistor. Even if it is, it can sufficiently protect the sub-materials. This may be crystallized ITO, that is, poly-crystalline ITO (ITO), which is crystallized as a high temperature is applied in the process of depositing the passivation layer on the ITO, and the ITO layer may be thinned or removed at the time the process is completed. have. Part 610 of FIG. 9 and part 810 of FIG. 13 will be enlarged.

14 is an enlarged view showing the configuration of the quadruple layer of the pad part according to an embodiment of the present invention. Part 610 of FIG. 9 is the pad part 200 in a state in which the passivation layer 115 is disposed, and reference numeral 540a is poly (crystallized) ITO. Since the 540a is disposed, the conductive materials 510a , 520a , and 530a disposed below are not affected by the external chemical process even during the subsequent etching of the passivation layer 115 .

On the other hand, in the state in which the hole 750 is formed by etching the passivation layer 115 , the ITO layer 540a poly-polished as shown in 810 may be maintained. However, according to another embodiment, a portion of the polyified ITO layer 540a may be etched and the polyified ITO layer 540a may be disposed only under the passivation layer 116 .

15 is a view showing a configuration in which the height of the pad portion ITO according to an embodiment of the present invention is not uniform. 15 shows a configuration in which the height of the area under the passivation layer 115 and the height of the polyized ITO of the open hole 750 are different from the polyized ITO layer 541a. When the 1010 part is enlarged and looked at, the height H1 of the area under the passivation layer 115 (the first area) and the height H2 of the ITO in the area where the passivation layer 115 is open (the second area) are compared. H1 > H2.

This shows a phenomenon in which the ITO area of the pad part is partially etched out by subsequent chemical and physical influences after the area is opened. That is, in the pad part 200 of the display panel or substrate according to the embodiment of the present invention, the height of the layer containing the polyized ITO in the region where the passivation is disposed includes the polyized ITO in the region where the passivation is not arranged. In one embodiment, it is larger than the height of the layer to be used.

In addition, the height of the ITO in the second region close to the first region may be higher than H2. When this is close to the first region under the passivation layer 115 , physical or chemical effects may be reduced due to the step difference. Therefore, it is summarized as follows.

The height between the polyified ITO layer 541a of the first region and the polyified ITO layer of the second region is in a decreasing direction, where the boundary between the second region R2 and the first regions R1a and R1b is The height of the ITO layer may be higher than H2.

Referring to FIG. 15 , the first regions R1a and R1b of the pad part 200 include a first layer 510a including MoTi, a second layer 520a including Cu, and a third layer including Moti. 530a, and a fourth layer 541a comprising polyized ITO. In addition, a passivation layer 115 is disposed on the first regions R1a and R1b of the fourth layer 541a. The first to third layers 510a to 530a that are disposed below the fourth layer 541a are protected by the arrangement of the polymorphized ITO. In addition, the electrical properties of the pad part 200 may be improved by repeatedly disposing the conductive materials. The passivation layer 115 may be disposed on the edge of the pad part 200 according to the configuration of the mask. The passivation layer 115 blocks the side surface of the pad part 200 from the outside and selectively blocks the top edge so that the conductive materials constituting the pad part 200 can insulate the side surface and the top edge from other electrical elements. .

Meanwhile, the second region R2 of the pad part 200 is similarly formed with a first layer 510a containing MoTi, a second layer 520a containing Cu, a third layer 530a containing MoTi, and likewise composed of a fourth layer 541a comprising polyized ITO. However, the passivation layer 115 is not disposed on the fourth layer of the second region. In addition, the height H1 of the fourth layer in the first region is higher than the height H2 of the fourth layer in the second region. This means that the open hole 750 of the pad part 200 is exposed to chemical and physical processes as much as H2 is reduced, and shows that the lower conductive material is sufficiently protected. If the polyized ITO layer is not disposed, there is a problem in that a new mask is required because damage caused by physical and chemical processes to the second layer 520a including Cu is large. However, when the embodiment of the present invention is applied, since the second layer 520a containing Cu and the third layer 530a thereon are sufficiently protected by polyized ITO, the number of masks is reduced and process efficiency is increased. The pad part 200 and the source-drain electrode 150 may be formed so as to be exposed.

Meanwhile, in the configuration of FIG. 15 , H2 may be zero. This will be looked at in FIG. 16 .

16 is a view showing a configuration in which the ITO of the pad part according to an embodiment of the present invention is removed from the hole. 15 , the first regions R1a and R1b of the pad part 200 include a first layer 510a including MoTi, a second layer 520a including Cu, and a third layer including Moti ( 530a), and a fourth layer 542a, 543a comprising polyized ITO. A passivation layer 115 is disposed on the fourth layers 542a and 543a.

However, the configuration of the second region is composed of a first layer 510a containing MoTi, a second layer 520a containing Cu, and a third layer 530a containing Moti, and in the second region R2, The ITO layer is not disposed. And the third layer 530a has a structure in which a passivation layer is not disposed.

Unlike FIG. 15 , ITO is not disposed in the hole 750 area (the second area). This shows a phenomenon in which the ITO area of the pad part is partially etched out by subsequent chemical and physical influences after the area is opened. It means that the polyized ITO previously disposed in the open hole 750 of the pad part 200 is removed by exposure to chemical and physical processes, and the lower conductive material is sufficiently protected instead of the polyized ITO being removed. show that it has been If the polyized ITO layer is not disposed, there is a problem in that a new mask is required because damage caused by physical and chemical processes to the second layer 520a including Cu is large. However, when applying the embodiment of the present invention, since the polyized ITO is removed instead of the second layer 520a containing Cu and the third layer 530a thereon, process efficiency while reducing the number of masks The pad part 200 and the source-drain electrode 150 may be formed to increase the .

In addition, a trace amount of the ITO layer may be present in the second region close to the first region. When this is close to the first region under the passivation layer 115 , physical or chemical effects may be reduced due to the step difference. Therefore, it is summarized as follows.

The height between the polyized ITO layers in the second region is zero when compared to the polyized ITO layers 542a, 543a in the first region, but here the boundary between the second region R2 and the first regions R1a, R1b In some parts the ITO layer can be present, although at a very low height.

Therefore, when the embodiment of the present invention is applied, the height of the ITO of the pad part may be 0 or 0 or more. In addition, the height of the ITO of the pad portion may be lower than the height of the ITO under the passivation layer.

In summary, it is as follows. A display panel according to an embodiment of the present invention includes a first substrate including a display area 20 and a non-display area 21 outside of the display area 20 as shown in FIGS. 1 and 2 , and facing the display area 20 . and a second substrate 1310 disposed thereon. A plurality of color filters 1320 may be included in the second substrate 1310 .

Also, as described above, in the display area 20 , a plurality of gate lines, a plurality of data lines, and a plurality of thin film transistors for controlling each pixel are disposed at intersections of the gate lines and the data lines. As described above, in the non-display area 21 , a plurality of pad parts 200 may be disposed. The configuration of the pad part 200 is as shown in FIGS. 15 and 16 , the area under the passivation layer 115 is It consists of 4 layers.

In the pad part 200 , an area in which the passivation layer 115 is not disposed is a quadruple layer as shown in FIG. 15 or a triple layer as shown in FIG. 16 . This configuration of the pad part 200 may be equally applied to the source-drain electrode 150 . The source-drain electrode 150 and the pad part 200 may be produced in the same process except for the case where the pixel electrode 155 is disposed up to process 801 of FIGS. 6 to 12 .

Accordingly, as previously described with reference to FIGS. 15 and 16 , the configuration of the region under the passivation layer and the region where the pixel electrode 155 is coupled to the source-drain electrode 150 may be different.

15 and 16 , the conductive materials constituting the pad part 200 disposed in the non-display area are poly-polished so that they can be sufficiently protected during various processes in the display area for generating the pixel electrode and arranging the bank. The ITO is disposed on the pad part 200 . As a result, since the pad part 200 can be formed in the same process in the process of forming the source and drain, the number of masks can be reduced and the efficiency of the process can be increased while protecting the pad part 200 . In addition, by reducing the number of masks, a process error occurring in the mask alignment process can also be reduced.

17 is a view showing a configuration applied to the source-drain electrode 150 according to an embodiment of the present invention. Part 820 of FIG. 13 is an enlarged configuration. 15 , the third regions R3a and R3b have a quadruple layer like the first regions R1a and R1b of FIG. 15 , and the fourth region R4 is the second region R2 of FIG. 15 . It is a four-layered configuration. 1701 is enlarged and examined. The height H3 of the fourth layer 540c in the third regions R3a and R3b is higher than the height H4 of the fourth layer 540c in the fourth region R4.

18 is a view showing a configuration applied to the source-drain electrode 150 according to an embodiment of the present invention. Part 820 of FIG. 13 is an enlarged configuration. 16 , the third regions R3a and R3b have a quadruple layer like the first regions R1a and R1b of FIG. 16 , and the fourth region R4 is formed with the second region R2 of FIG. 16 . It is a three-tiered configuration. Let's take a closer look at the 1801 part. The height H3 of the fourth layer 540c in the third regions R3a and R3b is greater than 0, and the fourth layer is not disposed in the fourth region R4.

Meanwhile, in the configuration of FIG. 18 , H4 may be larger than H2 of FIG. 15 . This is because, since pixel electrodes are disposed in the R4 region of FIG. 18 , the possibility that 540c of the R4 region is etched by a subsequent process is lowered. Therefore, the following relationship between H1, H2, and H4 may satisfy H1 > H4 > H2.

Hereinafter, a configuration in which the pad part according to another embodiment of the present invention is composed of three layers will be described. A process in which the passivation layer 115 of the portion 610 of FIG. 9 is etched in the processes of FIGS. 10 and 11 has been described previously. An embodiment in which the size of a mask for etching the passivation layer 115 is different will be described.

19 is a view showing the configuration of a pad part according to another embodiment of the present invention. When adjusting the size of the mask for viewing the passivation layer 115 of the portion 610 of FIG. 9 , it may be configured such that the entire polyified ITO layer 540a is opened as in 1910. In this case, in a subsequent chemical or physical process process, the height of the polyified ITO layer 1940a as shown in 1911 may be reduced.

Alternatively, as in 1912, the entire polyified ITO layer 540a may be removed in a subsequent chemical or physical process.

In summary, as shown in 1912 of FIG. 19 , the pad part 200 includes a first layer 510a including MoTi, and a second layer 520a and a second layer 520a including Cu on the first layer 510a. ) may be composed of only the third layer 530a including MoTi on it. In this case, as in 1912 , the passivation layer 115 may be disposed on the side portions 1922 of the three layers 510a , 520a , and 530a constituting the pad part 200 .

Also, the polyized ITO layer as in 1911 may remain as in 1940a. In this case, the height of 1940a may be lower than that of the ITO layer 540a that is the fourth layer of 1910 . Also, as shown in 1911 , the passivation layer 115 may be disposed on the side portions 1921 of the four layers 510a , 520a , 530a , and 1940a constituting the pad part 200 .

The passivation layer 115 is disposed on the side surface of the pad unit 200 according to the configuration of the mask to block the side surface of the pad unit 200 from the outside so that the conductive materials constituting the pad unit 200 are separated from other electrical elements on the side surface. to be insulated. In addition, since a separate passivation layer 115 is not disposed on the upper surface, a contact point at which the pad unit 200 is electrically connected to the driving units may be increased.

It has been seen in FIGS. 17 and 18 that such a configuration can be equally applied to the source or the drain.

In the configuration shown in FIG. 19 , the region in which the passivation layer is maintained may be the side portions 1921 and 1922 .

20 is a diagram illustrating a process of manufacturing a display panel according to an embodiment of the present invention.

First, a light blocking layer is disposed on the first substrate (S2010). S2010 can be an optional process. An active layer is disposed on the above-described first substrate (S2020). The active layer is not necessarily disposed on the light blocking layer of the first substrate. The active layer may be disposed on the light blocking layer, or the active layer may be disposed on a second surface opposite to the first surface of the first substrate on which the light blocking layer is disposed. In addition, a gate layer is disposed so that at least a part of it overlaps with the active layer (S2030). If the S2030 process is configured in more detail, the gate layer may be disposed after the gate insulating layer is disposed.

The configuration of the gate layer or the active layer may be arranged in various configurations and in various orders according to the configuration of a top gate, a bottom gate, or an etch stopper type gate, and the present invention is not limited thereto. Accordingly, although the gate layer is disposed after the active layer is disposed in S2010 to S2030, the present invention is not limited thereto.

Accordingly, after the gate layer is first disposed, the gate insulating layer may be disposed and the active layer may be disposed to partially overlap the gate layer. Thereafter, an interlayer dielectric (ILD) is disposed on the first substrate formed until S2030 (S2040). The first substrate disposed up to the interlayer insulating layer in this way corresponds to the embodiment of the substrate 110 of FIG. 5 .

Thereafter, as shown in FIGS. 6 to 13 , the source-drain electrode 150 and the pad part 200 are arranged in a quadruple layer ( S2050 ). This was looked at at 501 of FIG. 6 . In an embodiment, the first layer ( 510 in FIG. 6 ) includes MoTi and the second layer ( 520 in FIG. 6 ) includes Cu. The third layer (530 in FIG. 6 ) includes MoTi, and the fourth layer ( 540 in FIG. 6 ) includes ITO.

And after disposing the passivation layer 115 and the overcoat layer 120 thereon as shown in FIG. 9 (S2060), these passivation layer 115 and the overcoat layer 120 using a mask as shown in FIGS. ) to maintain the passivation layer in the first region of the pad part 200 and remove the passivation layer in the second region of the pad part ( S2070 ). In this process, the source-drain electrode 150 is also exposed. Using one mask, the passivation layer 115 and the overcoat layer 120 disposed on the pad part 200 and the source-drain electrodes 150 may be removed.

As shown in FIG. 9 , while the passivation layer 115 is deposited, the ITO layers 540a, 540b, and 540c are poly- ized by heat. Accordingly, the ITO layers 540a, 540b, and 540c after the deposition process and the etching process of the passivation layer 115 are completed are poly(crystallized).

A halftone mask can be used in the S2070. Various embodiments in which the passivation layer is removed from a predetermined area of the pad part have been described in FIGS. 15, 16, and 19 . Thereafter, as shown in 802 of FIG. 12 , the pixel electrode 155 is disposed on the source-drain electrode 150 ( S2075 ), and as shown in FIG. 13 , a bank 160 defining a light emitting region is disposed on the pixel electrode 155 , (S2080), the second substrate 1310 on which the color filters are selectively disposed and the first substrate are combined (S2090) to complete the manufacturing process of the display panel.

In the process shown in FIG. 20, since a total of eight masks are used as in the processes of S2010, S2020, S2030, S2040, S2050, S2060, S2075, and S2080, the efficiency of the process can be increased and the process cost can be lowered. In particular, since the pad part and the source-drain electrode can be formed using a single mask, process efficiency can be greatly improved. In addition, process errors can also be reduced by reducing the number of masks.

21 is a view showing the configuration of a display panel when the same process as in FIG. 20 is applied.

A base substrate 2102 on which glass or other various thin film transistors can be installed is disposed on the lower plate 1305 , and light shield layers 2103s and 2104s are disposed thereon. The light blocking layer may be composed of a double layer. Alternatively, 2104s may be disposed with a chemical that allows the light blocking layer to be well disposed on the base substrate 2102 . In addition, in the same process as the light blocking layers 2103s and 2104s, they may be disposed as in 2103e and 2104e to form the EVSS auxiliary electrode.

Next, a buffer layer 2105 is disposed, and the buffer layer may be partially etched to expose it.

And to configure the thin film transistor, an active layer 2120 , a gate insulating layer 2115t , and gate layers 2110t and 2111t are disposed. In this process, the same material 2115p as the gate insulating layer 2115t and the same materials 2110p and 2111p as the gate layers 2110t and 2111t are disposed in the non-display area where the pad part 200 is to be disposed in the same structure. can

Next, an interlayer insulating layer (ILD, 2125) is disposed, and a partially etched state becomes an embodiment of the substrate 110 as described above with reference to FIGS. 6 to 13 .

Thereafter, 2160 may be configured as a quadruple layer to form the pad part 200 , the source-drain electrodes 150 , and the EVSS auxiliary electrode. The source-drain electrode 150 may be electrically connected to the light blocking layer 2103s.

Then, after the passivation layer 115 and the overcoat layer 120 transferred thereto are deposited and etched, the pixel electrode 155 is disposed. In this process, the VSS contact electrode 2150 may also be disposed together with the pixel electrode 155 . Thereafter, a bank 160 is disposed to define a light emitting area. Then, the second substrate 1310, which is the upper plate on which the color filter 1320 is disposed, and the first substrate are combined.

The number of masks applied to the lower plate when the pad part and the source-drain of the quadruple layer structure of the present invention described above are simultaneously formed in the same process, especially when applied to an organic light emitting diode display having a top emission structure. can be reduced to increase productivity.

Since the passivation layer 115 and the overcoat layer 120 can be integrated and deposited and etched by applying the SD quadruple layer, process efficiency is increased. In addition, when forming the pad part 200 and the source-drain electrode 150 in a quadruple layer structure using ITO as the uppermost layer, in the process of depositing and etching the passivation layer 115 and the overcoat layer 120, the lower 3 The interlayer (Moti-Cu-Moti layer) can be protected.

The above-described structure may protect the lower three layers of the pad part 200 even in the wet etching process of the pixel electrode forming process to be developed later. In this process, the uppermost layer (polyized ITO layer) may remain in the pad part 200, some may be removed, or all may be removed.

Embodiments of the present invention can be applied to various structures of thin film transistors, and among them, embodiments in which the source, drain, and pad are formed in a quadruple layer in the same process are included.

According to an embodiment, the pad unit 200 of FIG. 21 constitutes a data pad unit connected to a data line. In addition, according to an embodiment, the pad part 200 of FIG. 21 constitutes a gate pad part connected to the gate line. Although not shown in the drawing, the pad unit 200 and the data line may be formed of the same quadruple layer or triple layer.

In the above, although the embodiment of the present invention has been mainly described, various changes or modifications may be made at the level of those skilled in the art. Accordingly, it will be understood that such changes and modifications are included within the scope of the present invention without departing from the scope of the present invention.

11: Display panel
10: display device
20: display area
110: substrate
115: passivation layer
120: overcoat layer
150: source-drain electrode
155: pixel electrode
160: bank
200: pad part

Claims (20)

A display area comprising a plurality of gate lines and a plurality of data lines and a plurality of thin film transistors for controlling each pixel at intersections of the gate lines and data lines, and at least one pad portion disposed in an outer area of the display area a first substrate including a non-display area; and
a second substrate disposed opposite to the first substrate;
A display panel including a multi-layered pad unit, wherein the first area of the pad unit is a quadruple layer, the second region is formed of any one of a quadruple layer or a triple layer, and the first region constitutes an outer periphery of the second area.
According to claim 1,
The source or drain of the thin film transistor includes a third region having the same configuration as the first region and a fourth region having the same configuration as the second region, and the source or drain is generated in the same process as the pad portion, A display panel including a multi-layered pad unit.
According to claim 1,
The first area is
a first layer comprising MoTi;
a second layer including Cu on the first layer;
a third layer including MoTi on the second layer; and
a fourth layer comprising polyized ITO on the third layer;
and a multi-layered pad portion, wherein a passivation layer is disposed on the fourth layer in the first region.
According to claim 1,
The second area is
a first layer comprising MoTi;
a second layer including Cu on the first layer;
a third layer including MoTi on the second layer; and
a fourth layer comprising polyized ITO on the third layer;
and a multi-layered pad part in which a passivation layer is not disposed on the fourth layer in the second region.
5. The method of claim 4,
and a height of the fourth layer in the first region is higher than a height of the fourth layer in the second region, and a multi-layered pad part.
According to claim 1,
The second area is
a first layer comprising MoTi;
a second layer including Cu on the first layer; and
and a third layer including MoTi on the second layer,
and a multi-layered pad part in which a passivation layer is not disposed on the third layer in the second region.
a plurality of thin film transistors disposed in the display area to control electrical operations of pixels;
a pad unit including a quadruple layer made of a conductive material, a first region having a passivation layer disposed thereon, and a second region having a triple layer made of a conductive material disposed thereon, the pad part being disposed outside the display area; and
a plurality of data lines electrically connecting a source or drain of the thin film transistor and the pad unit; and
A substrate comprising a multi-layered pad portion including a plurality of gate lines connected to a gate of the thin film transistor.
8. The method of claim 7,
The source or drain includes a third region having the same configuration as the first region and a fourth region having the same configuration as the second region, and the source or drain is generated in the same process as the pad part. A substrate including a pad part.
8. The method of claim 7,
The first area is
a first layer comprising MoTi;
a second layer including Cu on the first layer;
a third layer including MoTi on the second layer; and
a fourth layer comprising polyized ITO on the third layer;
and a multi-layered pad portion in which the passivation layer is disposed on the fourth layer in the first region.
8. The method of claim 7,
The second area is
a first layer comprising MoTi;
a second layer including Cu on the first layer;
and a third layer including MoTi on the second layer,
A substrate including a multi-layered pad portion in which a passivation layer is not disposed on the third layer in the second region.
11. The method of claim 10,
A substrate comprising a multi-layered pad portion comprising a fourth layer comprising polyized ITO on the third layer.
12. The method of claim 11,
and a height of the fourth layer in the first region is higher than a height of the fourth layer in the second region;
A display area comprising a plurality of gate lines and a plurality of data lines and a plurality of thin film transistors for controlling each pixel at intersections of the gate lines and data lines, and at least one pad portion disposed in an outer area of the display area a first substrate including a non-display area; and
a second substrate disposed opposite to the first substrate;
The pad part comprises a multi-layered pad part comprising a first layer containing MoTi, a second layer containing Cu on the first layer, and a third layer containing MoTi on the second layer,
A passivation layer is disposed on side surfaces of the first layer, the second layer, and the third layer, but the passivation layer is not disposed on the top surface of the third layer.
14. The method of claim 13,
and a source or drain of the thin film transistor has the same configuration as that of the pad part, and the source or drain is generated in the same process as the pad part.
A display area comprising a plurality of gate lines and a plurality of data lines and a plurality of thin film transistors for controlling each pixel at intersections of the gate lines and data lines, and at least one pad portion disposed in an outer area of the display area a first substrate including a non-display area; and
a second substrate disposed opposite to the first substrate;
The pad part comprises a first layer containing MoTi, a second layer containing Cu on the first layer, a third layer containing MoTi on the second layer, and polyized ITO on the third layer. A display panel including a multi-layered pad part, including a fourth layer including a fourth layer.
16. The method of claim 15,
A passivation layer is disposed on side surfaces of the first layer, the second layer, the third layer, and the fourth layer.
17. The method of claim 16,
The passivation layer is not disposed on an upper surface of the fourth layer.
disposing a source, a drain, and a pad portion in a quadruple layer on a first substrate;
disposing a passivation layer and an overcoat layer on the disposed source, drain, and pad portions;
etching the passivation layer and the overcoat layer to maintain the passivation layer in a first region of the pad part and removing the passivation layer in a second region of the pad part;
disposing a pixel electrode at the source or drain; and
and disposing a bank defining a light emitting region on the pixel electrode.
19. The method of claim 18,
The four layers are
a first layer comprising MoTi;
a second layer including Cu on the first layer;
a third layer including MoTi on the second layer; and
A method of manufacturing a display panel including a multi-layered pad portion including a fourth layer including ITO on the third layer.
20. The method of claim 19,
When the fourth layer is disposed in the first region, the fourth layer is a polyized ITO layer.

Images