KR20070077387A - Method for forming of semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to enhance an electric characteristic of a device by superposing mother verniers used in lower layers. A box-shaped mother vernier for harmonizing patterns of a first lower layer is formed, and then a second box-shaped mother vernier for harmonizing patterns of a second lower layer is formed, in which the second mother vernier has a size slightly smaller than that of the first mother vernier. The first mother vernier is superposed on the second mother vernier to form a mother vernier(25). A rectangular son vernier(27) is formed in the mother vernier.

Description

Method of forming a semiconductor device {METHOD FOR FORMING OF SEMICONDUCTOR DEVICE}

1A and 1B are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.

2 is a photographic view illustrating a problem of a method of forming a semiconductor device according to the prior art.

3 is a graph showing the degree of mis-alignment occurring between the lower layer and the upper layer of the prior art.

4A to 4D are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a semiconductor device capable of simultaneously satisfying the degree of overlap between two or more lower and upper layers.

In general, when fabricating a semiconductor device having a stacked structure, an overlay vernier is formed on a wafer in order to identify and correct an alignment state between a previously formed lower layer and a currently formed layer. Form with).

In the manufacture of existing semiconductor devices, the density is low and is formed by considering only the overlap between the currently formed layer and one previously formed lower layer. Especially, in the landing plug contact mask process, the vernier used in the previous gate process and device isolation process is used. Is as shown in FIG. 1A.

However, as semiconductor devices are highly integrated, it is important to accurately overlap two or more lower and upper layers formed in the same direction, and thus, two types of overlay verniers are used as shown in FIG. 1B.

However, in the current overlay vernier, as shown in FIG. 2A, a misalignment occurs because the recess gate region 11 and the gate 13 do not coincide in the gate forming process, or as shown in FIG. 2B. As shown, it can be seen that the gate 13 is not formed symmetrically with respect to the isolation region 15.

3 shows the degree of mis-alignment between the lower and upper layers of the prior art.

Referring to FIG. 3, misalignment occurs about 15 nm between the isolation region and the recess gate region, and misalignment occurs about 20 nm between the recess gate region and the gate. 35 nm of misalignment occurs between the final gate and the device isolation (ISO) region.

The above-described method of forming a semiconductor device according to the related art has a problem in that when two or more lower layers formed in the same direction are not properly overlapped with the upper layer, they are misaligned.

The present invention has been created to solve the above problems, and even when there are two or more lower layers formed in the same direction, a method of forming a semiconductor device capable of optimizing the degree of overlap by overlapping the vernier used in each layer The purpose is to provide.

A method of forming a semiconductor device of the present invention for achieving the above object comprises the steps of: forming a first mother vernier in the form of a box to match the pattern of the first lower layer; Forming a box-shaped second parent vernier having a size smaller than the first parent vernier for matching the pattern of the second lower layer; Superimposing a first parent vernier and a second parent vernier to form a parent vernier; It characterized in that it comprises a step of forming a quadrature ruler vernier inside the mother vernier.

In addition, in the method of forming a semiconductor device including a gate of the present invention, the process of forming the gate comprises forming an isolation region in the semiconductor substrate of the cell region, and forming a first parent vernier in the scribe lane; Etching the semiconductor substrate with a mask defining the recess gate region to form a recess gate region, and forming a second mother vernier in the scribe lane; And forming a gate in the recess gate region and forming a vernier in the scribe lane.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A through 4D are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Referring to FIG. 4A, a first mother vernier 21 having a box shape is formed.

In this case, the first mother vernier 21 is preferably formed to match the pattern of the first lower layer.

Referring to FIG. 4B, a second mother vernier 23 having a box shape having a size smaller than that of the first mother vernier 21 is formed.

At this time, the second mother vernier 23 is preferably formed to match the pattern of the second lower layer.

Referring to FIG. 4C, an outer box 25 is completed by overlapping the first mother vernier 21 and the second mother vernier 23.

At this time, it is preferable that the overlap interval d1 is formed at 1 μm to 50 μm.

Referring to FIG. 4D, a quadrangle ruler vernier 27 is formed inside the parent vernier 25.

As described above, in the present invention, when the first mother vernier 21 and the second mother vernier 23 are overlapped at a predetermined interval to form the mother vernier 25, there are two or more lower layers formed in the same direction. In addition, the accuracy of the alignment can be improved.

Meanwhile, the overlay vernier according to the present invention may be used in semiconductor devices to which light sources such as 365 nm, 248 nm, and 193 nm are applied during the exposure process.

Although not shown in the drawings, a method of forming a semiconductor device using the parent vernier 25 having the above configuration is as follows. Here, the gate forming process will be described as an example.

First, when the device isolation region is formed in the semiconductor substrate of the cell region, the first parent vernier 21 is formed in the scribe lane.

Next, the semiconductor substrate is etched with a mask defining a recess gate region to form a recess gate region, and the second parent vernier 23 is formed in a scribe lane.

Next, after the gate oxide film, the conductive film, and the hard mask layer are formed on the semiconductor substrate including the recess gate region, the gate oxide film, the conductive film, and the hard mask layer are etched using a gate mask to form a gate. At this time, the magnetic vernier 27 is formed in the scribe lane.

At this time, the first isolation | separation region and the recess gate area are not mis-aligned by overlapping the said 1st mother vernier 21 and the said 2nd mother vernier 23, and the overlapping degree is optimized.

As described above, in the method of forming the semiconductor device of the present invention, even when two or more lower layers are formed in the same direction, the overlapping of the verniers used in each layer is optimized to improve the electrical properties of the device by optimizing the degree of overlap. It can be effective.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

Forming a first parent vernier in the form of a box to match the pattern of the first lower layer; Forming a box-shaped second parent vernier having a size smaller than the first parent vernier for matching the pattern of the second lower layer; Overlapping the first parent vernier and the second parent vernier to form a parent vernier; And Forming a quadrature ruler vernier inside the parent vernier; Forming method of a semiconductor device comprising a. The method of claim 1, wherein the overlap interval is 1 μm to 50 μm. In the method of forming a semiconductor device comprising a gate, the step of forming the gate is Forming an isolation region in the semiconductor substrate in the cell region and forming a first parent vernier in the scribe lane; Etching the semiconductor substrate with a mask defining a recess gate region to form a recess gate region, and forming a second mother vernier in the scribe lane; And Forming a gate in the recess gate region and forming a vernier in the scribe lane Forming method of a semiconductor device comprising a. 4. The method of claim 3, wherein the first vernier and the second vernier are overlapped to form a parent vernier. The method of claim 3, wherein the overlap interval is 1 μm to 50 μm.

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