KR20070076043A - Semiconductor memory device and method for fabricating the same - Google Patents

Abstract

A semiconductor memory device is provided to increase the effective area of a capacitor by making the capacitor have a protruded sidewall profile of an unevenness type. A first interlayer dielectric(110) in which a storage node contact(115) is formed is formed on a semiconductor substrate(100). A second interlayer dielectric is formed on the first interlayer dielectric, having an opening(130H) with a protruding sidewall of an unevenness type. A capacitor(140) is conformally formed on the bottom and sidewall of the opening, having substantially the same profile as that of the sidewall of the opening and including a lower electrode(141), a dielectric layer(143) and an upper electrode(145). The lower electrode comes in contact with the storage node contact. The dielectric layer is conformally formed on the lower electrode according to the profile of the lower electrode. The upper electrode is formed on the dielectric layer.

Description

Semiconductor memory device and method for fabricating the same {Semiconductor memory device and Method for fabricating the same}

1 is a layout diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3 to 7 are cross-sectional views sequentially illustrating a method of manufacturing the semiconductor memory device shown in FIG. 2.

(Explanation of symbols for the main parts of the drawing)

100 semiconductor substrate 110 first interlayer insulating film

115: storage node contact 120: second interlayer insulating film

125: mask pattern 130H: opening

140: capacitor 141: lower electrode

143: dielectric film 145: upper electrode

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device including a capacitor with improved capacity and a method of manufacturing the same.

Recently, with the trend toward miniaturization, integration, and thickness, semiconductor memory devices have been required to have high capacity and high speed functionally. Accordingly, attempts have been made to increase the capacitance of the capacitor of the semiconductor memory device, that is, the capacitance.

To this end, stacked or trench type capacitors have been applied as various attempts to increase the effective area of capacitors. In addition, efforts have been made to increase the effective area of the capacitor by maximizing the height of the capacitor.

However, in order to increase the height of the capacitor, it is necessary to increase the thickness of the capacitor storage node electrode, that is, the interlayer insulating layer for forming the lower electrode, and the increase of the thickness makes the etching process for forming the lower electrode difficult. As such, the etching process for forming the lower electrode may not be performed properly, which may cause problems such as a bridge failure between the lower electrodes of the capacitor or poor contact between the lower electrode and the storage node contact. There is a fear that the characteristics of the semiconductor memory device may deteriorate.

An object of the present invention is to provide a semiconductor memory device having an improved capacitor capacity.

Another object of the present invention is to provide a method of manufacturing the semiconductor memory device described above.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor memory device according to an embodiment of the present invention for achieving the technical problem is formed on the first interlayer insulating film, the first interlayer insulating film formed on the semiconductor substrate and the storage node contact therein, and in the form of irregularities A second interlayer insulating film having an opening having a protruding sidewall, and a lower electrode conformally formed on the bottom and sidewalls of the opening and having a substantially same profile as the sidewall of the opening and contacting the storage node contact; A capacitor including a dielectric film conformally formed on the lower electrode and an upper electrode formed on the dielectric film according to the profile of the electrode is provided.

In addition, according to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, forming a first interlayer insulating film on a semiconductor substrate, forming a storage node contact in the first interlayer insulating film, and A second interlayer insulating film is formed on the first interlayer insulating film, and sidewalls are formed in the second interlayer insulating film so that the sidewalls protrude from the concave-convex shape and expose the upper surface of the storage node contact, and conformally to the bottom and sidewalls of the openings. And a lower electrode having a profile substantially the same as a sidewall of the opening, contacting the storage node contact, conformally forming a dielectric film on the lower electrode according to the profile of the lower electrode, and forming the dielectric film. Forming an upper electrode on the substrate.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Embodiments described herein will be described with reference to cross-sectional and / or plan views, which are ideal exemplary views of the present invention. Accordingly, the shape of the exemplary diagram may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. For example, the etched regions shown at right angles may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device and not to limit the scope of the invention.

Hereinafter, a semiconductor memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2. 1 is a layout view of a semiconductor memory device, specifically, a capacitor of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the semiconductor memory device according to II ′ of FIG. 1.

1 and 2, a semiconductor memory device according to an embodiment includes a first interlayer insulating layer 110 formed on a semiconductor substrate 100. Although not illustrated in the drawing, the semiconductor substrate 100 includes transistors including a gate electrode, a source, and a drain region on the semiconductor substrate 100.

In this case, the storage node contact 115 is positioned in the first interlayer insulating layer 110. The storage node contact 115 electrically connects a source region (not shown) formed in the semiconductor substrate 100 and a capacitor 140 formed thereon. In this case, the storage node contact 115 may be directly connected to the source region. Alternatively, the storage node contact 115 may be connected to a predetermined landing pad (not shown) formed on the source region. The storage node contact 115 may be formed of a metal material such as, for example, tungsten, and may further include a diffusion barrier layer for suppressing diffusion of the metal material.

The capacitor 140 is formed on the opening 130H formed in the second interlayer insulating layer 120 positioned on the first interlayer insulating layer 110, and the lower electrode 141 is in contact with the top surface of the storage node contact 115. The dielectric layer 143 and the upper electrode 145 may be formed in a cylindrical shape. As shown in FIG. 1, the sidewall of the capacitor 140 included in the semiconductor memory device according to the exemplary embodiment protrudes in an uneven form. That is, the capacitor 140 is formed by reflecting the sidewall profile of the opening 130H having the uneven shape. In detail, the lower electrode 141 is conformally formed on the uneven sidewall and contacts the upper surface of the storage node contact 115. Since the lower electrode 141 has a profile reflecting the concave-convex shape of the opening 130H, the dielectric film 143 and the upper electrode 145 formed thereon may also have a concave-convex profile. Therefore, since the effective area of the capacitor 140 increases according to the degree of concavities and convexities, the capacity of the capacitor 140 can be increased thereby. At this time, the degree of unevenness is not limited to that shown in the drawings, of course, may be further increased or reduced than shown in the drawings within the scope of the present invention.

The lower electrode 141 and the upper electrode 145 may be used as a single film or a composite film, for example, polysilicon, TiN, TaN, WN, Ru, Pt, Ir, Os, Ph, Co, Ni, or the like. Can be. As the dielectric film 143, for example, a tantalum oxide film, BST, PZT, AHO (aluminum oxide and hafnium oxide) composite film, HAH composite film, or the like can be used.

Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 3 to 7. In the following description of the manufacturing method, a process that can be formed according to process steps well known to those skilled in the art will be briefly described in order to avoid obscuring the present invention. In addition, the process that can be formed according to the process steps that are well known to those skilled in the art in the following description of the manufacturing method will be outlined in order to avoid being ambiguously interpreted. In addition, the size, shape, material, etc. of each component described in the above structure will be omitted or briefly described in order to avoid duplication of description.

First, as shown in FIG. 3, the first interlayer insulating layer 110 having the storage node contact hole 115H is formed on the semiconductor substrate 100. Although not shown in the drawings, a plurality of transistors are formed on the semiconductor substrate 100.

The storage contact hole 115H may be formed to expose the source region of the transistor, but when the pad electrode contacting the source region is formed between the gate electrodes, the storage contact hole 115H may be formed to expose the top surface of the pad electrode.

Next, as shown in FIG. 4, the storage node contact hole 115H is filled with a conductive material to complete the storage node contact 115.

In this case, a conductive material forming the storage node contact 115 may be, for example, a metal such as tungsten or polysilicon doped with impurities. In the case where a metal is used, a diffusion barrier film may be further formed before the conductive material is embedded.

Next, as shown in FIGS. 5A and 5B, a second interlayer insulating layer 120 is formed. Next, a mask pattern 125 is formed on the second interlayer insulating layer 120, and then an opening 130H is formed in the second interlayer insulating layer 120 to expose the top surface of the storage node contact 115.

The opening 130H is a region in which the cylinder type capacitor is to be formed, and FIG. 5B illustrates a view of the opening 130H viewed from the upper portion of the region corresponding to II-II ′. As shown in FIG. 5B, the opening 130H is formed such that the sidewall profile protrudes in an uneven shape. To this end, a mask pattern 125 corresponding to the concave-convex shape of the opening 130H when the second interlayer insulating layer 120 is etched is formed, and the second interlayer insulating layer 120 is patterned using the mask pattern 125 as an etching mask.

6, the lower electrode 141 is formed on the bottom and sidewalls of the formed opening 130H. In this case, since the lower electrode 141 may be conformally formed on the bottom and sidewalls of the opening 130H, the sidewalls may be formed in an uneven shape to reflect the profile of the opening 130H. As a result, the surface area of the lower electrode 141 may increase according to the degree of irregularities of the sidewalls.

Subsequently, as shown in FIG. 7, a dielectric film 143 covering the lower electrode 141 is formed. In this case, since the dielectric layer 143 may be conformally formed on the lower electrode 141 and the second interlayer insulating layer 120, the dielectric layer 143 formed in the opening 130H may have a concave-convex shape of the lower electrode 141. The protruding profile may be reflected as it is.

Then, the upper electrode 145 is formed on the dielectric film 143. In this case, the upper electrode 145 may be conformally formed on the dielectric layer 143, but is not limited thereto. The upper electrode 145 may be formed to fill the opening 130H.

In this case, at least one surface of the upper electrode 145 in contact with the dielectric layer 143 may be formed in an uneven shape corresponding to the profile of the dielectric layer 143.

As a result, the capacitor 140 including the lower electrode 141, the dielectric layer 143, and the upper electrode 145 may be completed. Since the capacitor 140 is formed to have a sidewall profile protruding in a concave-convex shape as described above, the effective area of the capacitor may increase. Therefore, the capacity of the capacitor can be further improved, and the performance of the semiconductor memory device can be improved. In addition, according to an embodiment of the present invention, it is possible to maximize the capacitor capacity by appropriately adjusting the layout of the capacitor without adding a separate process, there is an advantage in the process.

Thereafter, forming wirings to enable input and output of electrical signals of the semiconductor memory device according to process steps well known to those skilled in the art of forming a semiconductor memory device, and forming a passivation layer on the substrate. And packaging the substrate to complete the semiconductor device. These subsequent steps are outlined in order to avoid obscuring the present invention.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the method of manufacturing the semiconductor memory device according to the present invention, the capacitance of the semiconductor memory device can be improved while the process is simple.

Claims (3)

A first interlayer insulating layer formed on the semiconductor substrate and having a storage node contact formed therein; A second interlayer insulating film formed on the first interlayer insulating film and having an opening having sidewalls protruding in an uneven shape; And A lower electrode conformally formed on the bottom and sidewalls of the opening to have substantially the same profile as the sidewall of the opening, and conformally formed on the lower electrode according to the profile of the lower electrode in contact with the storage node contact. And a capacitor including a dielectric layer and an upper electrode formed on the dielectric layer. Forming a first interlayer insulating film on the semiconductor substrate, A storage node contact is formed in the first interlayer insulating layer, Forming a second interlayer insulating film on the first interlayer insulating film, Sidewalls protruding in a concave-convex shape in the second interlayer insulating layer to form an opening exposing an upper surface of the storage node contact; Conformally formed on the bottom and sidewalls of the opening to form a lower electrode having substantially the same profile as the sidewall of the opening and in contact with the storage node contact, Conformally forming a dielectric film on the lower electrode according to the profile of the lower electrode, Forming an upper electrode on the dielectric layer. The method of claim 2, wherein forming the opening Forming a mask pattern having a concave-convex shape on a sidewall of the second interlayer insulating film, And patterning the second interlayer insulating layer using the mask pattern as an etch mask to expose an upper surface of the storage node contact.

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